JP2003163352A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is capable of preventing breakdown of a semiconductor element even when a high-frequency surge is applied. <P>SOLUTION: In a peripheral high voltage breakdown section, a pn junction section by a p<SP>+</SP>-type contact region 22 electrically connected to an emitter electrode 11 and an n<SP>-</SP>-type layer 1B is formed in a surface section of an n<SP>-</SP>-type layer 1B. By forming the pn junction section which has a larger impurity gradient, that is, a lower breakdown voltage, than that of a pn junction section by a p-type well 3, a p-type base region 4, and the n<SP>-</SP>-type layer 1B in a cell section, the pn junction section having a larger impurity gradient is broken down earlier than the cell section when a high-frequency surge is applied, reducing a breakdown current flowing into a semiconductor element. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a power element such as a MOSFET or an insulated gate bipolar transistor (hereinafter referred to as an IGBT).

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device provided with a power element such as an IGBT, a means for improving a surge resistance is formed on an outer peripheral portion.

FIG. 6 shows an example of a cross section of a conventional semiconductor device having an IGBT. This semiconductor device has a substantially quadrangular shape when viewed from above and has four straight line portions and four corner portions. FIG. 6 shows a cross section of the semiconductor device cut in a direction perpendicular to one side. This is an example. The right side portion of FIG. 6 is a part of a region in which a plurality of semiconductor elements are formed, and is hereinafter referred to as a cell portion. Further, a portion on the left side of the cell portion is an outer peripheral breakdown voltage portion formed on the outer periphery of the cell portion.

In the semiconductor substrate J1, the p ⁺ type substrate J1
An n ⁻ type layer J1B is formed on A. In the cell portion, the p-type well J3 is formed in the surface layer portion of the n ⁻ -type layer J1B.

In the outer periphery breakdown voltage portion, the n ^-- type layer J1B is formed.
An outer peripheral p-type well J13 is formed on the surface layer portion of the. n
^An outermost peripheral p-type well J14 having a junction depth shallower than that of the outer peripheral p-type well J13 is formed by overlapping a part of the outer peripheral p-type well J13 of the ⁻ type layer J1B away from the cell portion. A plurality of field plates J1 are formed on the field oxide film J16 formed on the surface of the n ⁻ type layer J1B.
7a to J17d are formed outside the outermost peripheral p-type well J14. Further, Zener diodes J18a to J18c formed of polysilicon or the like are arranged between the plurality of field plates J17a to J17d, respectively, and these are electrically connected.
The field plate 17a has a gate wiring J19.
And the field plate 17d is connected to the n ⁺ type region J
It is connected to 15.

In this semiconductor device, the outer peripheral p-type well J1
3, outermost p-type well J14, and field plate J1
7a to J17d alleviate the electric field gathering on the outer peripheral side of the cell portion. In addition, Zener diode J18a
.. to J18c, the Zener diodes J18a to J18c are broken down when a high voltage surge of a certain voltage or more is applied between the collector and the emitter of the semiconductor element, and the gate electrode J7 is provided via the gate wiring J19. The element is turned on by applying a voltage to it, and the surge is absorbed when the element is on.

[0007]

Even if the above-mentioned Zener diodes J18a to J18c are provided in the outer periphery breakdown voltage portion, the gate electrode J7 is not sufficiently charged when a high frequency surge is applied to this IGBT. For this reason, the surge cannot be absorbed in the ON state of the element as described above. Therefore, in this case, p of the cell part is
Outermost p-type well J on the bottom surface of the well J3
The 14 edges are broken down at the same time to absorb the surge.

However, for example, in a quadrangular semiconductor device, the outer periphery breakdown voltage portion is formed in a straight line shape in a straight line portion along a side of the semiconductor device and in a curved shape in a corner portion of the semiconductor device. Normally, the breakdown voltage of the straight portion and the corner portion of the corner portion is lower than that of the straight portion. Therefore, when a high-frequency surge is applied, the outer circumference breakdown voltage portion of the outermost p-type well J14 of the corner portion is exposed. Since the breakdown occurs locally in the edge part, the surge amount that can be absorbed is limited. Therefore, a surge that cannot be absorbed by the outer peripheral breakdown voltage portion must be absorbed by the cell portion, and if the breakdown current flowing in this cell portion is larger than the withstand capacity of the semiconductor element, the semiconductor element will be destroyed.

In view of the above points, an object of the present invention is to provide a semiconductor device capable of preventing the destruction of a semiconductor element even when a high frequency surge is applied.

[0010]

In order to achieve the above object, in the invention according to claim 1, the breakdown voltage region has a pn junction between the first conductivity type semiconductor layer and the second semiconductor region. The pn junction has a larger impurity gradient than the pn junction formed by the semiconductor layer and the first semiconductor region, and is designed to be broken down first when a surge is applied. .

In this way, in the breakdown voltage region, the impurity gradient is larger than that of the pn junction formed by the first conductivity type semiconductor layer and the first semiconductor region, that is, the breakdown voltage p is low.
Since the n-junction is formed, when a surge is applied, the pn-junction can be broken down prior to the region where the semiconductor element is formed. As a result, the breakdown current flowing through the semiconductor element can be reduced, so that the breakdown of the semiconductor element due to the breakdown current can be prevented.

The pn junction portion of the breakdown voltage region may be formed, for example,
As described above, the semiconductor layer of the first conductivity type and the second semiconductor region of the second conductivity type can be formed. Further, according to claim 3, the first conductivity type semiconductor region (50) is formed between the first conductivity type semiconductor layer and the second semiconductor region, and has a higher impurity concentration than the first conductivity type semiconductor layer. And the second semiconductor region.

According to a fourth aspect of the present invention, the pn of the breakdown voltage region is
The current density of the breakdown current flowing in the pn junction can be reduced by making all the junction surfaces of the junction flat so as to reduce current concentration. This allows
The reliability of the region near the pn junction portion against breakdown due to the breakdown current can be improved.

Further, for example, in the fifth aspect, the second semiconductor region is directly electrically connected to the metal electrode so that the breakdown occurs at the pn junction of the breakdown voltage region. Claim 6
Then, the second semiconductor region is electrically connected to the metal electrode via the metal layer. In the claim 7, in the breakdown voltage region, the impurity concentration is lower than that of the second semiconductor region (44) in the surface layer portion of the semiconductor layer, and the second conductivity type third electrode electrically connected to the metal electrode (11). The semiconductor region (43) is formed, and the second semiconductor region forming the pn junction is the third semiconductor region.
It is electrically connected to the metal electrode via the semiconductor region.

The reference numerals in parentheses of the above-mentioned means indicate the correspondence with the concrete means described in the embodiments described later.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 shows a partial cross section of a semiconductor device having an IGBT to which an embodiment of the present invention is applied. The right side portion of FIG. 1 is the cell portion, and the portion on the left side of the cell portion is the outer periphery breakdown voltage portion formed on the outer periphery of the cell portion.

In the semiconductor substrate 1, the n ⁻ type layer 1B is formed on the p ⁺ type substrate 1A. This semiconductor substrate 1
Has a back surface 1a on the p ⁺ type substrate 1A side and a main surface 1b on the n ⁻ type layer 1B side. The collector electrode 2 is formed on the back surface 1a.

In the cell portion, on the main surface 1b side of the semiconductor substrate 1, a p-type well 3 is formed in the surface layer portion of the n ^-- type layer 1B, and the junction depth is shallower than the p-type well 3.
A p-type base region 4 is formed so as to overlap with the p-type well 3. Further, an n ⁺ type source region 5 is formed inside the p type base region 4. A gate electrode 7 made of polysilicon or the like is provided on the main surface 1b of the semiconductor substrate 1 via a gate insulating film 6. And
The p-type base region 4 sandwiched between the n ⁺ -type source region 5 and the n ⁻ -type layer 1B located under the gate electrode 7 serves as a channel region 8.

Of the surface layer of the p-type base region 4,
n ⁺ on the opposite side of the channel region 8 for type source region 5 p ⁺ -type region 9 overlaps with the n ⁺ -type source region 5 is formed. Then, B formed on the surface of the n ⁻ -type layer 1B
A is formed on the interlayer insulating film 10 made of PSG or PSG or the like.
An emitter electrode 11 made of an l-alloy or the like is provided.
The emitter electrode 11 passes through the contact hole 12 formed in the interlayer insulating film 10 and then the n ⁺ type source region 5 and p ⁺
It is electrically connected to the mold region 9.

As described above, the p-type base region 4, the n ⁺ -type source region 5, and the p ⁺ -type region 9 are included, and the emitter electrode 11 on the p ⁺ -type region 9 and the p-type base region 4 are The structure having the gate electrode 7 on the channel region 8 of 1 is defined as one cell, and the cell portion has a configuration in which a plurality of these are installed.

On the other hand, in the outer peripheral breakdown voltage portion, an outer peripheral p-type well 13 having the same junction depth as the p-type well 3 is formed around the outermost peripheral cell in the surface layer portion of the n ⁻ type layer 1B. Then, an outermost peripheral p-type well 14 that is on the side away from the cell portion with respect to the outer peripheral p-type well 13 and overlaps a part of the outer peripheral p-type well 13 and has the same junction depth as the p-type base region 4 is formed. Has been formed. An n ⁺ type contact region 15 is formed on the outermost peripheral side of the surface layer portion of the n ⁻ type layer 1B.

A field oxide film 16 is formed on the n ^-- type layer 1B.
6, field plates 17a to 17d of polysilicon, Al, or the like are formed between the outer peripheral side end of the outermost peripheral p-type well 14 and the cell side end of the n ⁺ type contact region 15, and the field plate 17a is formed. Zener diodes 18a to 18c made of polysilicon or the like are formed between the respective layers 17d to 17d, and these are electrically connected. Further, the interlayer insulating film 10 is formed on the field oxide film 16. A gate wiring 19 is provided on the interlayer insulating film 10, and the gate wiring 19 is electrically connected to the field plate 17a through a contact hole 20 formed in the interlayer insulating film 10. Further, an equipotential plate 21 is provided on the outermost peripheral side on the interlayer insulating film 10. The equipotential plate 21 is electrically connected to the field plate 17d and the n ⁺ type contact region 15.

Here, the outer peripheral p-type well 13 of the outer peripheral pressure-resistant portion.
The structure of the region in which is formed will be described. The outer peripheral p-type well 13 is the outer peripheral p-type well 13a formed on the cell side.
And the outer peripheral p-type well 1 formed on the outer peripheral side so that the width from the cell portion toward the outer periphery is wider than the outer peripheral p-type well 13a.
3b and. And these outer perimeter p
A p ⁺ type contact region 22 is formed in the surface layer portion of the n ⁻ type layer 1B so as to overlap with both of the type wells 13a and 13b. This p ⁺ type contact region 22 has an outer periphery p
The emitter electrode 11 extending up to the mold well 13 is electrically connected through a contact hole 23 formed in the interlayer insulating film 10.

That is, in the present embodiment, the outer periphery withstanding voltage portion is
The structure is such that a pn junction portion is formed by the p ⁺ type contact region 22 and the n ⁻ type layer 1B.

Since the p ⁺ -type contact region 22 has a higher impurity concentration than the outer peripheral p-type well 13, the p-type well 3 and the p-type base region 4 in the cell portion, the pn junction is the outer peripheral p-type well 13. The impurity gradient is larger than that of the pn junction formed by the n ⁻ type layer 1B and the pn junction formed by the n ⁻ type layer 1B and the p type well 3 or the p type base region 4 in the cell portion. That is, the p ⁺ type contact region 22 and the n ⁻ type layer 1
The junction with B has a lower breakdown voltage than other regions.

Therefore, when a high frequency surge is applied, a breakdown can be caused at this junction before the cell portion, and a breakdown current can flow as shown by the arrow in FIG. As a result, the breakdown current flowing in the cell portion can be reduced, and the breakdown of the semiconductor element due to the breakdown current can be prevented.

Further, unlike the conventional case, the outer peripheral p-type well 13 is not divided into two, but p ^{+ +} is provided inside the outer peripheral p-type well 13.
In the structure in which the type contact region 22 is formed, the breakdown current flows from the edge portion of the outermost peripheral p-type well 14 through the surface layer portion of the outer peripheral p-type well 13 to the emitter electrode 11 through the contact hole 23. For this reason, the outer peripheral p-type well 13 is a resistance component to the breakdown current, although slightly, and the amount of the breakdown current is suppressed. Further, depending on the current density of the breakdown current, the outer peripheral p-type well 13 may be destroyed. On the other hand, in the present embodiment, the p ⁺ type contact region 22 has the emitter electrode 1
Since it is electrically directly connected to 1, the breakdown current flows as shown by the arrow in the figure without passing through the outer peripheral p-type well 13. Therefore, more breakdown current can be made to flow through the pn junction than in the conventional case, and the breakdown current flowing in the semiconductor element can be reduced. Further, it is possible to prevent the breakdown of the outer peripheral p-type well 13 due to the breakdown current.

The present embodiment further has the following effects. Since the pn junction portion having a large impurity gradient is formed on the cell portion side of the outer peripheral p-type well 13 of the outer peripheral breakdown voltage portion, it is possible to break down even the linear portion of the semiconductor device when a surge is applied. This makes pn
The current density of the breakdown current flowing in the junction can be reduced. In addition, a planar pn that does not include an edge portion formed by the p ⁺ type contact region 22 and the n ⁻ type layer 1B.
Since the junction surface 22a is formed, the breakdown current can flow to the planar pn junction surface 22a.
In this case, the area through which the breakdown current flows is larger than that in the case where the breakdown current flows, and the current density can be reduced. As a result, it is possible to enhance the reliability of the breakdown of the region near the pn junction where the breakdown current flows due to the breakdown current.

In the above embodiment, the outer peripheral p-type wells 13a and 13b are formed in the outer peripheral withstand voltage portion, but the outer peripheral p-type well 13a may be omitted. A cross-sectional view of the semiconductor device at this time is shown in FIG. In this case, the p ⁺ type contact region 22 is
The pn junction between the p ⁺ -type contact region 22 and the n ⁻ -type layer 1B is formed not only on the planar bottom face, but also on the edge portion. Since the electric field is concentrated at the edge part, p
The breakdown voltage of the edge portion of the ⁺ type contact region 22 becomes lower than that in the case of FIG. 1, and the breakdown can be more positively made at this edge portion.

From this, the shape of the pn junction having a large impurity gradient can be determined according to the purpose. That is, in the case of more positively breaking down in the outer breakdown voltage portion, the pn junction has a structure having an edge portion, and in the case of increasing the reliability of breakdown of the pn junction due to the breakdown current. , This pn
It suffices if the joining portion has a planar structure having no edge portion.

The semiconductor device to which this embodiment is applied is
In a conventional semiconductor device manufacturing process, an outer peripheral p-type well
By changing the mask pattern when forming J13
Peripheral p-type wells 13a, 13b can be formed
It In the present embodiment, p having such a large impurity gradient is used.
Forming the n-junction part in the outer breakdown voltage part, not in the cell part
To form this pn junction regardless of the cell structure.
And restricts the pattern design of the cell part.
There is no gain. Therefore, the degree of freedom in designing the cell section is increased.
Can be large. (Second Embodiment) A second embodiment of the present invention is applied to FIG.
A sectional view of the semiconductor device is shown. In this embodiment, the perimeter
In the withstand voltage portion, the conventional outer peripheral p-type well J13 of FIG.
An outer peripheral p-type well 33 having a similar shape is formed. This
Of the outer periphery p-type well 33 below the contact hole 23
To a region having a depth equivalent to that of the outer peripheral p-type well 33.
The wrench 34 is formed, and the trench 34 is further tapped.
The contact plug 35 is formed of
There is. Then, p near the bottom surface of the trench 34 ⁺Type
The contact region 32 is formed so as to overlap the outer peripheral p-type well 33.
Formed, p⁺Mold contact regions 32 and n^-With the mold layer 1B
A pn junction is formed. Also, p⁺Type contact
The emitter region 32 is connected to the emitter electrode via the contact plug 35.
It is electrically connected to the pole.

As described above, the p ⁺ type contact region 32 and the n ⁻
Pn having an impurity gradient larger than that of the cell portion due to the mold layer 1B
By forming the junction near the bottom surface of the trench 34, when a high frequency surge is applied, the pn junction can also be broken down prior to the cell portion, as shown by the arrow in FIG. Breakdown current can flow. Therefore, the breakdown current flowing through the cell portion can be reduced, and the breakdown of the semiconductor element due to the breakdown current can be prevented.

Also in this embodiment, since the p ⁺ type contact region 32 is electrically connected to the emitter electrode 11 via the contact plug 35, the breakdown current does not pass through the outer peripheral p type well 33. Flowing. Therefore, more breakdown current can be made to flow through the pn junction than in the conventional case, and the breakdown current flowing in the semiconductor element can be reduced.

In addition to the planar bottom surface of the p ⁺ -type contact region 32, the pn junction between the p ⁺ -type contact region 22 and the n ⁻ -type layer 1B is formed not only at the edge portion. Since the electric field is concentrated at the edge portion, it is possible to break down the edge portion earlier than the cell portion. This also makes it possible to reduce the breakdown current flowing through the semiconductor element.

Further, since the pn junction having a large impurity gradient is formed on the cell portion side of the outer peripheral p-type well 33, the linear portion of the semiconductor device can be broken down when a surge is applied. As a result, the current density of the breakdown current flowing in the pn junction can be reduced, and the reliability of the breakdown of the pn junction due to the breakdown current can be improved.

Incidentally, such a structure has a conventional semiconductor device.
The outer peripheral p-type well 33 was formed in the manufacturing process of
After that, the trench 34 is formed, and then ion implantation is performed.
P ⁺Forming a mold contact region 32, and further contact
Formed by adding a step of forming the top plug 35
be able to. (Third Embodiment) FIG. 4 shows a semiconductor device to which the present embodiment is applied.
FIG. In the outer pressure resistant part, n ^-Table of mold layer 1B
The conventional peripheral p-type wells J13 and p shown in FIG.⁺Type control
An outer peripheral p-type well 43 having the same configuration as the tact area J22,
p⁺A mold contact region 22 is formed. That
Different from the conventional one, the p-type well 3 and the p-type base region
4. Outermost, where the impurity concentration is higher than that of the outer peripheral p-type well 43
Lap p⁺The mold well 44 is on the outer peripheral side of the outer peripheral p-type well 43,
It is formed so as to overlap the outer peripheral p-type well 43.

In this embodiment, since the impurity gradient is larger than that of the pn junction formed with the n ^-- type layer 1B in the cell portion and the outer peripheral p-type well 43, the breakdown voltage of the outermost peripheral p ⁺ -type well 44 is lowered. Can be made. Also, this outermost p ⁺
Since the type well 44 has a higher impurity concentration than that of the conventional outermost p-type well J14, the junction depth is shallower than that of the conventional type well.
The radius of curvature of the edge portion is smaller than in the conventional case. Since the radius of curvature is small, when the high frequency surge is applied, electric charges are concentrated around the edge portion, and the electric field strength at the edge portion becomes larger than that in other regions. From these things, when a high frequency surge is applied, it is possible to break down in the outermost peripheral p ⁺ type well 44 earlier than before. As a result, the breakdown current flowing through the semiconductor element can be reduced as compared with the conventional case.

The semiconductor device to which this embodiment is applied has the outermost peripheral p-type well J14 in the conventional manufacturing process.
Is formed by ion implantation at the same time as the p-type base region J4. For example, when the p ⁺ -type contact region 22 is formed by ion implantation, the outermost peripheral p ⁺ -type well 44 is formed at the same time. It can be obtained by changing to. (Fourth Embodiment) FIG. 5 is a sectional view of a semiconductor device to which the fourth embodiment of the present invention is applied. In Figure 5, the outer peripheral withstand voltage portion, the outer peripheral p-type well 13a in FIG. 1, 13b similar to the outer periphery p ⁺ -type well 53a in the position, 53b are formed respectively, the outer peripheral p ⁺ -type well 53a, between the 53b p ⁺
A mold contact region 22 is formed. And p ⁺
An n ⁺ type region 50 is formed below the type contact region 22.

The surface concentrations of these regions are, from the highest, the p ⁺ type contact region 22 and the outer peripheral p ⁺ type well 53.
The order is a, 53b, and n ⁺ type region 50. The semiconductor device having such a structure can be obtained by changing the process of forming the outer peripheral p-type well J13 by ion implantation as follows in the conventional semiconductor device manufacturing process. For example, the outer peripheral p ⁺ -type wells 53a and 53b are formed so that the p-type impurity concentration becomes 1 × 10 ¹⁸ cm ⁻³ . Next, the n ⁺ -type region 5 is adjusted so that the n-type impurity concentration becomes 5 × 10 ¹⁶ cm ^−3.
Form 0. After that, the p-type impurity concentration is 1 × 10 ¹⁹ c
The p ⁺ type contact region 22 is formed so as to have m ⁻³ .

[0040] In this embodiment, by thus the p ⁺ -type contact region 22 and n ⁺ -type region 50, the impurity gradient than the first embodiment is a large pn junction is formed, n ⁺
The n ⁻ type layer 1B is connected to the mold region 50, and the emitter electrode 11 is connected to the p ⁺ type contact region 22.

In this case, since the breakdown voltage of the pn junction is lower than that in the first embodiment, when a high frequency surge is applied, the pn junction can be broken down earlier than in the first embodiment. it can. From this,
The effect of reducing the breakdown current flowing in the cell portion becomes higher.

Also in this embodiment, the emitter electrode 11 is electrically directly connected to the p ⁺ -type contact region 22, and the junction surface of the pn junction does not include an edge portion and is planar. And the pn junction portion is formed on the cell portion side of the outer peripheral p ⁺ type well 53, the same effect as that of the first embodiment can be obtained. (Other Embodiments) It is also possible to combine the first embodiment and the third embodiment. Although not shown, the first
As in the third embodiment, a pn junction having an impurity gradient larger than that of the cell portion is arranged under the contact hole 23, and overlaps with the outer peripheral p-type well 43 as in the third embodiment to overlap the outermost peripheral p ^+.
The mold well 44 may be formed.

The pn formed in the cell portion in this way
By forming a plurality of pn junctions having a larger impurity gradient than the junctions in the outer breakdown voltage portion, the breakdown current flowing through the semiconductor element can be further reduced. The second
The embodiment and the fourth embodiment can be combined.

Further, in the above-mentioned first to fourth embodiments,
Although the field plate and the Zener diode are provided in the outer peripheral withstand voltage portion in addition to the outer peripheral p-type well 11, the shape and arrangement thereof may be other than those in the above-described embodiment. Further, the pressure resistance means is not limited to these, and other general pressure resistance means such as a guard ring may be formed.

In the first to fourth embodiments, the pn junction having a larger impurity gradient than that of the cell portion is formed in the outer breakdown voltage portion so as not to reduce the area of the cell portion. It may be formed in other than the withstand voltage portion. That is, such a pn is provided between the semiconductor elements.
A region having a joint portion is formed. This also makes it possible to reduce the breakdown current flowing through the semiconductor element, so that the breakdown of the semiconductor element due to the breakdown current can be prevented.

Further, in each of the above embodiments, an n-channel type I in which the first conductivity type is n-type and the second conductivity type is p-type.
Although the description has been given by taking the GBT as an example, the present invention can be applied to a p-channel type IGBT in which the conductivity type of each constituent element is reversed.

In each of the above embodiments, the case where one embodiment of the present invention is applied to the semiconductor device having the planar vertical IGBT is explained, but the present invention is applied to the semiconductor device having the trench gate type IGBT. May be applied. Further, the present invention may be applied to a semiconductor device including a MOSFET in which the semiconductor substrate 1 and the semiconductor layer 2 have the same conductivity type, instead of the IGBT in which the semiconductor substrate 1 and the semiconductor layer 2 have different conductivity types. .

In the first to third embodiments, the n ^-- type layer 1B corresponds to the first conductivity type semiconductor layer and the first conductivity type semiconductor region. In the first and second embodiments, the p ⁺ type layer is used. The contact regions 22 and 32 correspond to the outermost peripheral p ⁺ type well 44 in the third embodiment as the second semiconductor region.

In the fourth embodiment, the n ^-- type layer 1B corresponds to the first conductivity type semiconductor layer, the n ⁺ type region 50 corresponds to the first conductivity type semiconductor region, and the p ⁺ type contact region 22 corresponds to the first conductivity type semiconductor region. Two
It corresponds to the semiconductor region.

In the first to fourth embodiments, the p-type well 3 and p-type base region 4 correspond to the first semiconductor region, and the emitter electrode 11 corresponds to the conductive layer.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor device to which a first embodiment of the present invention is applied.

2 is a cross-sectional view of a semiconductor device in which a part of the structure of FIG. 1 is modified.

FIG. 3 is a sectional view of a semiconductor device to which a second embodiment of the invention is applied.

FIG. 4 is a sectional view of a semiconductor device to which a third embodiment of the invention is applied.

FIG. 5 is a sectional view of a semiconductor device to which a fourth embodiment of the invention is applied.

FIG. 6 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

1 ... Semiconductor substrate, 1A ... p ⁺ type substrate, 1B ... n ⁻ type layer, 2
... collector electrode, 3 ... p-type well, 4 ... p-type base region, 5 ... n ⁺ type source region, 6 ... gate insulating film, 7 ... gate electrode, 9 ... p ⁺ type region, 10 ... interlayer insulating film, 11 …
Emitter electrode, 12 ... Contact hole, 13 ... Perimeter p
Type well, 14 ... Outermost peripheral p type well, 15 ... N ⁺ type contact region, 16 ... Field oxide film, 17 ... Field plate, 18 ... Zener diode, 19 ... Gate wiring, 20 ... Contact hole, 21 ... Equipotential plate , 22 ... P ⁺ type contact region, 23 ... Contact hole.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H01L 21/822 H01L 27/04 H 27/04

Claims (7)

[Claims] 1. A semiconductor layer (1) of the first conductivity type on the main surface side.
A semiconductor substrate (1) having B) and a first semiconductor region (3, 4) of a second conductivity type for forming a semiconductor element formed in a surface layer portion of the semiconductor layer. A second semiconductor layer formed on the surface layer portion so as to be separated from the first semiconductor region;
In a semiconductor device having a breakdown voltage region including a conductivity type second semiconductor region (22, 32, 44), the breakdown voltage region has a pn junction between the semiconductor layer and the second semiconductor region, The junction has a larger impurity gradient than the pn junction formed by the semiconductor layer and the first semiconductor region, and is designed to break down first when a surge is applied. apparatus. 2. The semiconductor device according to claim 1, wherein the pn junction portion of the breakdown voltage region is formed by the semiconductor layer and the second semiconductor region. 3. A first conductivity type semiconductor region (50) having an impurity concentration higher than that of the semiconductor layer is formed in the breakdown voltage region between the semiconductor layer and the second semiconductor region, The semiconductor device according to claim 1, wherein the pn junction is formed by the first conductivity type semiconductor region and the second semiconductor region. 4. The entire junction surface of the pn junction portion in the breakdown voltage region is flat so as to reduce current concentration, and the junction surface is flat. Semiconductor device. 5. The metal electrode (11) is provided on the main surface of the semiconductor substrate, and the second semiconductor region is directly electrically connected to the metal electrode.
The semiconductor device according to claim 4. 6. A metal electrode (11) formed on the main surface of the semiconductor substrate, and formed between the metal electrode and the second semiconductor region of the breakdown voltage region and electrically connected to the metal electrode. A semiconductor device according to claim 2, characterized in that the second semiconductor region is electrically connected to the metal layer. 7. A metal electrode (11) formed on a main surface of the semiconductor substrate and a surface layer portion of the semiconductor layer in the breakdown voltage region, the impurity concentration of which is higher than that of the second semiconductor region (44). A second semiconductor region (43) of a second conductivity type that is low and is electrically connected to the metal electrode;
The semiconductor region is electrically connected to the metal electrode via the third semiconductor region.
The semiconductor device according to.