JPH02178956A - Resin-sealed semiconductor device - Google Patents
Resin-sealed semiconductor deviceInfo
- Publication number
- JPH02178956A JPH02178956A JP63331533A JP33153388A JPH02178956A JP H02178956 A JPH02178956 A JP H02178956A JP 63331533 A JP63331533 A JP 63331533A JP 33153388 A JP33153388 A JP 33153388A JP H02178956 A JPH02178956 A JP H02178956A
- Authority
- JP
- Japan
- Prior art keywords
- internal substrate
- resin
- connection
- plating
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000007747 plating Methods 0.000 claims abstract description 10
- 239000004020 conductor Substances 0.000 claims abstract description 8
- 230000002093 peripheral effect Effects 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 238000000034 method Methods 0.000 abstract description 3
- 230000002411 adverse Effects 0.000 abstract description 2
- 230000000694 effects Effects 0.000 abstract description 2
- 210000001331 nose Anatomy 0.000 abstract 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract 1
- 230000004913 activation Effects 0.000 abstract 1
- 229910052802 copper Inorganic materials 0.000 abstract 1
- 239000010949 copper Substances 0.000 abstract 1
- 238000007772 electroless plating Methods 0.000 abstract 1
- 238000009713 electroplating Methods 0.000 abstract 1
- 238000011282 treatment Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止型半導体装置に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a resin-sealed semiconductor device.
従来の樹脂封止型半導体装置は、第３図に示すように、
内部基板４と外部リード２とが金属の接線細線７で接続
されているかスは、第４図に示すように、内部基板４と
外部リード２の一方又は相方に銅等の柔かい金属からな
る接続バンプ８を設げこれを使用して接続をとる構造を
有していた。The conventional resin-sealed semiconductor device, as shown in FIG.
The connection between the internal board 4 and the external lead 2 by a thin metal tangential wire 7 is as shown in FIG. It had a structure in which bumps 8 were provided and connections were made using these bumps.
上述した従来の樹脂封止型半導体装置の中で第３図に示
す接続細線によるものは、−本ずつ接続する為に非常に
時間がかかる、又接続した後に内部素子を搭載すると細
線の破壊を起す為にこの接続は内部素子を搭載した後に
行わなけれはならない。この為接続作業中に素子の汚染
、破壊等があり、歩留りが低いという欠点があった。Among the conventional resin-sealed semiconductor devices mentioned above, the one using the thin connection wires shown in FIG. This connection must be made after mounting the internal components in order to For this reason, there is a problem of contamination or destruction of the elements during the connection work, resulting in a low yield.
又、第４図に示す金、／／Ａ等の接続バンプにて接続す
るものは第３図の例と比へ作業時間的には速いかバンプ
の高さが高いと接続中に外部リードがずれて接続不良を
起す為バンプの高さ管理が非常に難しく歩留りを落とす
原因となっている。又内部基板に樹脂系の安価な材料を
使用すると接続する時のバンブをつぷず為の熱て内部基
板が破壊し、安い基板が使用圧きないという欠点があっ
た。Also, connections using gold, //A, etc. connection bumps shown in Figure 4 may be faster in terms of work time compared to the example shown in Figure 3, or if the height of the bumps is high, external leads may become loose during connection. Bump height management is extremely difficult because misalignment can cause connection failures, causing a drop in yield. Furthermore, if a cheap resin-based material is used for the internal board, the internal board will be destroyed by the heat generated by the bumps during connection, and the cheap board will not hold up well.
本発明の目的は、樹脂封止型半導体装置の歩留り及び信
頼性の改善にある。An object of the present invention is to improve the yield and reliability of resin-sealed semiconductor devices.
本発明は、半導体素子を搭載した内部基板と、前記内部
基板に設けられた配線導体に接続された外部リードとを
備えた樹脂封止型半導体装置において、前記外部リート
の先端か前記内部基板の周辺部に、前記配線導体に連結
する金属めっき層て固定されているというものである。The present invention provides a resin-sealed semiconductor device comprising an internal substrate on which a semiconductor element is mounted and an external lead connected to a wiring conductor provided on the internal substrate, in which a tip of the external lead is connected to the internal substrate. A metal plating layer connected to the wiring conductor is fixed to the peripheral portion.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の第１の実施例の断面図である。FIG. 1 is a sectional view of a first embodiment of the invention.
この実施例は、半導体素子１を搭載した配線基板様の内
部基板４と、内部基板４に設けられた配線導体（図示し
ない）に接続された外部リード２とを備えた樹脂封止型
半導体装置において、外部リード２の先端か内部基板４
の周辺部に、前述の配線導体に連結する金属めっき層５
て固定されているというものである。金属めっき層５の
形成方法は配線基板におけるスルホールの形成に準し、
適当な治具を用いて内部基板と外部リートを一部重ね合
せて固定し、ホ１〜リソグラフィー技術、表面活性化処
理、無電解めっき及び電解めっきを組合わせて厚さ３〜
８μｍの銅めっきを行なえばよい
しかる後、半導体素子の搭載及び封止を行うな第２図は
本発明の第２の実施例を示す断面図である。This embodiment is a resin-sealed semiconductor device comprising an internal substrate 4 like a wiring board on which a semiconductor element 1 is mounted, and external leads 2 connected to wiring conductors (not shown) provided on the internal substrate 4. , the tip of the external lead 2 or the internal board 4
A metal plating layer 5 connected to the above-mentioned wiring conductor is provided around the periphery of the
It is said that it is fixed. The method for forming the metal plating layer 5 is based on the formation of through holes in wiring boards,
Using an appropriate jig, the internal substrate and the external substrate are partially overlapped and fixed, and a thickness of 3.
After that, the semiconductor element is mounted and sealed. FIG. 2 is a sectional view showing a second embodiment of the present invention.
この実施例は内部基板の外部と接続すべき配線の一部に
接続穴５′を設けておき、外部リードの一端にも同様の
穴を設け、この両者の穴を密着さぜな状態で穴の内部に
めっきを行い基板と外部リードとを電気的に接続したも
のである。In this embodiment, a connection hole 5' is provided in a part of the wiring to be connected to the outside of the internal board, a similar hole is provided at one end of the external lead, and both holes are placed in close contact with each other. The inside of the board is plated to electrically connect the board and external leads.
すなわち、配線基板の上下接続と同じくスルホールて接
続されている。従って、機械的強度において第１の実施
例に優り、又接続作業を内部基板の形成作業の中に取り
込むことがてきるのて作業工数か少なくてすむ。That is, the connection is made through through holes, similar to the connection between the top and bottom of the wiring board. Therefore, it is superior to the first embodiment in terms of mechanical strength, and since the connection work can be incorporated into the process of forming the internal board, the number of man-hours can be reduced.
以上説明したように本発明は、内部基板と外部リー１〜
との接続が金属めっき層でなされているのて、従来の金
属細線での接続のように時間がかがることかなく製造で
き、又、素子を搭載する前に接続を完了している為に素
子への悪響かなく樹脂封止型半導体装置のニスｌ−ダウ
ン（歩留り向上）及び信頼性の向」二を図ることが出来
る。As explained above, the present invention has an internal board and an external lead 1 to
Since the connection is made with a metal plating layer, it can be manufactured without taking the time required to connect with conventional thin metal wires, and because the connection is completed before mounting the element. It is possible to reduce the varnish (yield improvement) and improve the reliability of resin-sealed semiconductor devices without adversely affecting the elements.
又従来のハンプ接続構造に比べ全て低温で作業出来る為
に内部基板に紙、樹脂等の安い材料を使用することか出
来る為、材料の選択範囲の拡大と共にコストタウンが行
なえる。勿論ずれも生しないので信頼性の向上を図るこ
とができる。In addition, compared to the conventional hump connection structure, all operations can be performed at a lower temperature, so cheap materials such as paper and resin can be used for the internal substrate, which allows for a wider selection of materials and lower costs. Of course, since no deviation occurs, reliability can be improved.
は従来技術の別の例を説明する断面図である。FIG. 2 is a sectional view illustrating another example of the prior art.
１−・・半導体素子、２・外部リート、３ ・封止樹脂
、４・・内部基板、５・・・金属めっき層、５・・・接
続穴、６・・・導電性細線、７・・・内部基板と外部リ
ートの接続細線、８・・・接続ハンプ。DESCRIPTION OF SYMBOLS 1-- Semiconductor element, 2- External lead, 3- Sealing resin, 4- Internal substrate, 5- Metal plating layer, 5- Connection hole, 6- Conductive thin wire, 7-.・Connection thin wire between internal board and external lead, 8...connection hump.
Claims (1)
られた配線導体に接続された外部リードとを備えた樹脂
封止型半導体装置において、前記外部リードの先端が前
記内部基板の周辺部に、前記配線導体に連結する金属め
っき層で固定されていることを特徴とする樹脂封止型半
導体装置。In a resin-sealed semiconductor device comprising an internal substrate on which a semiconductor element is mounted and an external lead connected to a wiring conductor provided on the internal substrate, a tip of the external lead is attached to a peripheral portion of the internal substrate, A resin-sealed semiconductor device, characterized in that it is fixed by a metal plating layer connected to the wiring conductor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63331533A JP2679197B2 (en) | 1988-12-29 | 1988-12-29 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63331533A JP2679197B2 (en) | 1988-12-29 | 1988-12-29 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02178956A true JPH02178956A (en) | 1990-07-11 |
| JP2679197B2 JP2679197B2 (en) | 1997-11-19 |
Family
ID=18244724
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63331533A Expired - Fee Related JP2679197B2 (en) | 1988-12-29 | 1988-12-29 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2679197B2 (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5895657U (en) * | 1981-12-23 | 1983-06-29 | 日本電気株式会社 | Lead frame for integrated circuits |
| JPH0286158A (en) * | 1988-09-22 | 1990-03-27 | Ibiden Co Ltd | Lead frame with wiring board and its manufacture |
-
1988
- 1988-12-29 JP JP63331533A patent/JP2679197B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5895657U (en) * | 1981-12-23 | 1983-06-29 | 日本電気株式会社 | Lead frame for integrated circuits |
| JPH0286158A (en) * | 1988-09-22 | 1990-03-27 | Ibiden Co Ltd | Lead frame with wiring board and its manufacture |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2679197B2 (en) | 1997-11-19 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |