JPH02178921A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02178921A JPH02178921A JP33333888A JP33333888A JPH02178921A JP H02178921 A JPH02178921 A JP H02178921A JP 33333888 A JP33333888 A JP 33333888A JP 33333888 A JP33333888 A JP 33333888A JP H02178921 A JPH02178921 A JP H02178921A
- Authority
- JP
- Japan
- Prior art keywords
- silica
- layer
- spin
- glass
- rosette
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 49
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 18
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims abstract description 6
- 229910001882 dioxygen Inorganic materials 0.000 claims abstract 2
- 239000011247 coating layer Substances 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 8
- 229910052787 antimony Inorganic materials 0.000 claims description 5
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 5
- 238000001035 drying Methods 0.000 claims 2
- 239000011521 glass Substances 0.000 abstract description 15
- 230000000694 effects Effects 0.000 abstract description 4
- 238000000859 sublimation Methods 0.000 abstract description 3
- 230000008022 sublimation Effects 0.000 abstract description 3
- 238000004017 vitrification Methods 0.000 abstract description 2
- LJCFOYOSGPHIOO-UHFFFAOYSA-N antimony pentoxide Inorganic materials O=[Sb](=O)O[Sb](=O)=O LJCFOYOSGPHIOO-UHFFFAOYSA-N 0.000 abstract 2
- 229910003849 O-Si Inorganic materials 0.000 abstract 1
- 229910003872 O—Si Inorganic materials 0.000 abstract 1
- ADCOVFLJGNWWNZ-UHFFFAOYSA-N antimony trioxide Inorganic materials O=[Sb]O[Sb]=O ADCOVFLJGNWWNZ-UHFFFAOYSA-N 0.000 abstract 1
- GHPGOEFPKIHBNM-UHFFFAOYSA-N antimony(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Sb+3].[Sb+3] GHPGOEFPKIHBNM-UHFFFAOYSA-N 0.000 abstract 1
- 230000008878 coupling Effects 0.000 abstract 1
- 238000010168 coupling process Methods 0.000 abstract 1
- 238000005859 coupling reaction Methods 0.000 abstract 1
- YEAUATLBSVJFOY-UHFFFAOYSA-N tetraantimony hexaoxide Chemical compound O1[Sb](O2)O[Sb]3O[Sb]1O[Sb]2O3 YEAUATLBSVJFOY-UHFFFAOYSA-N 0.000 abstract 1
- 238000009792 diffusion process Methods 0.000 description 28
- 239000010410 layer Substances 0.000 description 20
- 239000012535 impurity Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000002485 combustion reaction Methods 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000005416 organic matter Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、半導体装置の製造方法における、アンチモン
（Ｓｂ）拡散、詳しくは、ｓｂシリノドスピン・オン工
法のプロセスに関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to antimony (Sb) diffusion in a method of manufacturing a semiconductor device, and more specifically to the process of sb silinode spin-on method.
従来の技術
近年、半導体装置の製造方法において、拡散マスク上に
拡散すべき不純物をスピン・オン塗布し、選択拡散する
低コストな工法が多用されてきている。拡散不純物の一
つであるｓｂは、伯の不純物に比べ、オート・ドープ現
象が少ないため、特に埋め込み層形成に良く使用される
が、２ゾーン工法という、コストの極めて高い方法に依
らなければならなかったが、前記スピン・オン工法を用
いることで約１／３のコストで実施できるようになった
。BACKGROUND OF THE INVENTION In recent years, in semiconductor device manufacturing methods, a low-cost method of selectively diffusing impurities by spin-on coating of impurities to be diffused onto a diffusion mask has been frequently used. SB, which is one of the diffusion impurities, has less auto-doping phenomenon than dopant impurities, so it is often used especially for forming buried layers, but it requires an extremely expensive method called the two-zone construction method. However, by using the above-mentioned spin-on method, the cost can now be reduced to about 1/3.
以下に従来のｓｂシリカ・スピン・オン拡散工法につい
て説明する。従来のｓｂシリカ・スピン・オン工法は、
ｓｂを含有しているシリカ／有機物溶液（以下、ｓｂシ
リカ溶液と略記）を、シリコン（Ｓｉ）基板主表面上に
選択的に形成された拡散マスク上にスピン・オン塗布し
、カラス化した後、熱拡散する工法である。第３図は、
従来のｓｂスピン・オン拡散工法により製造されたＳｉ
基板の断面を示したものである。ここで、１はＳｉ基板
、２は８１基板主表面上に選択的に形成されたＳｉＯ２
の拡散マスク、３はスピン・オン塗布した後ガラス化さ
れたｓｂガラス層、４は拡散層である。The conventional sb silica spin-on diffusion method will be explained below. The conventional sb silica spin-on method is
A silica/organic solution containing sb (hereinafter abbreviated as sb silica solution) is applied by spin-on onto a diffusion mask selectively formed on the main surface of a silicon (Si) substrate, and then glassed. , is a construction method that uses heat diffusion. Figure 3 shows
Si manufactured by conventional sb spin-on diffusion method
It shows a cross section of the substrate. Here, 1 is a Si substrate, 2 is a SiO2 selectively formed on the main surface of the 81 substrate.
, 3 is a sb glass layer vitrified after spin-on coating, and 4 is a diffusion layer.
発明が解決しようとする課題
ところで、従来のｓｂスピン・オン拡散工法では、ロー
ゼットと一般的に呼ばれている結晶性の異物が発生し易
く、これは、前記拡散マスクを突き抜けて、本来拡散層
を形成しない領域く以下、非拡散領域と略記）に、拡散
層を作ってしまう。Problems to be Solved by the Invention However, in the conventional sb spin-on diffusion method, crystalline foreign matter commonly called rosettes are likely to occur, and these can penetrate through the diffusion mask and disintegrate into the diffusion layer. A diffusion layer is created in a region where a diffusion layer is not formed (hereinafter abbreviated as a non-diffusion region).
（以下、この現象を、不要拡散と略記。）又、拡散領域
にも発生し、この上にエピタキシャル層を形成するよう
な場合には、結晶欠陥を生じさせてしまう。これらの問
題は、いずれも半導体装置において、耐圧不良、リーク
不良として現れ、歩留まりを低下させる要因となる。か
つ、ｓｂは、ＡｓやＢと比較し、Ｓ】に対する固溶限が
低く、かつ、前記ｓｂカラス層からｓｂが昇華し易いた
め、拡散層のシート抵抗を下げにくいという問題もあっ
た。(Hereinafter, this phenomenon will be abbreviated as unnecessary diffusion.) It also occurs in the diffusion region, and when an epitaxial layer is formed thereon, it causes crystal defects. All of these problems appear in semiconductor devices as breakdown voltage defects and leakage defects, and become factors that reduce yield. In addition, sb has a lower solid solubility limit for S than As and B, and sb easily sublimates from the sb glass layer, so there is also the problem that it is difficult to lower the sheet resistance of the diffusion layer.
第３図中、５はローゼット、６は不要拡散層である。こ
の日−ゼット５については、ｓｂ−。In FIG. 3, 5 is a rosette and 6 is an unnecessary diffusion layer. For this day-Z5, sb-.
Ｓｉの化合物であり、極めてエツチング除去しに＜＜、
一般に、拡散層のシート抵抗を低くしようとすると発生
し易いということ以外、その発生メカニズム等はほとん
と解明されていない。It is a compound of Si and is extremely difficult to remove by etching.
In general, the mechanism by which this phenomenon occurs has not been fully elucidated, other than that it tends to occur when trying to lower the sheet resistance of the diffusion layer.
そのため、ローゼットの発生を制御するため、拡散層の
シート抵抗を低くてきす、用途が限定されてしまう、き
いう欠点を有していた。Therefore, in order to control the generation of rosettes, the sheet resistance of the diffusion layer must be lowered, which has the drawback of limiting its applications.
本発明は上記従来の問題点を解決するもので、前記シー
ト抵抗を約１０数Ωｃｍと十分低くてき、しかもローゼ
ットが発生しないｓｂシリカ・スピン・オン工法を提供
することを目的とする。The present invention solves the above-mentioned conventional problems, and aims to provide an sb silica spin-on method in which the sheet resistance can be sufficiently low to about 10-odd Ωcm, and rosettes do not occur.
課題を解決するための手段
この目的を達成するために本発明のｓｂシリカ・スピン
・オン工法は、ｓｂ塗布層に十分な０２を供給するプロ
セスを提供するものである。Means for Solving the Problems To achieve this object, the sb silica spin-on method of the present invention provides a process that supplies sufficient 02 to the sb coating layer.
すなわち、本発明の第１は、ｓｂシリノ１塗布層がｓｂ
カラス化してゆく過程で１気圧以上の０２のみ供給しな
がら、カラス化温度を印加するものである。That is, the first aspect of the present invention is that the sb silino 1 coating layer is sb
During the process of glassing, the glassing temperature is applied while supplying only 02 at a pressure of 1 atm or higher.
本発明の第２は、ｓｂシリカ塗布層と８１基板との界面
から加熱する製造方法である。The second aspect of the present invention is a manufacturing method in which heating is performed from the interface between the sb silica coating layer and the 81 substrate.
作用
本プロセスは、発明者らの研究結果、ｓｂカラス層に十
分な０２を供給してやることで、ｓｂカラス層中のｓｂ
の昇華性を抑制でき、かつ活性化できる。しかもローゼ
ットの発生を抑止できることが判明した。この理論的な
根拠はまだ明確になっていないが、ｓｂカラスが５ｂ２
０３，５ｂ２０５であり、また、ローゼットがｓｂ−〇
−３ｉの形であることから、ｓｂシリカ塗布層に十分な
０２を供給することて、ｓｂカラスが昇華性の強い５ｂ
２０３から昇華性のない５ｂ２０５の形に変わり、結合
が強固になるため、活性が高くなり拡散し易くなり、し
かも５ｂ−０−８ｉの結合にＯを向えにくくなる。すな
わち、ローゼットが発生しにくくなると推定している。Effect This process is based on the research results of the inventors, and by supplying sufficient 02 to the sb crow layer, the sb in the sb crow layer is reduced.
The sublimation property of can be suppressed and activated. Moreover, it was found that the occurrence of rosettes could be suppressed. The theoretical basis for this is not yet clear, but the sb crow is 5b2
03,5b205, and since the rosette is in the form of sb-〇-3i, by supplying sufficient 02 to the sb silica coating layer, the sb glass becomes 5b, which has strong sublimation properties.
203 changes to the non-sublimable 5b205 form, and the bond becomes stronger, resulting in higher activity and easier diffusion, and moreover, it becomes difficult for O to direct toward the 5b-0-8i bond. In other words, it is estimated that rosettes are less likely to occur.
実施例
以下本発明の実施例について、図面を参照しながら説明
する。第１図〜第２図は各本発明の一実施例で、第１図
は本発明１の製造プロセスを示しておりＳ】基板主表面
上のｓｂシリカ塗布層に、１気圧以」二の純酸素雰囲気
中て２００〜５０００Ｃの熱処理を加えてカラス化する
工程である。EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. Figures 1 and 2 show one embodiment of each of the present inventions, and Figure 1 shows the manufacturing process of present invention 1. This is a process of adding heat treatment at 200 to 5000 C in a pure oxygen atmosphere to make it glass.
以上のような製造プロセスを用いた場合について、以下
その作用・動作を説明する。ｓｂシリカ塗布層がｓｂカ
ラス化する途上、ポーラスな状態になるが、その時、０
２がｓｂシリカ塗布層に浸透し、拡散に依らず取入れさ
せることができるので０２を十分含んだ、しかも、ち密
なｓｂガラス層を作ることができる。In the case where the manufacturing process as described above is used, its function and operation will be explained below. While the sb silica coating layer becomes sb glass, it becomes porous, but at that time, 0
Since 02 can penetrate into the sb silica coating layer and be incorporated without relying on diffusion, it is possible to create a dense sb glass layer that sufficiently contains 02.
第２図は、本発明の第２の方法を実現するための製造装
置の一実施例である。ここで、７はカセット」二に並へ
られたＳｉ基板、８は前期カセット、９は熱伝導の良い
材料から成るプレート、１０は加熱のためのヒーター、
１１は石英等の材料から成るペルジャー １２は０２カ
スの注入口、１３は排気口である。本実施例では、排気
口１３より注入口１２の口径を大きくして、ヘルシャー
内の○２ガス圧を１気圧以−にに高めている。FIG. 2 shows an embodiment of a manufacturing apparatus for implementing the second method of the present invention. Here, 7 is a cassette, Si substrates arranged in two rows, 8 is a first cassette, 9 is a plate made of a material with good thermal conductivity, 10 is a heater for heating,
11 is a Pelger made of a material such as quartz; 12 is an inlet for 02 dregs; and 13 is an exhaust port. In this embodiment, the diameter of the inlet 12 is made larger than that of the exhaust port 13 to increase the ○2 gas pressure in the Hölscher to 1 atmosphere or more.
以」二のように構成された製造装置を、本発明の第１の
製造プロセスに適用した場合の作用・動作を以下に説明
する。Ｓ ｂシリカ溶液を塗布したＳｉ基板、ノ７セッ
Ｉ・に並へて乗せ、プレート」二に設置する。ペルジャ
ーを閉め、Ｑカス注入口より、純酸素を注入すると、排
気口の［コ径が注入口より小さいため、ヘルシャー内は
純酸素で満たされ、１気圧より高い圧力を持つようにな
る。この時点て、ヒーターに通電し、Ｓｉ基板を２００
〜５００℃の間の任意の温度まて昇温する。ところで、
ｓｂシリカ塗布層中には、有機物が含まれているが、こ
れがｓｂカラス化の過程で燃焼し、燃焼カスはｓｂガラ
ス塗布層中を拡散しながら外部に逃げてゆく。この時、
前記有機物がｓｂカラス中に残ると、ローゼットが発生
したり、炭素が拡散する不具合が起こるが、本実施例製
造装置では、Ｓｉ基板とｓｂシリノＪ塗布層界面から加
熱されるため、界面からカラス化が起こり、Ｓｉ基板表
層はポーラスな状態であるため、前記燃焼カスがｓｂカ
ラス中に取り残されることがない。The functions and operations when the manufacturing apparatus configured as described above is applied to the first manufacturing process of the present invention will be described below. Place the Si substrate coated with the Sb silica solution side by side on the plate, and set it on the plate. When the Pelger is closed and pure oxygen is injected from the Q-cass injection port, the diameter of the exhaust port is smaller than the injection port, so the inside of the Hölscher is filled with pure oxygen and has a pressure higher than 1 atmosphere. At this point, the heater is energized and the Si substrate is
Raise the temperature to any temperature between ~500°C. by the way,
The sb silica coating layer contains organic matter, which is burned during the sb glassing process, and the combustion residue escapes to the outside while diffusing in the sb glass coating layer. At this time,
If the organic matter remains in the sb glass, problems such as rosettes and carbon diffusion will occur, but in the manufacturing apparatus of this embodiment, heating is performed from the interface between the Si substrate and the sb silino J coating layer, so the glass is removed from the interface. Since the surface layer of the Si substrate is in a porous state, the combustion residue is not left behind in the sb glass.
発明の効果
以」二のように本発明の製造プロセスによれば、ｓｂシ
リカ塗布層形成〜ｓｂカラス層形成〜拡散の工程のうち
、ｓｂカラス層形成工程に関するもので、ｓｂガラス形
成時に、２００〜５００℃のガラス化に最適な加熱をお
こなう工程、及び、１気圧以上の圧力を有する純酸素雰
囲気中で前記加熱処理を行なう工程、ｓｂシリノ１塗布
層とＳ］基板界面より加熱する工程、を備えることによ
り、ローゼッＩ・の発生が少なく、かつ、低シートが得
られる優れた半導体装置の製造方法、詳しくは、ｓｂシ
リカスピン・オン工法を実現できるものである。Effects of the Invention According to the manufacturing process of the present invention, as described in ``2'', among the steps of sb silica coating layer formation to sb glass layer formation to diffusion, the process relates to the sb glass layer formation process, and when forming the sb glass, 200 A step of performing heating optimal for vitrification at ~500 ° C., a step of performing the heat treatment in a pure oxygen atmosphere having a pressure of 1 atmosphere or more, a step of heating from the interface of the sb silino 1 coating layer and the S] substrate, By providing this, it is possible to realize an excellent method of manufacturing a semiconductor device, in particular, the sb silica spin-on method, which reduces the occurrence of rosette I and provides a low sheet.
第１図は本発明の実施例における、半導体装置の製造方
法のプロセスを示すフロー図、第２図は同半導体装置の
製造方法で用いた製造装置の基本構成図、第３図は従来
のｓｂスピン・オン拡散工法によって製造された、半導
体装置のＳ】基板の断面図である。
］・・・・・・Ｓｉ基板、２・・・・・・拡散マスク、
３・旧・・ｓｂカラス層、４・・・・・・拡散層、５・
・・・・・ローゼッ］・、６・・・・・・不要拡散層、
７・・・・・・ツノセット」二に並へられたＳｉ基板、
８・・・・・・カセット、９・・・・・・プレーＩ・、
１゜・・・・・・加熱ヒータ、１１・旧・・ペルジャー
１２・・・・・・０２力ス注入口、１３・・・・・・
排気口。
代理人の氏名 弁理士 粟野重孝 はか１名第１図
第２図FIG. 1 is a flow diagram showing the process of a semiconductor device manufacturing method in an embodiment of the present invention, FIG. 2 is a basic configuration diagram of a manufacturing apparatus used in the semiconductor device manufacturing method, and FIG. 3 is a conventional SB 1 is a cross-sectional view of a substrate of a semiconductor device manufactured by a spin-on diffusion method. ]... Si substrate, 2... Diffusion mask,
3. Old... sb crow layer, 4... Diffusion layer, 5.
...Rozet]...6...Unnecessary diffusion layer,
7...Tsunoset" Si substrates arranged in two rows,
8...Cassette, 9...Play I...
1゜・・・Heater, 11・Old Pelger 12・・・・・・02 Force inlet, 13・・・・・・
exhaust port. Name of agent: Patent attorney Shigetaka Awano (1 person) Figure 1 Figure 2
Claims (2)
液を塗布した後に、前記アンチモン含有シリカ塗布層を
、１気圧以上の純酸素ガス雰囲気中で２００〜５００℃
に加熱乾燥する工程を備えたことを特徴とする半導体装
置の製造方法。(1) After applying an antimony-containing silica solution onto the main surface of a semiconductor substrate, the antimony-containing silica coating layer is heated at 200 to 500°C in a pure oxygen gas atmosphere of 1 atm or more.
1. A method for manufacturing a semiconductor device, comprising a step of heating and drying.
液を塗布した後に、前記アンチモン含有シリカ塗布層と
前記半導体基板界面から乾燥し始めるように熱を印加す
ることを特徴とする半導体装置の製造方法。(2) A method for manufacturing a semiconductor device, comprising applying an antimony-containing silica solution onto the main surface of a semiconductor substrate, and then applying heat so as to start drying from the interface between the antimony-containing silica coating layer and the semiconductor substrate. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33333888A JPH02178921A (en) | 1988-12-29 | 1988-12-29 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP33333888A JPH02178921A (en) | 1988-12-29 | 1988-12-29 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02178921A true JPH02178921A (en) | 1990-07-11 |
Family
ID=18264996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP33333888A Pending JPH02178921A (en) | 1988-12-29 | 1988-12-29 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02178921A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58117A (en) * | 1981-06-25 | 1983-01-05 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS63237411A (en) * | 1987-03-26 | 1988-10-03 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
-
1988
- 1988-12-29 JP JP33333888A patent/JPH02178921A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58117A (en) * | 1981-06-25 | 1983-01-05 | Fujitsu Ltd | Manufacture of semiconductor device |
| JPS63237411A (en) * | 1987-03-26 | 1988-10-03 | Oki Electric Ind Co Ltd | Manufacture of semiconductor device |
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