JPH02177330A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a structure where a conductive material which is superb in evenness is embedded within a field region by forming a groove part at a scheduled part for forming a field region, and forming a conductive material at the bottom of the groove part and an isolation material film on it. CONSTITUTION:An n-type embedded layer 202 is formed on a semiconductor substrate 201, an n-type semiconductor layer 203 is formed on it, and Si nitriding film patterns 204a, b and Si thermal oxidation film patterns 205a, b are formed on it. A groove part 206 is formed with it as a mask and an oxide film 207 is formed within it. The patterns 204a, b and 205a, b are eliminated and the Si nitriding film is accumulated. After that, resist patterns 208a-208d are formed, Si nitriding patterns 209a-209d are formed with the patterns 208a, b as a mask, and grooves 210a-210c are formed with them as a mask. B is impregnated and the patterns 208a, b are eliminated to form P<+> regions 211a-211c. An SiO2 film 212 is formed over the entire surface, is etched to the surface to form field regions 213 and 214, thus obtaining a bipolar LSI.

Description

[Detailed Description of the Invention] [Statement of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device, and in particular, a method for improving isolation technology between elements of bipolar or MOS type ICs, LSIs, etc. Regarding the manufacturing method.

(Prior Art) Conventionally, pn junction isolation has been used as a method for isolating elements in the manufacturing process of semiconductor devices, particularly bipolar ICs.

Selective oxidation is commonly used. This method will be explained below using a bipolar vertical npn transistor as an example.

First, as shown in FIG. 1(a), a high concentration n-type buried region 2 is selectively formed in a p-type substrate 1, and then,
An n-type semiconductor layer 3 is grown epitaxially, and a silicon acid film 4 of about 1,000 layers is formed for selective oxidation.
An oxidation-resistant silicon nitride film having a thickness of approximately 1000 nm is deposited thereon. Subsequently, the silicon oxide film 4 and the silicon nitride film 5 are patterned by photolithography to form silicon oxide film patterns 4a, 4b and silicon nitride film patterns 5.
Form a, 5b. Subsequently, the silicon oxide film patterns 4a, 4b and the silicon nitride film pattern 5a are formed.
, 5b as a mask, the n-type semiconductor layer 3 is coated with a thickness of approximately 500 nm.
About 0 people etched the silicon, and then the same pattern 4. a,
4b, 5a, 5b as masks, p-type regions 6a, 6 are formed by boron ion implantation method.
b (as shown in FIG. 1(C)). Next, thermal oxidation was performed in a steam or wet atmosphere to selectively grow silicon oxide films 7a to 7C with a thickness of about 1 μm (
(Illustrated in FIG. 1(d)). Subsequently, the silicon nitride film patterns 5a and 5b are removed using, for example, hot phosphoric acid, and boron ion implantation is performed on the region immediately below the silicon nitride film pattern 5a to form a base region 8.
Furthermore, an n-type region 9 that will become an emitter and an n-type region 10 for leading out the collector electrode are formed by arsenic ion implantation, and a contact window is formed in the silicon oxide film pattern 4a that has been formed in advance. After opening, emitter electrode 1. A vertical npn transistor was manufactured by forming an L base electrode I2 and a collector electrode 13.

(Illustrated in FIG. 1(e)). In this case, the device isolation of the npn transistor is performed by a field oxide film 7a having a thickness of about 1 μm.

7c and p-type head regions 6a, 6b, etc., but if the thickness of the n-type semiconductor layer 6 is about 1 to 2
If it is about μ, field oxidation by selective oxidation method can be brought into direct contact with the p-type substrate 1, and elements can be isolated. In addition, even when devices are directly isolated using a field oxide film, ion implantation of p-type impurities for channel stop is performed between the p-type substrate l and the field oxide film to prevent leakage current between devices. It is recommended that you perform a John.

However, the method of manufacturing bipolar ICs using the conventional selective oxidation method described above has various drawbacks as shown below.

FIG. 2 shows in detail the cross-sectional structure when field oxide films 7a and 7b are formed using Si, N, and patterns 5a and 5b as masks. However, in FIG. 2, the semiconductor layer 3 is not etched. Generally, in the selective oxidation method, the field oxide film 7b is 5isN4
It is known that it grows by digging into the area under the pattern 5a (region F in FIG. 2). This means that during field oxidation, the oxidizer is Si, a thin 5i0 layer under the N4 pattern 5a.
It consists of a so-called bird's beak portion D1 where the oxide film is formed due to diffusion through the field oxide film 7b, and a portion E where the thick portion of the field oxide film 7b extends laterally as well. For example, the length of F is approximately 1 μm when the thickness of the Si, N4 pattern 5a is 1000 μm, and the 5in2 film 4a below it is grown under the conditions of 1000 μm thick field oxide film 7b. Therefore, the width C of the field area is 5t3N, and the distance between patterns 5a and 5b is 1lI.
If iA is 2μ, then F is 1μ], so it cannot be made smaller than 4μ, which is a big hindrance to LSI integration. For this reason, recently, a method has been developed to suppress bird's beak (portion D in the figure) by increasing the thickness of the Si, N4 patterns 5a and 5b and thinning the underlying SiOJ film, and by increasing the thickness of the field oxide film 7b. Attempts have been made to reduce the thickness of the field oxide film and suppress the digging in of the field oxide film.

However, in the former case, the stress at the edge of the field increases and defects are more likely to occur, and in the latter case, there are problems such as a drop in field inversion voltage and an increase in wiring capacitance in the field part, and there are limits to the high density achieved by selective oxidation. be.

When the above-mentioned bird's beak or the like occurs, the following problems occur. This will be explained using the manufacturing process of a bipolar transistor by the conventional selective oxidation method shown in FIGS. 3(a) and 3(b).

As shown in FIG. 3(a), silicon oxide films 22a and 22b are formed on the surface of the semiconductor layer 2I, which will become the n-type collector region, by the conventional selective oxidation method, and using this oxide film as a mask, boron A p-type base region 23 was formed using the ion immobilization method.

Next, as shown in FIG. 3(b), an n-type emitter region was formed by a diffusion method or an ion implantation method. Here, the silicon oxide film 24 is an insulating film for taking out the electrode. The problems with the manufacturing method using the conventional selective oxidation method are mainly the shape of the so-called bird peaks of the silicon oxide films 22a, 22b, etc. formed, stress in the conductor region near the bird peaks, and stress. This is due to the occurrence of defects due to First, base area 2
In the shape of No. 3, the depth from the main surface of the conductor of the base bond by the boron ion fist implantation is C.

If the depth of the base junction directly below Bird Peak is D, then
Compared to C, the value of D is smaller by the thickness of the oxide film at Bird's peak. Furthermore, the surface of the silicon oxide film is etched during the etching process during the manufacturing process.
The value of D becomes even smaller. For this reason, if an Ag electrode for taking out the base is formed at the tip of the bird's peak, Ag will penetrate through the base region due to the reaction between Ag and silicon, causing device failure. Also, the base width of the transistor directly under the main surface of the semiconductor substrate is A.

Assuming that the base width directly below Bird Peak is B, the depth of the base at Bird Peak is shallow as described above, and the etching process during manufacturing causes the tip of Bird Peak to recede, and the width from the tip of Bird Peak to The depth of the emitter becomes deeper than other parts, and the stress and defects caused by the selective oxidation method cause abnormal diffusion of the emitter, and the depth of the emitter junction becomes deeper, resulting in a normal base width. Compared to A, the base width B immediately below the bird peak is smaller, which is undesirable because it causes a failure in the collector-emitter withstand voltage of the npn transistor. As described above, when the selective oxidation method is applied to bipolar ICs, it causes various device defects and degrades the quality of the devices.

For these reasons, the present applicant proposed a method for manufacturing a bipolar semiconductor device (for example, a vertical 'jJ n p n transistor) using the novel field chain acid forming means described below.

First, as shown in FIG. 4(a), a p-type semiconductor substrate 101
After selectively forming a buried layer 102 with a high concentration of n-type impurities and growing an n-type epitaxial semiconductor layer 103 to a thickness of about 2.5 μm on the buried layer 102, a resist layer 102 is formed on the surface of the semiconductor layer 103 by photolithography. Patterns 104a, 104
b, 104e was placed g. Resist 104a, 104b, 104 that has been subjected to conobaturing
Using c as a mask, the semiconductor layer 1.03 is anisotropically glued and active ion etched to form a p-type substrate 1.01.
By silicon etching until reaching E,
Grooves 105a and 105b having a width of about 1 μm and a depth of about 3 μm are formed to separate the n-type semiconductor layer 103 into islands (fourth
Figure (b) shown). At this time, due to the channel cut between the elements, pQ
It is preferable to form regions 108a and 108b.

Next, as shown in FIG. 4(C), a resist 104a is formed.

After removing 104b and 104c, CV D -S
iOx film 107 is formed into element isolation grooves 105a, 10
5b (approximately 5,000 people). At this time, CVD SiO2 is gradually deposited on the inner surface of the groove, and the grooves 105a and 105b are sufficiently filled, and the surface of the CVD-5in film +07 is almost flat. In addition, during this deposition, unlike selective oxidation, high-temperature and long-term thermal oxidation treatment is not required, so the p-type region! Rediffusion of [1[ia, l061+] hardly occurs. Next, CVD-5iO□ film 107
The entire surface of the silicon semiconductor layer 1, 03 was etched using ammonium fluoride until the portions of the silicon semiconductor layers 1, 03 other than the grooves 105a, 105b were exposed.

At this time, as shown in FIG. 4(d), only the thickness of the CVD-5ioz film 107 on the semiconductor layer 103 is removed.
CVD-5102 remains only in the trenches 105a and 105b, thereby forming field regions 107a and 107b buried in the semiconductor layer 103.

Next, a p#1 base region 1 is formed in the semiconductor region separated by the field region 107a and LO7b by boron ion implantation using a resist block method.
An insulating film 109 of approximately 3,000 layers is formed on the entire surface of the semiconductor layer, and diffusion windows for emitters and collectors are opened in this insulating film 109 by photolithography, and arsenic ion implantation is performed. n-type region 110. which becomes an emitter. N-type head area I that becomes the collector extraction part
form ll. Next, an opening for the p-type base region 108 is formed, an ARM electrode material is deposited on the semiconductor surface, and this electrode material is patterned by photolithography to form a base electrode 112, an emitter electrode 113, and a collector electrode 114. is formed to manufacture an npn bipolar transistor (as shown in FIG. 4(c)).

According to the method described above, it is possible to obtain a bipolar semiconductor device that exhibits the various effects described below.

(Since the area of the field region is determined by the area of the groove portion previously provided in the semiconductor layer, by reducing the area of the groove portion, it is possible to easily form the initial target fine field region. The device can be controlled.

(2) Since the depth of the field region is determined by the depth of the groove provided in the semiconductor layer regardless of the area, it is possible to arbitrarily select the depth, and to prevent current leakage between cables, etc. It is possible to obtain a high-performance bipolar semiconductor device that can be reliably blocked in the field region.

(3) After forming the fj region and selectively doping the channel stopper impurity into the groove, the impurity region is 11. Since it does not re-diffuse in the groove direction and reach the buried layer in the element formation region or the active region of the transistor, reduction of the effective element formation area is prevented.11. can. In this case, if the impurity is doped by ion implantation, the impurity ion implantation Iω can be formed at the bottom of the trench, and even if the ion implantation layer is re-diffused, it will not be present in the surface layer of the element formation region (active part of the transistor). Therefore, it is possible to prevent the effective element formation region from being reduced, and also to prevent the impurity region from interfering with the active region of the transistor.

(4) When the field region is formed by leaving the insulating material in all of the grooves, the substrate is flattened, so that it is possible to prevent breakage from occurring during the subsequent formation of electrode wiring.

As described above, the above method has many advantages. However, although it is possible to form an LSI using all narrow field regions, there are some difficulties when forming a wide field region. That is, the width of the field S
is determined by the trench width S, and in order to leave the insulating film in the trench, the insulating film needs to have a thickness (T) > 1/2 S, and when the field width is large, the insulating film is deposited quite thickly. There is a need. For example, in order to form a field with a width of 20 μm, the thickness of the insulating film must be 10 μm or more, and there are many difficult problems such as deposition time, film thickness, accuracy, and crack-free conditions. Furthermore, it is very difficult to form a field with a width of 200 μm (for example, the lower part of an AII bonding pad) using the above method. Therefore, if a wide field is required, first create a narrow field 10 according to the method described above, as shown in FIG.
After 7a, 107b, and IQ7c are buried, an insulating film (SiOz), for example, is deposited, and this insulating film is left partially by photolithography to form a wide field region 107'.

This method allows the formation of a wide field oxide film and overcomes most of the defects of selective oxidation.
One major drawback occurs. That is, a step is generated at the end of the wide field film 107' of IIJ in FIG. 5, and flatness is lost. In the case of the selective oxidation method, half of the field film is buried in the silicon semiconductor layer, but in this method, the field film thickness becomes a step as it is, so the step is larger than in the case of the selective oxidation method, making it difficult to perform microlithography near the wide field film. This was a major hindrance when needed.

(Problem to be solved by the invention @) As a result of further intensive research based on the above method, the present invention has been developed to provide a self-aligned line to the trench of the semiconductor layer, a surface on the same level as the main surface of the semiconductor layer, and a wide field. A method for manufacturing a semiconductor device that achieves high integration and high performance by establishing a method for forming a region, and a method for manufacturing a semiconductor device with a structure in which wiring made of a conductive material with excellent i1 flatness is embedded within the field area. It is intended to provide a method.

[Structure of the invention] (Means and effects for solving the problem) Hereinafter, Part 1 of the present application
A detailed description of the invention will be given below.

First, a mask material film is waved onto a semiconductor layer such as silicon, and then wide and narrow field region portions of the mask material film are removed by photolithography to form a mask pattern. Examples of the mask material film used here include a silicon nitride film or a two-layer film of a silicon oxide film and a silicon nitride film. Next, using this mask pattern, the semiconductor layer is selectively etched to a desired depth to form wide and narrow first trenches.

In this case, if a directional etching method such as reactive ion etching or ion milling is used as the etching means, it is possible to provide a groove portion with vertical or nearly vertical side surfaces. However, a groove with a tapered side surface may be formed, and by forming such a groove,
It becomes possible to fill the first separation material membrane, which will be described later, in a good shape.

Next, thermal oxidation treatment is performed using a mask pattern made of a silicon nitride film as an oxidation-resistant mask, and a first isolation material film made of oxide is selectively formed in the exposed first groove portion. In this case, if the mask pattern is formed of two layers, a thin silicon oxide film and a silicon nitride film, the stress applied to the semiconductor layer portion at the end of the mask pattern during thermal oxidation can be alleviated. In addition, with this method, the surface of the semiconductor layer and the surface of the first separation material film are brought to almost the same level by appropriately selecting the lacquer in the groove and the thickness of the thermal oxide film (first separation material film). The flatness can be improved.

Next, after removing the mask pattern, a narrow second
Form a groove. The second groove portion is formed near the contact between the first isolation material film and the semiconductor layer, and at a location in the semiconductor layer different from the isolation material film. In particular, in the method of the present invention, by removing the former portion using a directional etching method such as reactive ion etching or ion milling, it is possible to form a second groove portion with vertical or nearly vertical side surfaces. In the process, by filling this groove with a second separation material, a wide field region with little difference in pattern conversion can be formed.

Next, the second separating material is filled and embedded in the narrow second groove portion by the means described below.

(b) CVD an insulating material layer on the semiconductor layer including the second groove part
After depositing a film with a thickness sufficiently thicker than half the width of the trench by the D method, PVD method, etc., the insulating material (second isolation material) is etched until the surface of the semiconductor layer is exposed.
remain.

Top: As a self-insulating material, for example, S i 02Si3N
, or Ai' 20x, and in some cases, low-melting insulating materials such as phosphorus silicide glass (PSG), arsenic silicide glass (AsSG), and boron silicide glass (BSG) may be used. good. Note that prior to forming the insulating material, a channel stopper region or a p-type conductive region a may be formed in the semiconductor layer or the semiconductor substrate by selectively doping an impurity of the same conductivity type as the semiconductor substrate in the trench. Furthermore, prior to depositing the insulating material, the entire semiconductor layer having a groove, or at least a portion of the groove, may be oxidized or nitrided to grow an oxide film or a nitride film to an extent that the groove is not blocked.

By using these methods in combination, the obtained field insulating film is composed of a highly dense oxide film or nitride film in contact with the semiconductor layer in the trench and an insulating material formed by deposition, and the field insulating film is made up of an insulating material formed by deposition. The element isolation performance can be significantly improved compared to the one consisting of the following. Furthermore, after depositing the insulating material, the entire or part of the surface layer of the insulating film is doped with a low-melting substance such as boron, phosphorus, arsenic, etc., and the doped layer of the insulating film is melted by heat treatment, or A low-melting insulating material such as boron silicide glass (BSG) or phosphorus silicide glass (PSG) is applied on the whole or part of the insulating film.
G) Alternatively, arsenic silicide glass (A s S G) or the like may be deposited and this low-melting insulating film may be melted, or any other treatment may be performed. By adopting such a means, if the part corresponding to the first groove becomes concave due to the deposition conditions of the insulating material, the concave part can be filled and flattened, and as a result, the first groove can be flattened during subsequent etching. This has the effect of preventing the inconvenience of the insulating material remaining in the full part being below the level of the opening.

(b) A material that is converted into an oxide by oxidation treatment is deposited on the semiconductor layer including the narrow second groove by CVD, PVD, etc., and etched until the surface of the A7 conductor layer is exposed. After the material remains in the groove, a thermal oxidation treatment is performed to convert the remaining material into an oxide (second separation material). Examples of materials used here include polycrystalline silicon,
Amorphous silicon can be mentioned. Note that if at least the inside of the second groove is oxidized or nitrided prior to depositing the material to grow a thin oxide film or nitride film that does not block the groove, the material can remain in the groove. After this, the second separation material can be formed by oxidizing the exposed surface without oxidizing all of the remaining material.

By combining the oxide film (first separation material) remaining in the wide first trench with the remaining second separation material by means such as (a) and (b) described above, a wide field can be formed. A region is formed. A semiconductor device is manufactured by forming bipolar type elements, MO8 type elements, etc. on semiconductor layers separated by such wide and narrow field regions.

Therefore, in the main application of the first invention of the present application, a wide groove portion with a double or tapered side surface is provided in the semiconductor layer, and by thermal oxidation or the like, a layer with a thickness approximately the same as the depth of the groove portion is formed in the semiconductor layer. A wide field region is formed by forming a first isolation material, providing a second groove between the isolation material and the semiconductor layer near the side entrance of the groove, and filling this groove with the second isolation material. It's about doing. Therefore, according to the first invention of the present application, in addition to having the excellent effects (1) to (4) mentioned above, it is possible to form an arbitrarily wide field area without a step, which can lead to product integration and high performance. Semiconductor devices such as bipolar transistors and MOS transistors that have improved performance and high reliability can be obtained.

Next, the second invention of the present application will be explained in detail.

First, similarly to the first invention described above, the semiconductor layer is selectively etched to a desired depth using a mask pattern to widen the width (
Alternatively, a narrow first groove portion is formed as necessary. However, the mask pattern used here is +! jJ In addition to flintable materials, resist, SiO2, etc. can be used.

Next, after removing the mask pattern, at least a first separation material film is formed in the first groove with a thickness smaller than the depth of the groove. The first separation material membrane used here is:
Examples include a 5in2 film deposited by CVD or PVD, a Si3N4 film, or a mixture thereof, a thermal oxide film formed by thermal oxidation or nitridation, or a Si, N4 film.

Next, a conductive material film is deposited over the entire surface of the semiconductor layer including the first trench. The conductive material film is deposited to a thickness such that it fills the first trench in which the first separation material film is formed, and the surface of the conductive material film is approximately the same as the surface of the semiconductor layer in the trench.

Examples of the conductive material used here include polycrystalline silicon doped with impurities such as phosphorus, arsenic, and boron, amorphous silicon doped with the same impurities, metal silicides such as tungsten silicide and molybdenum silicide, or AΩ, Examples include metals such as Mo, Ti, and Ta. Note that, depending on the case, a polycrystalline silicon film or an amorphous silicon film may be deposited and doped with impurities after patterning in a process described later to form a conductive material film pattern.

Next, a striped mask pattern is formed on the main surface of the conductive material film at least within the wide groove. As the mask pattern material used here, for example, resist, 5i
n2. St, N, etc. can be mentioned. Continuing,
Using this mask pattern, the conductive material film is etched in stripes by a directional etching method such as reactive ion etching, thereby forming a conductive material film pattern that functions as a wiring pattern. At this time, if the thickness of the conductive material film formed in the narrow groove provided in another part of the semiconductor layer is sufficiently thicker than half the width of the groove, the narrow groove The conductive material also remains.

Next, a second separating material such as a sewn material is left in the second groove between the conductive material film patterns. As a means for forming this separation material, for example, after depositing an insulating material so as to sufficiently fill the second groove, the insulating material other than the groove is removed by etching the entire surface to form the insulating material (second portion M 44 ). Alternatively, if the conductive film pattern is made of impurity-doped polycrystalline silicon, impurity-doped amorphous silicon, or metal silicide, an oxide film can be grown directly on the ff11 surface of the conductive material film pattern by thermal oxidation treatment. Oxide (
A method such as filling the groove with a second separating material) may be adopted.

By leaving the second separation material in the second groove between the conductive material film patterns using the above-described means, the thin first separation +4 film and the second separation i! It has a striped conductive material film pattern (distribution A) surrounded by the F material, and a wide field region whose surface is approximately on the same level as the surface of the conductor layer is formed. A semiconductor device is manufactured by forming a bipolar type element, a MOS type element, etc. in the semiconductor layer separated by such a wide field region or a narrow field region formed as necessary.

According to the second invention of the present application, it is possible to form a wide field area that does not have a step and incorporates wiring, which in turn makes it possible to form high-density wiring with high performance and reliability. A semiconductor device with increased integration can be obtained.

Next, the third invention of the present application will be explained in detail.

First, as in the first invention described above, a semiconductor layer is selectively etched to a desired depth using a mask pattern to form wide and narrow first trenches.

Next, a thermal oxidation treatment is performed using an oxidation-resistant mask pattern to form a separation material film in the first trench, or after the mask pattern is removed, a film is formed so that at least the opening of the first trench is filled. A separation material film made of an insulating material is deposited on the surface.

Next, a striped mask pattern is formed on the main surface of the separation material film at least within the wide groove. As the mask pattern material used here, for example, resist, 5i
Examples include 02,5XiNa and the like. Continuing,
Using this mask pattern, the first portion #+4 film is etched in stripes by a directional etching method such as a reactive ion etching method or a wet etching method to form a second groove portion. In this etching, the separation material film may be selectively etched entirely in the depth direction, or it may be selectively etched so that only a thin second separation material remains on the bottom surface.

Note that when the former etching is performed, prior to leaving the conductive material in the second groove in the step described later, a thermal oxidation treatment or the like is performed to form an oxide film or the like on the semiconductor layer portion exposed from the second groove. do.

Next, the conductive material is left in the second groove.

A method for making this conductive material remain is to deposit a conductive material film on the entire surface to a thickness sufficiently thicker than half the width of the opening of the second groove, and then to etch the conductive material film over the entire surface to remove the remaining conductive material. The surface of the semiconductor layer is made substantially flat with respect to the semiconductor layer. The conductive materials used here are the same as those listed in the second invention.

By leaving the conductive material in the second groove provided in the separation material film by the above-described means, the conductive material (wiring) in the form of a strip is surrounded by the separation material film, and the surface is the surface of the semiconductor layer. A bipolar type element or M
A semiconductor device is manufactured by forming an OS type element or the like.

Therefore, according to the third invention of the present application, similarly to the second invention, it is possible to obtain a semiconductor device that achieves high performance, high reliability, and enables high-density wiring formation to achieve high integration. .

(Example) Hereinafter, an example in which the present invention is applied to manufacturing a bipolar LSI will be described with reference to the drawings.

Example 1 First, a buried layer 202 with a high concentration of n-type impurities was selectively formed on a p-type semiconductor substrate 201, and an n-type epitaxial semiconductor layer 203 with a thickness of about 2 μl was grown on this layer.
A thin thermal oxide film and a thin silicon nitride film are sequentially formed on the surface of the semiconductor layer 203, and the silicon nitride film and the thermal oxide film corresponding to the portion where the wide trench is to be formed are removed by photoetching to form a silicon nitride film pattern 204a, 2
04b and thermal oxide film patterns 205a and 205b were formed (as shown in FIG. 6(a)).

Next, silicon nitride film patterns 204a and 204b are formed.
Using a mask, the semiconductor layer 203 was etched to a desired depth to form a wide first groove 20G (as shown in FIG. 6(b)). Next, silicon nitride film patterns 204a, 2
A thermal oxidation treatment was performed using 04b as an oxidation-resistant mask. At this time, as shown in FIG. 6(e), oxidized H207 was selectively formed in the groove 206 as a first separation material film.

Next, silicon nitride film patterns 204a and 204b are formed.
After sequentially removing the thermal oxide film patterns 205a and 205b, a thin silicon nitride film is deposited again on the entire surface, and a photo-Afi! A resist pattern 208a is formed by il engraving.
208d, and further these resist patterns 20
Using 8a to 208d as masks, the silicon nitride film is buttered to form silicon nitride film patterns 209a to 209d.
was formed (as shown in FIG. 6(d)). Next, using the resist patterns 208a to 208d as a mask, the exposed portions of the semiconductor layer 203 and the portions extending between the end of the oxide film 207 and the semiconductor layer 203 in contact with this are etched by reactive ion etching. A narrow second groove 210a and narrow second grooves 210b and 210c were formed near the end of the oxide film 207, respectively. At this time, the oxide film 207' remained within the first trench. Thereafter, p-type impurities such as boron are ion-implanted using the resist patterns 208a to 208d as masks, and after removing the resist patterns 208a and 208d, heat treatment is performed to form the p-type semiconductor substrate 203 into the semiconductor layer 203 portion under each of the grooves 210a to 210b. The p' regions 211a to 211 reach up to
1c was formed (as shown in FIG. 6(e)) ## Next, a CV D-S i O2 film 21.2 was deposited on the entire surface to a thickness sufficiently thicker than half of the opening width of the second grooves 210a to 210c. did. At this time, the surface of the CVD-5iO□II!I 212 is almost flat as shown in FIG. Etching was carried out until the patterns 209a to 209d were exposed.At this time, as shown in FIG. 6(g), CVD-5iO□ 212' remained in the second trench 210 and east, forming a narrow field region 213. At the same time,
CVD-5iO
' remains, and a wide field nrI region 214 is formed, which is composed of five oxide films 207'. Subsequently, after removing the silicon nitride +4 patterns 209a to 209d (as shown in FIG. 6(g)), n-prop was applied to the island-shaped semiconductor layer separated by the narrow and wide field regions 213 and 214 according to a conventional method. A bipolar LSI was manufactured by forming a transistor (not shown).

According to the first embodiment, the narrow field area 2
In addition to H, a wide field region 214 can be formed, and the level difference between the surface of the n-type semiconductor layer 203 serving as an npn transistor formation portion and the surface of the wide field region 214 can be reduced (as shown in FIG. 6(g)). As a result, when an electrode such as a base is extended from the npn transistor region onto the wide field region 214, the electrode is broken between the field region 214 and the npn transistor region. 11. can. Also,
Field area 213. p-type region 2+1 below 214
By forming transistors a to 211e, it is possible to prevent leakage current from occurring between npn transistors. therefore,
A bipolar LSI with high performance and high integration can be obtained.

Example 2 First, a buried layer 302 with a high concentration of n-type impurities is selectively formed in a p-type semiconductor substrate 301, and an n-type epitaxial semiconductor layer 303 with a thickness of about 2 μl is grown on this layer. A thin silicon nitride film was deposited on the surface, and the silicon nitride film corresponding to the narrow and wide trench formation portions was removed by photoetching to form silicon nitride film patterns 304a to 304c (FIG. 7). (a
).

Next, using the silicon nitride film patterns 304a to 304c as a mask, the semiconductor layer 303 is etched to a desired depth by reactive ion etching to form a narrow T41 groove 305a and a wide first groove 305b, and then the same pattern is etched. Using 304a to 304c as a mask, boron ions are implanted and activated to form grooves 305a and 305b.
P+ type regions 30ia and 306b were formed below. The groove 30 continues to be formed on the entire surface including the grooves 305a and 405b.
The first CVD-5i is sufficiently thinner than the depth of 5a and 305b.
An O□ film 307 was deposited (as shown in FIG. 7(b)).

Next, after depositing a phosphorus-doped polycrystalline silicon film 308 on the entire surface to a thickness comparable to the depth of the wide trench 305b, the polycrystalline silicon film 3 in the wide trench 305b is deposited.
Striped resist patterns 309a and 309b were formed on the 08 main song by photolithography (Fig. 7(C)).
(Illustrated). Subsequently, the polycrystalline silicon film 308 was subjected to anisotropic etching such as reactive ion etching. At this time, the thin first CVD-S i O2 film 30
7 is covered with polycrystalline silicon 3.
1G remained. At the same time, polycrystalline silicon patterns 311a and 311b are formed on the side surfaces of the wide groove 305b, and polycrystalline silicon patterns 311c are formed within the groove 305b below the resist patterns 309a and 309b.

31! d were formed (as shown in FIG. 7(d)). In this case, if a wet etching method is used, only polycrystalline silicon patterns 311a and 311b corresponding to resist patterns 309a and 3091+ are formed.

Next, a second CV D-5i 02 312 was deposited to a thickness sufficiently thicker than the width of the opening of the second groove between the polycrystalline silicon patterns 311a to 311d.
(Figure 7(c) diagram) Next, CVD-5i 02
'a 312 is etched with ammonium fluoride until the surfaces of the silicon nitride film patterns 304a to 304c are exposed, and CVD-5iOz 312 is etched between the polycrystalline silicon patterns 311a to 311d in the wide groove 305b.
'a~312'c was left (as shown in FIG. 7(f')).

Continuing, silicon nitride film patterns 304a to 304
c was removed and thermal oxidation treatment was performed. As a result, the surface of the remaining polycrystalline silicon 310 within the narrow groove portion 305a is oxidized and
! 313 is grown, surrounded by the first CVD~Sin,
Polycrystalline silicon 3 covered with a film 307 and an oxide film 313
A narrow field region 314 having a width of 10 (wiring) to 9 was formed. At the same time, polycrystalline silicon patterns 311a to 3
An oxide film 313 is also grown on the surface of 11d, and the area II is the first CVD-3i 02 film 307, CVD-5i 02
A wide field region 315 is formed that covers polycrystalline silicon patterns 311a to 311d (wirings) covered with 312a' to 312c' and an oxide film 3H (
(Illustrated in FIG. 7(g)). Note that 313' is the semiconductor layer 303
This is an oxide film grown on the surface.

Thereafter, an island-shaped semiconductor layer separated by narrow and wide field regions 314315 is formed using a conventional method (not shown).
A bipolar LSI was manufactured by forming a pnh transistor.

According to the second embodiment, the wide field area 3
Since the phosphorus-doped polycrystalline silicon patterns 311a to 311d that function as wiring can be embedded in the wiring 15, it is possible to achieve high performance, high reliability, and high-density wiring formation.
A bipolar LSI that achieves high integration can be obtained.

Example 3 A silicon nitride film is deposited on the same semiconductor layer 303 as in Example 2, and a resist pattern 316 is formed by photolithography outside the parts on which narrow and wide grooves are to be formed on the silicon nitride film.
After forming patterns a to 318c, the same patterns 3168 to 31
The silicon nitride film was etched using Bc as a mask to form silicon nitride film patterns 304a to 304c (
(Illustrated in FIG. 8(a)). Next, resist pattern 31
Using 6a to 316c as masks, the semiconductor layer 303 is etched to a desired depth by reactive ion etching to form a narrow first groove 305a and a wide first groove 305.
After forming the same resist patterns 316a to 316
Boron ions were implanted using b as a mask, and activated to form a p''m OH region 3 (lGa, 30 (ib) below the trenches 305a and 305b that reached the p-type semiconductor substrate 301 (FIG. 8(b)). ).

Next, the resist patterns 318a to 318c are removed, and a CVD-5iO2 film 317 is formed on the entire surface in the wide groove 305.
After depositing the CVD-S i O2 film 317 in the wide groove 305b to a thickness similar to the depth of b.
Striped resist patterns 318a and 3111b were formed on the main surface by photolithography (as shown in FIG. 8(c)).

Next, using CVD-5in, the film 317 was subjected to anisotropic etching such as reactive ion etching. At this time, CVD-5i02319 is inserted into the narrow groove 305a.
remained. At the same time, CVD-5to2 film patterns 319a and 319b are formed around the side surfaces of the wide groove 305b, and CVD Sr 02 film patterns 319c are also formed within the groove 305b below the resist patterns 318a and 318b.

319d were formed respectively (as shown in FIG. 8(d)).

Next, thermal oxidation treatment was performed. At this time, CVD-5 inch is applied to the groove portion 305b, and the film patterns 319a to 319d are
A thin thermal oxide film 320 is formed on the exposed surface of the semiconductor layer 303 between
was grown. Note that since the surface of the semiconductor layer 303 is covered with the silicon nitride film patterns 304a to 304C that define definition, oxidation of the surface of the semiconductor layer 303 can be prevented. Next, phosphorus-doped polycrystalline silicon IIQ 32
1 to CVD S i 02 film pattern 319a-3
The film was deposited to a thickness sufficiently thicker than half of the opening of the second groove between 19d (as shown in FIG. 8(c)). Subsequently, the polycrystalline silicon film 321 is formed into a silicon nitride film pattern 304.
The CVD-5i02 film pattern 319 in the wide groove 305b is etched until the surface of a to 304C is exposed.
Patterned polycrystalline silicon 322a between 3 and 319d
-322c remained (as shown in FIG. 8 (1')).

Incidentally, since the silicon nitride film patterns 304a to 304C act as a mask when etching the polycrystalline silicon film 321, etching of the surface of the semiconductor layer 303 can be prevented.

Next, silicon nitride film patterns 304a to 304. c.
After gold was removed, thermal oxidation treatment was performed. As a result, the oxide film 31 is formed on the surface of the remaining polycrystalline silicon 322a to 3220.
3 was grown, the surrounding area was CVD-3in, and the film pattern 31
9a to 319d and remaining phosphorus-doped polycrystalline silicon 322a to 32 covered with thermal oxide film 320 and oxide film 313
A wide field region 315' having 2C (wiring) was formed. In addition, the above-mentioned C V D S i 0
The narrow groove portion 305a where 2319 remains functions as a narrow field region 314' (as shown in FIG. 8(g)).

Then, narrow and wide field areas 314'315'
A bipolar LSI was manufactured by forming an npn transistor (not shown) on the island-shaped semiconductor layer separated by the semiconductor layer.

According to the third embodiment, the wide field area 3
15' can be embedded with patterned phosphorus-doped polycrystalline silicon 322a to 322C that functions as wiring, making it possible to achieve high performance and reliability as well as high-density wiring formation and high integration. L.S.
You can get I.

In addition, it concerns on this invention. '1 In the production of conductor devices, the semiconductor layer is: ■ a p-type epitaxial layer provided on a p-type semiconductor substrate, ■ a layer formed by forming two n-type epitaxial layers on a p-type semiconductor substrate, or a p-type layer formed on the same substrate. A stack of an epitaxial layer and an n-type epitaxial layer may be used.

In manufacturing the semiconductor device according to the present invention, in addition to forming an np type semiconductor layer on a p-type semiconductor substrate as in the above embodiment, for example, a pn type semiconductor substrate is formed using a triple diffusion method. A bipolar transistor may also be formed.

The method for manufacturing a semiconductor device according to the present invention is as described in the above embodiment (
In addition to manufacturing npn bipolar transistors,
The present invention can be similarly applied to manufacturing other bipolar semiconductor devices such as 2L and MO5 semiconductor devices.

[Effects of the Invention] As described in detail above, according to the present invention, an arbitrary field region of "t", whether fine or wide, can be applied to a self-containing 7 mainly with respect to a groove provided in a semiconductor layer, without taking mask alignment metal tolerance. It is possible to provide a method for manufacturing a semiconductor device such as a bipolar transistor that can be formed in lines and has a structure in which wiring made of a conductive material with excellent tlJ properties is embedded in a wide field region.

[Brief explanation of the drawing]

Figures 1 (a) to (e) are cross-sectional views showing the manufacturing process of a vertical type transistor using the conventional selective oxidation method;
The figure is a cross-sectional view to explain the problems of the conventional selective oxidation method, and FIGS. 3(a) and 3(b) are cross-sectional views to explain the problems when the conventional selective oxidation method is applied to a bipolar transistor. 4(a) to 4(e) are process cross-sectional views showing the manufacturing of the npn bipolar transistor already proposed by the present applicant, and FIG. Cross-sectional view showing a state where regions are formed, No. 6
Figures (a) to (g) are cross-sectional views showing the manufacturing process of a bipolar LSI in Example 1 of the present invention, and Figures 7 (a) to (g).
) is a cross-sectional view showing the manufacturing process of a bipolar LSI according to a second embodiment of the present invention, and FIGS. 8(a) to (g) are cross-sectional views showing the manufacturing process of a bipolar LSI according to a third example of the present invention. 201.30t-p type conductor substrate, 202.302-n
゛-type buried layer, 203.303...n-type epitaxial semiconductor layer, 204a, 204b... silicon nitride film pattern, 20G, 205a, 205b-...first
groove part, 207-... oxide film, 210a ~ 210cm
...Second groove, 2 l 1. a, 2nd, 30
6a, 3061+...p type region 212'...residual CVD-9tO2 film, 2H, 314, 314'...
・Narrow field area, 214, 315, 315'
... wide field area, 307 ... 1st c.
7) CVD 5iOz film, 311a to 311d-・
・Polycrystalline silicon pattern, 312a' to 312d'
...Residual CVD-5io,, 319-...Remaining CVD
-3fO2, 319a to 319d-CV D-5i O
2-film pattern, 322a to 322c...patterned residual polycrystalline silicon.

Claims (3)

[Claims] (1) A step of forming a first trench in a portion of the semiconductor layer where a wide field region is to be formed, a step of selectively forming a first isolation material film in this trench so that the trench is filled; The first separation material film is patterned in a stripe shape so that the separation material film remains on the bottom surface of the groove, or after the separation material film is patterned in a stripe shape, the exposed bottom surface of the trench between the separation material film patterns is patterned. A method for manufacturing a semiconductor device, comprising the steps of: forming another thin isolation material film on a semiconductor layer portion; and leaving a conductive material in a second groove between the isolation material film patterns. (2) When forming the first groove, simultaneously form a narrow groove in another part of the semiconductor layer, and further form a first separation material film in the first groove, and simultaneously form the narrow groove in another part of the semiconductor layer. 1st in the groove
2. The method of manufacturing a semiconductor device according to claim 1, wherein the separating material remains. (3) The method of manufacturing a semiconductor device according to claim 1, wherein the conductive material is impurity-doped polycrystalline silicon, impurity-doped amorphous silicon, or metal silicide.