JPH0574220B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device by improving isolation technology between elements of bipolar or MOS type ICs, LSIs, etc. Regarding the method.

(Prior Art) Conventionally, as methods for separating elements in the manufacturing process of semiconductor devices, especially bipolar ICs, pn junction isolation,
Selective oxidation is commonly used. This method will be explained below using a bipolar vertical npn transistor as an example.

First, as shown in FIG. 1a, a p-type silicon substrate 1
A highly concentrated n-type buried region 2 is selectively formed, and then an n-type semiconductor layer 3 is epitaxially grown to form a silicon oxide film 4 of about 1000 Å for selective oxidation. An oxidation-resistant silicon nitride film with a thickness of approximately 1000 Å is deposited on the substrate. Continuing,
Silicon oxide film 4 and silicon nitride film 5 are patterned by photolithography to form silicon oxide film patterns 4a, 4b and silicon nitride film patterns 5a, 5.
form b. Subsequently, the silicon oxide film patterns 4a, 4b and the silicon nitride film pattern 5
Using a and 5b as masks, the n-type semiconductor layer 3 is
Silicon was etched to about 5000 Å, and p-type regions 6a and 6b were formed by boron ion implantation using the same patterns 4a, 4b, 5a, and 5b as masks (as shown in FIG. 1c). Next, thermal oxidation was performed in a steam or wet atmosphere to selectively grow silicon oxide films 7a to 7c with a thickness of about 1 .mu. (as shown in FIG. 1d). Next, silicon oxide film patterns 5a and 5b are formed.
For example, the base region 8 is formed by removing with hot phosphoric acid and performing boron ion implantation in the region directly under the silicon nitride film pattern 5a.
Furthermore, an n-type region 9 to serve as an emitter, an n-type region 10 for leading out the collector electrode, etc. are formed by arsenic ion implantation, and a contact window is formed in the silicon oxide film pattern 4a formed in advance. After opening, emitter electrode 1
1. A vertical npn transistor was manufactured by forming a base electrode 12 and a collector electrode 13. (Illustrated in Figure 1e). In this case, element isolation of the npn transistor is performed using field oxide films 7a and 7 with a thickness of about 1μ.
However, if the thickness of the n-type semiconductor layer 6 is about 1 to 2 μm, field oxidation by selective oxidation can be directly performed using p-type regions 6a, 6b, etc. The device can be brought into contact with the mold substrate 1 to separate the elements. In addition, even when devices are directly isolated using a field oxide film, ion implantation of p-type impurities for channel stop is performed between the p-type substrate 1 and the field oxide film to prevent leakage current between devices. It is preferable to carry out a pre-treatment.

However, the method of manufacturing bipolar ICs using the conventional selective oxidation method described above has various drawbacks as shown below.

FIG. 2 shows in detail the cross-sectional structure when field oxide films 7a and 7b are formed using Si ₃ N ₄ patterns 5a and 5b as masks. However, in FIG. 2, the thin-contact etching of the semiconductor layer 3 is
I haven't done it. It is generally known that in the selective oxidation method, the field oxide film 7b grows by digging into the region under the Si ₃ N ₄ pattern 5a (see
area F in the figure). This is because the oxidizing agent diffuses through the thin SiO ₂ film 4a under the Si ₃ N ₄ pattern 5a during field oxidation, resulting in the so-called bird's beak and the field oxide film 7.
The thick part b consists of a part E that wraps around in the lateral direction as well. For example, the length of F is Si ₃ N ₄ pattern 5a
The thickness of the SiO ₂ film 4a below it is 1000 Å.
When the filter field oxide film 7b with a thickness of 1 μm is grown under the conditions described above, the thickness reaches approximately 1 μm. Therefore, if the distance A between the Si ₃ N ₄ patterns 5a and 5b is 2 μm, the width c of the field region is 1 μm, so F is 1 μm.
It cannot be made smaller than 4 μm and becomes a major hindrance to LSI integration. For this reason, recently,
Make the Si ₃ N ₄ patterns 5a and 5b thicker and
Bird beak created by thinning the SiO ₂ film (part D in the figure)
Attempts have been made to suppress the intrusion F of the field oxide film by reducing the growth thickness of the field oxide film 7b. However, in the former case, the stress at the end of the field increases and defects are more likely to occur, and in the latter case, there are problems such as a drop in field inversion voltage and an increase in wiring capacitance in the field part, which limits the ability to achieve high integration using selective oxidation. There is.

When the above-mentioned bird's beak or the like occurs, the following problems occur. This will be explained using the manufacturing process of a bipolar transistor by the conventional selective oxidation method shown in FIGS. 3a and 3b.

As shown in FIG. 3a, the surface of the semiconductor layer 21, which will become the n-type collector region, is coated using the conventional selective oxidation method.
Silicon oxide films 22a and 22b were formed, and using the oxide films as masks, a p-type base region 23 was formed by boron ion implantation. Next, as shown in FIG. 3b, an n-type emitter region was formed by a diffusion method or an ion implantation method. Here, the silicon oxide film 24 is an insulating film for taking out the electrode.
The problems with the manufacturing method using the conventional selective oxidation method are mainly that the formed silicon oxide film 22a,
This is due to the so-called bird's beak shape such as 22b, stress in the semiconductor region near the bird's beak, and the resulting defects. First, regarding the shape of the base region 23, let C be the depth from the semiconductor main surface of the base junction formed by boron ion implantation, and D be the depth of the base junction under the bird's beak. , the value of D decreases by the thickness of the bird's beak oxide film. Furthermore, since the surface of the silicon oxide film is etched during the etching process during the manufacturing process, the value of D becomes even smaller. Therefore, if an Al electrode for taking out the base is formed at the tip of the bird's beak, the reaction between Al and silicon causes the Al to penetrate the base region, causing device failure. Also, if the base width of the transistor below the main surface of the semiconductor substrate is A, and the base width directly under the bird's beak is B, then as mentioned above, the depth of the base at the bird's beak is shallow and the etching during manufacturing. The process causes the tip of the bird's beak to recede and
The depth of the emitter from the tip of the beak becomes deeper than other parts, and the stress and defects caused by the selective oxidation method cause abnormal diffusion of the emitter, and the depth of the emitter junction becomes deeper. ,
Compared to the normal base width A, the base width B directly below the bird's beak becomes smaller, which is undesirable because it causes a failure in the collector-emitter breakdown voltage of the npn transistor. In this way, the selective oxidation method can be applied to bipolar ICs.
When applied to a device, it is likely to cause various device defects.

For these reasons, the present applicant proposed a method of manufacturing a bipolar semiconductor device (for example, a vertical npn transistor) using a novel field region forming means described below.

First, as shown in FIG. 4a, a p-type semiconductor substrate 1
High concentration buried layer 1 of n-type impurity selectively on 01
After forming an n-type epitaxial semiconductor layer 103 with a thickness of about 2.5 μm thereon, resist patterns 104a, 104b, and 104c were left on the surface of the semiconductor layer 103 by photolithography.
Next, this patterned resist 10
Using 4a, 104b, and 104c as masks, the semiconductor layer 103 is silicon-etched by anisotropic reactive ion etching until it reaches the p-type substrate 101, so that the width is approximately
Grooves 105a, 105b having a depth of 1μ and about 3μ are formed to separate the n-type semiconductor layer 103 into islands (as shown in FIG. 4B). At this time, it is preferable to form p-type regions 106a and 106b by boron ion implantation for channel cutting between elements.

Next, as shown in FIG. 4c, a resist 104 is formed.
After removing a, 104b, 104c, CVD-
The SiO ₂ film 107 is connected to the device isolation trenches 105a and 1.
The film is deposited sufficiently thicker than half the width of 05b (approximately 5000 Å). At this time, CVD-SiO ₂ is gradually deposited on the inner surface of the groove, the grooves 105a and 105b are sufficiently filled, and the surface of the CVD-SiO ₂ film 107 is
It is almost flat. Note that during this deposition, there is no need for high-temperature, long-term thermal oxidation treatment as in the selective oxidation method, so the p-type regions 106a, 1
Rediffusion of 06b hardly occurs. Continuing,
CVD-SiO ₂ film 107 with ammonium fluoride in groove 10
The entire surface of the silicon semiconductor layer 103 was etched until portions of the silicon semiconductor layer 103 other than 5a and 105b were exposed. At this time, as shown in FIG. 4d, the top of the semiconductor layer 103 is
The thickness of the CVD-SiO ₂ film 107 is removed,
CVD-SiO ₂ remains only in the trenches 105a and 105b, thereby forming field regions 107a and 107b buried in the semiconductor layer 103.

Next, a p-type base region 108 is formed in the semiconductor region separated by the field regions 107a and 107b by boron ion implantation using a resist block method, and an insulating film 109 with a thickness of about 3000 Å is formed on the entire surface of the semiconductor layer. Then, by photolithography, diffusion windows for the emitter and collector are opened in this insulating film 109, and arsenic ion implantation is performed to form an n-type region 110 that will become the emitter and a collector extraction part. n-type region 111
form. Next, an opening for the p-type base region 108 is formed, an electrode material such as Al is deposited on the semiconductor surface, and this electrode material is patterned by photolithography to form the base electrode 112, emitter electrode 113, and collector electrode. Forming the electrode 114
An npn bipolar transistor is manufactured (as shown in FIG. 4e).

According to the method described above, a bipolar semiconductor device having various effects shown below can be obtained.

(1) Since the area of the field region is determined by the area of the groove formed in advance in the semiconductor layer, by reducing the area of the groove, it is possible to easily form the initially intended fine field region. type semiconductor device can be obtained.

(2) The depth of the field region is determined by the depth of the groove provided in the semiconductor layer, regardless of the area, so the depth can be selected arbitrarily, and
Current leakage between elements can be reliably prevented in the field region, and a high-performance bipolar semiconductor device can be obtained.

(3) After forming the groove and selectively doping the channel stopper impurity into the groove, the impurity region is Since it does not re-diffuse in the lateral direction and reach the buried layer of the element forming region or the active region of the transistor, it is possible to prevent the effective reduction of the element forming area.
In this case, if the impurity is doped by ion implantation, the impurity ion implantation layer can be formed at the bottom of the trench, and even if the ion implantation layer is re-diffused, it will still remain in the surface layer of the element formation region (the active part of the transistor). Since it does not extend to a depth, it is possible to prevent the effective element formation region from being reduced, and also to prevent the impurity region from interfering with the active region of the transistor.

(4) When a field region is formed by leaving an insulating material in all of the grooves, the substrate is flattened, so that it is possible to prevent breakage from occurring during the subsequent formation of electrode wiring.

As described above, the above method has many advantages. However, although it is possible to form an LSI using narrow field regions, there are some difficulties in forming a wide field region. In other words, the width S of the field depends on the width S of the groove, and in order to leave the insulating film in the groove, it is necessary to make the insulating film thickness (T) > 1/2S, and the width of the field is When the size is large, the insulating film must also be deposited fairly thickly. For example, to form a field with a width of 20 μm, the insulating film must be thicker than 10 μm, and there are many difficult problems such as deposition time, film thickness accuracy, and crack-free conditions. Additionally, a 200μm wide field (for example, the bottom of the Al bonding pad)
etc., it is extremely difficult to form using the above method. Therefore, if a wide field is required, first create narrow fields 107a, 107b, 107 according to the method described above, as shown in FIG.
After embedding C, for example, an insulating film (SiO ₂ ) is deposited, and a wide field region 107' is formed by partially leaving this insulating film by photolithography.

Although this method allows the formation of a wide field oxide film and overcomes most of the deficiencies of the selective oxidation method, one major drawback occurs. That is, a step occurs at the end of the wide field film 107' shown in FIG. 5, and flatness is lost. In the case of the selective oxidation method, half of the field film is buried in the silicon semiconductor layer, but in this method, the field film thickness becomes a step, so the step is larger than that in the selective oxidation method, making it difficult to perform microlithography near the wide field film. This has become a major hindrance for those who need it.

(Problems to be Solved by the Invention) As a result of further intensive research based on the above-mentioned method, the present invention has developed a field region that is self-aligned to the groove of the semiconductor layer, whose surface is at the same level as the main surface of the semiconductor layer, and which has a wide width. We have established a method for forming a semiconductor device, thereby providing a method for manufacturing a semiconductor device that achieves high integration and high performance, as well as a method for manufacturing a semiconductor device with a structure in which wiring made of conductive material with excellent flatness is embedded in the field region. This is what I am trying to do.

[Structure of the invention] (Means and actions for solving problems) Hereinafter, the first invention of the present application will be explained in detail.

First, a mask material film is deposited on a semiconductor layer such as silicon, and then wide and narrow field region portions of the mask material film are removed by photolithography to form a mask pattern. Examples of the mask material film used here include a silicon nitride film or a two-layer film of a silicon oxide film and a silicon nitride film. Next, using this mask pattern, the semiconductor layer is selectively etched to a desired depth to form wide and narrow first trenches.
In this case, if reactive ion etching or a directional etching method such as an ion ring method is used as the etching means, it is possible to provide a groove portion with vertical or nearly vertical side surfaces. However, a groove portion whose side surfaces are tapered may be formed, and by forming such a groove portion, it becomes possible to fill the first separating material film described later with a good shape.

Next, thermal oxidation treatment is performed using a mask pattern made of a silicon nitride film as an oxidation-resistant mask, and a first isolation material film made of oxide is selectively formed in the exposed first groove portion. In this case, if the mask pattern is formed of two layers, a thin silicon oxide film and a silicon nitride film, the stress applied to the semiconductor layer portion at the end of the mask pattern during thermal oxidation can be alleviated. In addition, in this method, by appropriately selecting the depth of the groove and the thickness of the thermal oxide film (first separation material film), the surface of the semiconductor layer and the surface of the first separation material film are made to be approximately the same. It can be leveled and the flatness can be improved.

Next, after removing the mask pattern, a narrow second groove is formed. The second groove portion is formed near the contact between the first isolation material film and the semiconductor layer, and at a location in the semiconductor layer different from the isolation material film. In particular, in the method of the present invention, by removing the former portion using a reactive ion etching method, a directional etching method such as an ion ring, a second groove portion having vertical or nearly vertical side surfaces can be formed. In a subsequent step, by filling this groove with a second separation material, a wide field region with little pattern conversion difference can be formed.

Next, the second separating material is filled and embedded in the narrow second groove portion by the means described below.

(b) An insulating material film is placed on the semiconductor layer including the second groove.
After the film is deposited to a thickness sufficiently thicker than half the width of the groove by CVD, PVD, etc., it is etched until the surface of the semiconductor layer is exposed, and an insulating material (second isolation material film) is deposited in the second groove. ) remain.

Examples of the above-mentioned insulating material include SiO ₂ ,
Examples include Si ₃ N ₄ or Al ₂ O ₃ , and in some cases, phosphorus silicide glass (PSG), arsenic,
Silica glass (AsSG), boron silica glass (BSG)
A low melting insulating material such as may also be used. Note that, prior to forming the insulating material, a channel stopper region or a pn junction isolation region may be formed in the semiconductor layer or the semiconductor substrate by selectively doping an impurity of the same conductivity type as the semiconductor substrate in the trench. Furthermore, prior to depositing the insulating material, the entire semiconductor layer having a groove, or at least a portion of the groove, may be oxidized or nitrided to grow an oxide film or a nitride film to an extent that the groove is not blocked. By using these methods in combination, the obtained field insulating film is composed of a highly dense oxide film or nitride film in contact with the semiconductor layer in the groove and an insulating material formed by deposition, and is an insulating film. Element isolation performance can be significantly improved compared to those made of only materials. Furthermore, after depositing the insulating material, the entire or part of the surface layer of the insulating film is doped with a low-melting substance such as boron, phosphorus, arsenic, etc., and the doped layer of the insulating film is melted by heat treatment, or A low-melting insulating material such as boron silicide glass (BSG), phosphorus silicide glass (PSG), or arsenic silicide glass (AsSG) is deposited on all or part of the insulating film, and this low-melting insulating film is It may be melted or subjected to any other treatment. By adopting such a method, if the portion corresponding to the first groove becomes concave due to the deposition conditions of the insulating material, the concave portion can be filled and flattened, and as a result, subsequent etching can be performed easily. This has the effect of preventing the inconvenience of the insulating material remaining in the first groove becoming below the level of the opening.

(b) A material that will be converted into an oxide by oxidation treatment is deposited on the semiconductor layer including the narrow second groove by CVD.
Deposited by PVD method, etc., etched until the surface of the semiconductor layer is exposed, leaving the same material in the groove, and then subjected to thermal oxidation treatment to convert the remaining material into oxide (second isolation material) do. Examples of materials used here include polycrystalline silicon,
Amorphous silicon can be mentioned. In addition,
Prior to the deposition of the material, at least the inside of the second groove is subjected to oxidation or nitriding treatment to grow a thin oxide film or nitride film to the extent that the groove does not evaporate, so that the material remains within the groove. Thereafter, the second separation material can be formed by oxidizing the exposed surface without oxidizing all of the remaining material.

By combining the oxide film (first separation material) remaining in the wide first groove portion with the remaining second separation material by means such as (a) and (b) described above, a wide groove can be formed. A field region of A semiconductor device is manufactured by forming bipolar type elements, MOS type elements, etc. in semiconductor layers separated by such wide and narrow field regions.

Accordingly, the main application of the first invention of the present application provides a wide groove portion having vertical or tapered side surfaces in a semiconductor layer, and forms a first isolation layer within the groove portion by thermal oxidation or the like to a thickness that is approximately the same as the depth of the groove portion. A wide field region is formed by forming a second trench material, providing a second trench section between the separation material and the semiconductor layer near the side surface of the trench, and filling this trench section with the second separation material. be. Therefore, according to the first invention of the present application, in addition to having the above-mentioned excellent effects (1) to (4), it is possible to form an arbitrarily wide field region without a step, and as a result, it is possible to achieve high integration. , it is possible to obtain semiconductor devices such as bipolar transistors and MOS transistors that achieve high performance and high reliability.

Next, the second invention of the present application will be explained in detail.

First, as in the first invention described above, a semiconductor layer is selectively etched to a desired depth using a mask pattern to form a wide (or narrow if necessary) first layer.
Form a groove. However, for the mask pattern used here, in addition to oxidation-resistant materials, resist, _SiO2, etc. can be used.

Next, after removing the mask pattern, at least a first separation material film is formed in the first groove with a thickness smaller than the depth of the groove. As the first separation material film used here, for example, a SiO ₂ film, a Si ₃ N ₄ film, or a composite film of these deposited by CVD method or PVD method, or a thermal oxide film formed by thermal oxidation or nitriding treatment. , Si ₃ N ₄ film.

Next, a conductive material film is deposited over the entire surface of the semiconductor layer including the first trench. The conductive material film is deposited to a thickness such that it fills the first trench in which the first separation material film is formed, and the surface of the conductive material film is approximately the same as the surface of the semiconductor layer in the trench. Examples of the conductive material used here include polycrystalline silicon doped with impurities such as phosphorus, arsenic, and boron, amorphous silicon doped with the same impurities, amorphous silicon doped with the same impurities, or tungsten silicide. ,
Examples include metal silicides such as molybdenum silicide, metals such as Al, Mo, Ti, and Ta. Note that, depending on the case, a polycrystalline silicon film or an amorphous silicon film may be deposited and doped with impurities after patterning in a later step to form a conductive material film pattern.

Next, a striped mask pattern is formed on the main surface of the conductive material film at least within the wide groove. The mask pattern material used here is:
For example, resist, SiO ₂ , Si ₃ N ₄ and the like can be used. Next, using this mask pattern, the conductive material film is etched in stripes by a directional etching method such as reactive ion etching, thereby forming a conductive material film pattern that functions as a wiring pattern. At this time, if the thickness of the conductive material film formed in the narrow groove provided in another part of the semiconductor layer is sufficiently thicker than half the width of the groove, the narrow groove The conductive material also remains.

Next, a second separation material such as an insulator is left in the second groove between the conductive material film patterns. As a means of forming this isolation material, for example, after depositing an insulating material so as to sufficiently fill the second groove, the insulating material other than the groove is removed by etching the entire surface, and the insulating material (second isolation material) remains. or the conductive material film pattern is made of impurity-doped polycrystalline silicon,
If it is made of impurity-doped amorphous silicon or metal silicide, a method such as thermal oxidation treatment is used to grow an oxide film directly on the side surfaces of the conductive material film pattern and fill the groove with oxide (second isolation material). It is possible.

By leaving the second separating material in the second groove between the conductive material film patterns using the above-described means,
A wide field region having a striped conductive material film pattern (wiring) surrounded by a thin first separation material film and a thin second separation material film and whose surface is approximately at the same level as the surface of the semiconductor layer is formed. . Bipolar elements and semiconductor layers are separated by such wide or narrow field regions formed as necessary.
A semiconductor device is manufactured by forming MOS type elements and the like.

According to the second invention of the present application, it is possible to form a wide field area with no steps and in which wiring is incorporated, which in turn enables the formation of high-density wiring as well as high performance and reliability. A semiconductor device with increased integration can be obtained.

Next, the third invention of the present application will be explained in detail.

First, as in the first invention described above, a semiconductor layer is selectively etched to a desired depth using a mask pattern to form wide and narrow first trenches.
Next, a thermal oxidation treatment is performed using an oxidation-resistant mask pattern to form a separation material film in the first groove, or after the mask pattern is removed, at least the opening of the first groove is filled. A separator film of insulating material is deposited.

Next, a striped mask pattern is formed on at least the main surface of the separation material film within the wide groove. The mask pattern material used here is:
For example, resist, SiO ₂ , Si ₃ N ₄ and the like can be used. Next, using this mask pattern, the first separation material film is etched into stripes by a directional etching method such as a reactive ion etching method or a wet etching method, thereby forming a second groove portion. In this etching, the separation material film may be selectively etched entirely in the depth direction, or it may be selectively etched so that a thin second separation material remains on the bottom surface. Note that when the former etching is performed, prior to leaving the conductive material in the second groove in the step described later, a thermal oxidation treatment or the like is performed to form an oxide film or the like on the semiconductor layer exposed from the second groove. Form.

Next, the conductive material is left in the second groove.
A method for making this conductive material remain is to deposit a conductive material film on the entire surface to a thickness sufficiently thicker than half the width of the opening of the second groove, and then to etch the conductive material film over the entire surface to remove the remaining conductive material. The surface of the semiconductor layer is made substantially flat with respect to the semiconductor layer. The conductive materials used here are the same as those listed in the second invention.

By leaving the conductive material in the second groove provided in the separation material film by the above-described means, a striped conductive material (wiring) surrounded by the separation material film is formed;
A wide field region whose surface is almost at the same level as the surface of the semiconductor layer is formed, and bipolar type elements, MOS type elements, etc. A semiconductor device is manufactured by forming a semiconductor device.

Therefore, according to the third invention of the present application, similarly to the second invention, it is possible to obtain a semiconductor device that achieves high performance, high reliability, and enables high-density wiring formation to achieve high integration. .

(Example) Hereinafter, an example in which the present invention is applied to manufacturing a bipolar LSI will be described with reference to the drawings.

Example 1 First, a buried layer 202 with a high concentration of n-type impurities is selectively formed in a p-type semiconductor substrate 201, and an n-type epitaxial semiconductor layer 20 with a thickness of about 2 μm is formed on this.
3, a thin thermal oxide film and a thin silicon nitride film are sequentially formed on the surface of the semiconductor layer 203, and then the silicon nitride film and the thermal oxide film corresponding to the area where the wide trench is to be formed are removed by photoetching. Silicon nitride film patterns 204a, 204
Then, thermal oxide film patterns 205a and 205b were formed (as shown in FIG. 6a).

Next, silicon nitride film patterns 204a, 2
04b as a mask, the semiconductor layer 203 was etched to a desired depth to form a wide first groove 206 (as shown in FIG. 6b). Subsequently, thermal oxidation treatment was performed using the silicon nitride film patterns 204a and 204b as oxidation-resistant masks. At this time, as shown in FIG. 6c, an oxide film 207 was selectively grown in the groove 206 as a first isolation material film.

Next, silicon nitride film patterns 204a, 2
04b and thermal oxide film patterns 205a, 205b
After successively removing , a thin silicon nitride film is deposited again on the entire surface, resist patterns 208a to 208d are formed on this by photolithography, and the silicon nitride film is further patterned using these resist patterns 208a to 208d as a mask. Silicon nitride film patterns 209a to 209d were formed (as shown in FIG. 6d). Next, using the resist patterns 208a to 208d as a mask, the exposed portions of the semiconductor layer 203 and the portions extending between the end of the oxide film 207 and the semiconductor layer 203 in contact therewith are etched by reactive ion etching.
03, a narrow second trench 210a is formed in the oxide film 20.
Narrow second groove portions 210b, 21 near the end of 7
0c were formed respectively. At this time, the oxide film 207' remained within the first trench. Thereafter, p-type impurities such as boron are ion-implanted using the resist patterns 208a to 208d as masks, and after removing the resist patterns 208a and 208d, heat treatment is performed to remove the semiconductor layer 203 under each of the grooves 210a to 210b.
P ⁺ regions 211a to 211c reaching as far as the p-type semiconductor substrate 201 were formed in the p-type semiconductor substrate 201 (as shown in FIG. 6e). Next, a CVD-SiO ₂ film 212 was formed over the entire surface from half of the openings of the second grooves 210a to 210c. A sufficiently thick film was also deposited. At this time, the surface of the CVD-SiO ₂ film 212 becomes substantially flat as shown in FIG. 6f. Subsequently, the CVD-SiO ₂ film 212 was etched with ammonium fluoride until the silicon nitride film patterns 209a to 209d on the semiconductor layer 203 were exposed. At this time, as shown in FIG. 6g, CVD-SiO ₂ 212' remained in the second groove portion 210a, forming a narrow field region 213. at the same time,
The second layer between the remaining oxide film 207' and the semiconductor layer 203
CVD-SiO ₂ 21 is also used in the grooves 210b and 210c.
A wide field region 214 was formed in which the oxide film 207' was combined with the remaining oxide film 207'. Continuing, silicon nitride film patterns 209a to 209d
(as shown in FIG. 6g), an npn transistor (not shown) is formed in the island-shaped semiconductor layer separated by narrow and wide field regions 213 and 214 according to a conventional method to form a bipolar transistor. Manufactured LSI.

According to the first embodiment, in addition to the narrow field area 213, there is a wide field area 214.
In addition, as shown in FIG. 6g, an n-type semiconductor layer 203 as an npn transistor forming portion
The level difference between the surface and the surface of the wide field region 214 can be reduced to improve flatness. the result,
When an electrode such as a base extends from the npn transistor region onto the wide field region 214, it is possible to prevent the electrode from being disconnected between the field region 214 and the npn transistor region. In addition, there is a p ⁺ type region 211a below the field regions 213 and 214.
By forming .about.211c, leakage current between npn transistors can be prevented from occurring. Therefore, a bipolar LSI with high performance and high integration can be obtained.

Example 2 First, a buried layer 302 with a high concentration of n-type impurities is selectively formed in a p-type semiconductor substrate 301, and an n-type epitaxial semiconductor layer 303 with a thickness of about 2 μm is formed on this.
After growing a thin silicon nitride film, a thin silicon nitride film is deposited on the surface of the semiconductor layer 303, and the silicon nitride film corresponding to the areas where narrow and wide trenches are to be formed is removed by photo-etching to form silicon nitride film patterns 304a to 304c. was formed (as shown in Figure 7a).

Next, silicon nitride film patterns 304a-3
04c as a mask, the semiconductor layer 303 is etched to a desired depth by reactive ion etching to form a narrow first groove 305a and a wide first groove 305b, and then the same pattern 304a is etched.
Using ~304c as a mask, boron ions are implanted, activated, and p ⁺
Mold regions 306a and 306b were formed. The groove portion 3 continues to be formed on the entire surface including the groove portions 305a and 305b.
The first layer is sufficiently thinner than the depth of 05a and 305b.
A CVD-SiO ₂ film 307 was deposited (as shown in FIG. 7b).

Next, a phosphorus-doped polycrystalline silicon film 3 is formed on the entire surface.
08 is deposited to have a thickness comparable to the depth of the wide groove 305b, and then a striped resist pattern 309a,
309b (as shown in FIG. 7c). Subsequently, the polycrystalline silicon film 308 was subjected to anisotropic etching such as reactive ion etching. At this time, polycrystalline silicon 310 is placed in the narrow groove 305a covered with the thin first CVD-SiO ₂ film 307.
remained. At the same time, polycrystalline silicon patterns 311a and 311b are formed on the sides of the wide groove 305b.
However, the polycrystalline silicon pattern 311 also exists in the groove portion 305b under the resist patterns 309a and 309b.
c and 311d are respectively formed (shown in FIG. 7d).
In this case, if a wet etching method is used, only polycrystalline silicon patterns 311a and 311b corresponding to resist patterns 309a and 309b are formed.

Next, the second CVD-SiO ₂ 312 is applied to the second layer between the polycrystalline silicon patterns 311a to 311d.
The film thickness was sufficiently thicker than half the width of the opening of the groove (as shown in FIG. 7e). Next, CVD−
The SiO ₂ film 312 is etched with ammonium fluoride until the surfaces of the silicon nitride film patterns 304a to 304c are exposed, and then etched between the polycrystalline silicon patterns 311a to 311d in the wide groove 305b.
CVD-SiO ₂ 312'a to 312'c were left (as shown in FIG. 7f). Subsequently, the silicon nitride film patterns 304a to 304c were removed and thermal oxidation treatment was performed. As a result, an oxide film 313 is grown on the surface of the remaining polycrystalline silicon 310 in the narrow groove 305a, and the polycrystalline silicon 310 is surrounded by the first CVD-SiO ₂ film 307 and the oxide film 313.
A narrow field region 314 having (wiring) was formed. At the same time, polycrystalline silicon pattern 31
An oxide film 313 is also grown on the surfaces of 1a to 311d, and the surrounding area is the first CVD-SiO ₂ film 307, CVD-
Polycrystalline silicon patterns 311a to 311d covered with SiO ₂ 312a' to 312c' and oxide film 313
A wide field region 315 having (wiring) was formed (as shown in FIG. 7g). Note that 313' is an oxide film grown on the surface of the semiconductor layer 303. After that, narrow and wide field areas 314 31
Although not shown, an npn transistor was formed in the island-shaped semiconductor layer separated by 5 according to a conventional method to manufacture a bipolar LSI.

According to the second embodiment, the phosphorus-doped polycrystalline silicon patterns 311a to 311d functioning as wiring can be embedded in the wide field region 315, so that high performance, high reliability, and high-density wiring can be formed. This makes it possible to obtain a bipolar LSI that achieves high integration.

Example 3 A silicon nitride film is deposited on the semiconductor layer 303 similar to that in Example 2, and narrow widths on the silicon nitride film are
After resist patterns 316a to 316c were formed by photolithography in areas other than the areas where the wide grooves were to be formed, the silicon nitride film was etched using the patterns 316a to 316c as masks to form silicon nitride film patterns 304a to 304c (No. 8).
(Figure a shown). Next, resist pattern 316
After etching the semiconductor layer 303 to a desired depth using a reactive ion etching method using a to 316c as a mask to form a narrow first groove 305a and a wide first groove 305b, the same resist patterns 316a to 316b are etched. Boron ions are implanted as a mask and activated to form the grooves 305a, 305.
p ⁺ reaches the p-type semiconductor substrate 301 below b
Mold regions 306a and 306b were formed (FIG. 8b).
(Illustrated).

Next, resist patterns 316a to 316c
After removing the CVD-SiO ₂ film 317 on the entire surface to a thickness similar to the depth of the wide groove 305b, the CVD-SiO 2 film 317 in the wide groove 305b is
Striped resist patterns 318a and 318b were formed on the main surface of the SiO ₂ film 317 by photolithography (as shown in FIG. 8c). Next, CVD−
The SiO ₂ film 317 was subjected to anisotropic etching such as reactive ion etching. At this time, CVD-SiO ₂ 319 remained within the narrow groove portion 305a. At the same time, around the sides of the wide groove 305b.
The CVD-SiO ₂ film patterns 319a and 319b are
Groove 3 under resist patterns 318a, 318b
There is also a CVD-SiO ₂ film pattern 319c in 05b,
319d were formed respectively (as shown in FIG. 8d).

Next, thermal oxidation treatment was performed. At this time, groove 3
CVD-SiO ₂ film pattern 319a in 05d
A thin thermal oxide film 320 was grown on the exposed surface of the semiconductor layer 303 between 319d and 319d. Note that since the surface of the semiconductor layer 303 is covered with oxidation-resistant silicon nitride film patterns 304a to 304c, the surface of the semiconductor layer 303 can be prevented from being oxidized. Next, the phosphorus-doped polycrystalline silicon film 321 is deposited by CVD.
-Second between SiO ₂ film patterns 319a to 319d
The film was deposited to a thickness sufficiently thicker than half of the opening of the groove (as shown in FIG. 8e). Subsequently, the polycrystalline silicon film 321 is formed into a silicon nitride film pattern 304.
Etching was performed until the surfaces of layers a to 304c were exposed, leaving patterned polycrystalline silicon 322a to 322c between CVD-SiO ₂ film patterns 319a to 319d in wide groove 305b (as shown in FIG. 8f). Note that when etching this polycrystalline silicon film 321, the silicon nitride film pattern 30
Since 4a to 304c act as a mask, etching of the surface of the semiconductor layer 303 can be prevented.

Next, silicon nitride film patterns 304a-3
After removing 04c, thermal oxidation treatment was performed. As a result, the remaining polycrystalline silicon 322a to 322c
An oxide film 313 is grown on the surface, and the surrounding area is CVD-
Residual phosphorus-doped polycrystalline silicon 322a-322c (wiring) covered with SiO ₂ film patterns 319a-319d, thermal oxide film 320, and oxide film 313
A wide field region 315' was formed. Note that the narrow groove portion 305a in which the aforementioned CVD-SiO ₂ 319 remains functions as a narrow field region 314' (as shown in FIG. 8g). Thereafter, narrow and wide field regions 314', 31
The island-shaped semiconductor layer separated by 5′ is
A bipolar LSI was manufactured by forming an npn transistor (not shown).

According to the third embodiment, the patterned phosphorus-doped polycrystalline silicon 322a to 322 functioning as wiring is formed in the wide field region 315'.
Since c can be embedded, it is possible to obtain a bipolar LSI that has high performance, high reliability, and enables high-density wiring formation to achieve high integration.

Note that in manufacturing the semiconductor device according to the present invention, a p-type semiconductor substrate provided as a semiconductor layer is used.
A type epitaxial layer, a p-type semiconductor substrate laminated twice with an n-type epitaxial layer, or a p-type epitaxial layer and an n-type epitaxial layer laminated on the same substrate may be used.

In manufacturing a semiconductor device according to the present invention, in addition to forming an npn bipolar transistor on an n-type semiconductor layer on a p-type semiconductor substrate as in the above embodiment, for example, a triple diffusion method is used on a p-type semiconductor substrate.
An npn bipolar transistor may also be formed.

The method for manufacturing a semiconductor device according to the present invention is not limited to manufacturing npn bipolar transistors as in the above embodiments, but can be similarly applied to manufacturing other bipolar type semiconductor devices such as I ² L and MOS semiconductor devices.

[Effects of the Invention] As explained above, according to the present invention, arbitrary field regions such as fine or wide fields can be formed in self-alignment mainly with respect to grooves provided in the semiconductor layer without taking mask alignment margins. With the completion,
It is possible to provide a method for manufacturing a semiconductor device such as a bipolar transistor having a structure in which wiring made of a conductive material with excellent flatness is buried in a wide field region.

[Brief explanation of the drawing]

Figures 1 a to e are cross-sectional views showing the manufacturing process of a vertical npn transistor using the conventional selective oxidation method, Figure 2 is a cross-sectional view illustrating the problems of the conventional selective oxidation method, and Figure 3 a , b are cross-sectional views for explaining problems when the conventional selective oxidation method is applied to bipolar transistors, and Figures 4 a to e are process cross-sectional views showing the manufacturing of an npn bipolar transistor already proposed by the applicant. , FIG. 5 is a sectional view showing a state in which a field region is formed by the deformation means shown in FIGS. 4 a to e, FIGS. 7a to 7g are cross-sectional views showing the manufacturing process of a bipolar LSI according to the second embodiment of the present invention, and FIGS. 8a to 8g are cross-sectional views showing the manufacturing process of the bipolar LSI according to the third example of the present invention. 201, 301... p-type semiconductor substrate, 202,
302... n ⁺ type buried layer, 203, 303...
...n-type epitaxial semiconductor layer, 204a, 20
4b...Silicon nitride film pattern, 206, 20
5a, 205b...first groove, 207...oxide film, 210a-210c...second groove, 211
a, 211b, 306a, 306b... p ⁺ type region, 212'... remaining CVD-SiO ₂ film, 213, 3
14,314'...Narrow field area, 21
4,315,315'... wide field area,
307...First CVD-SiO ₂ film, 311a-3
11d...Polycrystalline silicon pattern, 312a'~
312d'...residual CVD-SiO ₂ , 319...remaining
CVD-SiO ₂ , 319a to 319d...CVD-
SiO ₂ film pattern, 322a to 322c...patterned residual polycrystalline silicon.

Claims (1)

[Scope of Claims] 1. A step of forming a first groove in a portion of a semiconductor layer where a wide field region is to be formed, and selectively forming a first isolation material film in this groove so as to fill the groove. The first separation material film is patterned into a stripe shape so that the separation material film remains on the bottom surface of the groove, or after the separation material film is patterned into a stripe shape, the separation material film pattern is exposed between the separation material film patterns. A semiconductor device comprising the steps of: forming another thin isolation material film on the semiconductor layer portion at the bottom of the groove; and leaving a conductive material in the second groove between the isolation material film patterns. Production method. 2. When forming the first groove, simultaneously form a narrow groove in another part of the semiconductor layer, and further form a first separation material film in the first groove, and at the same time, form a narrow groove in another part of the semiconductor layer. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the first separating material remains in the semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the conductive material is impurity-doped polycrystalline silicon, impurity-doped amorphous silicon, or metal silicide.