JPH02173851A - History device - Google Patents

Abstract

PURPOSE:To facilitate the analysis of a fault by performing the comparison between the change pattern of each sequence and the pattern obtained by tracing the control signal of an input/output interface, holding the code corresponding to the relevant sequence as the history information when the coincidence of a comparison is obtained, and holding the trace information as the fault information when no coincidence of comparison is obtained. CONSTITUTION:The expected value is read out of an expected value memory 7 with the address set at a selector 4. This expected value is compared with the value of the control signal of an input/output interface traced by a trace register 9 via a comparing part 10 only when the value of the control signal is changed. When the coincidence of comparison is obtained, the several high- order bits of the address of the memory 7 held by the register 5 are successively stored in a sequence code memory 8 as a unique code showing the relevant sequence. In the case on coincidence of comparison is obtained, the value of the register 5 obtained when the no coincidence of comparison is detected and the value of the register 9 are stored in a fault register 11. As a result, the information of the fault is coded and the analysis of the fault is facilitated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a history device in an input/output system of an information processing device, and more particularly to a history device having an input/output interface and history information holding means for channel internal state information in a channel. Regarding.

[Conventional technology]

Conventionally, this type of input/output system has a history information recording memory of an input/output interface in a channel, and all or a specific signal of the input/output interface is sent to the history information recording memory at a certain period or a specific time. I was recording every step of the way.

Further, the start/stop of the recording was executed according to microinstructions and conditions set by the microinstructions.

[Problem to be solved by the invention]

The above-mentioned conventional input/output system records the signals of the input/output interface one by one, which has the disadvantage that a large amount of information is collected, making subsequent failure analysis difficult.

Furthermore, in the conventional input/output system described above, the start/end of tracing, etc. is performed based on microinstructions and conditions set by the microinstructions, so it is difficult to specify trace conditions that have a wide range of use.

[Means for Solving the Problems] The configuration of the history device of the first invention is such that codes predetermined corresponding to each sequence of input/output interfaces and expected values of change patterns of each sequence are held in the channel. means for comparing the expected value with a value of a change pattern of the input/output interface being executed; and detecting an address of the expected value holding means corresponding to the sequence in which the comparison is being performed. means for holding a predetermined code corresponding to each of the sequences as history information of the input/output interface if the comparison results match over the entire sequence; The present invention is characterized in that it includes means for holding a code corresponding to the detected sequence, the address corresponding to the sequence, and trace results of its input/output interface as fault information.

Further, the configuration of the history device of the second invention includes means for tracing internal state information and input/output interface values in the channel, a memory in which values can be set arbitrarily, and a series of storage in the memory. means for comparing the information with the values of a particular group of signals of said trace means; a trace control circuit that operates when the comparison results match for all words of said memory; and a trace control circuit under the control of said trace control circuit. and a trace memory for storing the channel internal state information and trace results of the input/output interface.

〔Example〕

Next, the first and second inventions will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the first invention, FIG. 2 is a diagram showing the correspondence between addresses and sequences of the address memory 3 of FIG. 1, and FIG. 3 is a block diagram of an embodiment of the second invention. The block diagram, FIG. 4, is a diagram showing the trace conditions set in the trace condition memory 3 of FIG. 3, and FIG. 5 is a diagram showing the time course of the trace signal.

In FIG. 1, channel 1 is connected to input/output device 2 via input/output interface 40. Channel 1 is connected to input/output device 2 via input/output interface 40. In FIG.

The channel 1 includes an address memory 3, a selector 4, a register 5, an adder 6, an expected value memory 7, a sequence code memory 8, a trace register 9, a comparator 10, and a fault register 11.

The input/output interface 40 is connected to the data transfer control unit 12 and the trace register 9 within the channel 1.
Data transfer with the input/output device 2 is executed and managed by the data transfer control unit 11.

The expected value memory 7 stores in advance a change pattern of the state value of the control signal in each sequence of the input/output interface. The address memory 3 holds the start address where the expected value of each sequence in the above-mentioned expected value memory 7 is recorded, and if the allocation is as shown in FIG. 2, the upper 2 bits represent each sequence. It becomes a code.

When the input/output interface moves from one input/output interface sequence to the next sequence, the start address corresponding to the sequence to be executed next is read from the address memory 3 and sent to the register 5 via the selector 4.
is set to The expected value in the expected value memory 7 is read by the address set in the selector 5, and the value of the control signal of the input/output interface traced by the trace register 9 is compared with the comparing unit 10 only when the value changes.
It is compared in. If the comparison result is a match, adder 6
The value of the register 5 is updated by , and the next expected value pattern is compared with the control signal of the input/output interface in the same manner. As a result, if all patterns in the sequence match, the upper few bits of the address in the expected value memory 7 held in the register 5 are sequentially stored in the sequence code memory 8 as a unique code representing the sequence. I'll go.

If the result of the comparison is a mismatch, the value of the register 5 and the value of the trace register 9 at the time when the mismatch is detected are stored/retained in the fault register 11, thereby encoding information at the time of the fault. Therefore, failure analysis becomes easier.

Next, the second invention will be explained with reference to the drawings.

FIG. 3 is a partial block diagram of an embodiment of the second invention.

In Fig. 3, a channel has internal state information and input/output interface values that are captured in a trace data register 2 that sequentially captures them over time, a trace condition memory 3 that can set values arbitrarily, and a trace data register 2. The comparison circuit 4 sequentially compares the specified plurality of bits of the trace data and the value of each word of the trace condition memory 3 over time, and only when a match is obtained for the consecutive words, the output indicates that a match has been detected. A trace control circuit 5 that operates according to the output of a comparison circuit 4 and a trace memory 1 that performs tracing under the control of the trace control circuit 5 are provided.

Here, the specific bits of the trace data register 2 are A, B, C, and D, and the changes in these bits over time are as shown in FIG. Assume that trace conditions are stored in advance as shown in section 2.

The comparison circuit 4 sequentially compares the trace data with a plurality of specific bits starting from word O of the trace condition memory 3.
When the comparison results up to word 3 match successively over time, the output indicates that a match has been detected. Figures 4 and 5
In the example shown in the figure, the trace condition and the trace data match from time t3 to t6, the output of the comparator circuit 4 indicates a match detection at time t6, the trace control circuit 5 operates according to this output, and the trace data at that time In response to requests, instructions such as starting or stopping tracing are given to the trace memory 1.

〔Effect of the invention〕

The channel and input/output device interfaces operate according to a predetermined sequence. Therefore, as explained above, according to the first invention, the change pattern of each sequence is stored in advance, and this is compared with the change pattern when tracing the control signal of the input/output interface, and if they match, the change pattern is stored. For example, the code corresponding to that sequence is retained as history information, and in the case of a mismatch, the code indicating the sequence in which the mismatch occurred, the position within the sequence, and trace information of the input/output interface are retained as failure information. Since information at the time of a failure is coded, this has the effect of facilitating failure analysis.

Further, according to the second invention, internal state information of the channel,
By recording input/output interface information and controlling the tracer based on data trace conditions and temporal changes in a specific signal group, it is possible to specify trace conditions that can be used in a wide range of applications.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the first invention, FIG. 2 is a diagram showing the correspondence between addresses and sequences in the address memory 3 of FIG. 1, and FIG. 3 is an embodiment of the second invention. FIG. 4 is a diagram showing the trace conditions set in the trace condition memory 3 of FIG. 3, and FIG. 5 is a diagram showing the time course of the trace signal. 1... Channel, 2... Input/output device, 3... Address memory, 4... Selector, 5... Register, 6
. . . Adder, 7. Expected value memory, 8. Sequence code memory, 9. Trace register, 10.
... Comparison unit, 11 ... Fault register, 40 ... Input/output interface, 100 ... Trace memory, 20
0...Trace data register, 300...Trace condition memory, 400...Comparison circuit, 500...Trace control circuit.

Claims (1)

[Claims] 1. Expected value holding means for holding in a channel a predetermined code corresponding to each sequence of an input/output interface and an expected value of a change pattern of each sequence, and the expected value and execution. means for comparing the value of the change pattern of the input/output interface in the input/output interface, means for detecting the address of the expected value holding means corresponding to the sequence in which the comparison is being performed, and means for distributing the comparison result to the entire sequence. means for retaining a predetermined code corresponding to each of the above sequences as history information of the input/output interface if there is a match; A history device comprising means for holding trace results of the corresponding address and its input/output interface as fault information. 2. In the channel, means for tracing its internal state information and input/output interface values, a memory in which values can be arbitrarily set, a series of stored information in the memory, and a specific signal group of the tracing means. a means for comparing the value of
a trace control circuit that operates when the comparison results match for all words of the memory; and a trace memory that stores the channel internal state information and the trace result of the input/output interface under the control of the trace control circuit. 2. The history device according to claim 1, further comprising: a.