JPH02171918A - Access system for frame memory - Google Patents

Abstract

PURPOSE:To speed up picture display and memory access by providing the system with an address conversion circuit for converting an address at the time of writing display data on a frame memory. CONSTITUTION:When a CPU 11 specifies an address of a frame memory 14 and sends display data, the address conversion circuit 15 executes address conversion so that data groups sent from the frame memory 14 almost simultaneously while mutually corresponding to each other between divided display areas 12a, 12b of a display device 12 are written in the adjacent addresses of the memory 14. The address conversion information is sent to the frame memory 14 through a random access port 14a and the display data are written in the converted addresses. The display data are read out from the memory 14 through a serial access port 14b and the images are simultaneously displayed on the divided display areas 12a, 12b of the display device 12. Consequently, the picture display can be rapidly executed and the CPU 11 can access the frame memory 14 simultaneously with the picture display without waiting the sending of the picture display data.

Description

[Detailed Description of the Invention] (Summary) A frame memory access method for simultaneously transmitting and displaying data to different display areas on a display device using a liquid crystal display panel with a display area divided into upper and lower halves via an address conversion circuit. The purpose of this technology is to use dual-port memory that stores data in a different order to enable high-speed display on a large LCD panel, as well as to receive access from the CPU without waiting time. It has a divided display device, a random access port, and a serial access port, a frame memory in which display data to be sent to the display device is stored and expanded, and an address specification for the frame memory, and a frame memory for storing and developing display data sent to the display device. A control unit that writes display data via a random access port, and an address conversion circuit that is disposed between the frame memory and the control unit and converts an address when writing display data to the frame memory,
The address conversion circuit performs address conversion so that the data groups that correspond to each other between the divided display areas and are sent out from the frame memory almost simultaneously are written to adjacent addresses in the frame memory. .

[Industrial application field]

The present invention relates to a frame memory access method for simultaneously sending and displaying data to different display areas in a display device using a liquid crystal display panel with a display area divided into upper and lower halves and a dual port memory as a frame memory for display.

(Prior Art) A conventional liquid crystal display device uses a single-port random access memory to display data from the upper left to the right side of the liquid crystal display panel, and then from the upper line to the lower line. , data was sequentially read from random access memory and displayed. In this case, processing is performed in a cycle in which each time data is read from the random access memory for displaying data, the data is then accessed once from the CPU for writing or reading.

In recent years, liquid crystal display panels have become larger, but even if the number of dots on the screen increases, if the display panel is used without being divided, the screen will flicker and become difficult to see, so as shown in Figure 3, the display panel A system in which the display area of 1 is divided into upper and lower panels, an upper panel 2 and a lower panel 3, has come into practical use.

When a single-port random access memory is used for such a display device, the access method is to read one piece of display data for each different display area in order to display the data, and then receive one access from the CPU. It is processed in this cycle.

[Problem to be solved by the invention]

However, in such conventional memory access methods, when displaying data on a large liquid crystal display panel that has a display area divided into upper and lower halves, access from the CPU to the random access memory is performed by reading and displaying data. The problem is that the access from the CPU is only received once compared to the 2 times, and the waiting time for the data reading and display processing to be completed becomes long, which slows down the processing.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a memory that enables high-speed display on a large liquid crystal display panel and that can be accessed by the CPU without waiting time. The purpose is to provide an access method.

[Failure to solve the problem]

FIG. 1 is a diagram showing the basic configuration of the present invention.

In this figure, reference numeral 12 represents a display device whose display area is divided into upper and lower sections, and 14 represents a frame memory constituted by a dual port memory having a random access port 14a and a serial access port 14b. Reference numeral 11 denotes a CPU as a control unit that specifies the address of the frame memory 14 and writes display data to the frame memory via the random access port 14a.
15 is an address conversion circuit disposed between the frame memory 14 and the CPU II, which converts addresses when writing display data to the frame memory.

(Function) When writing display data to the frame memory 14, the CPU
When the II specifies the address of the frame memory 14 and sends the display data, the address conversion circuit 15 sends out the display data from the frame memory 14 almost simultaneously and correspondingly between the divided display areas 12a and 12b of the display device 12. so that data groups (hereinafter referred to as the same sending data group) are written to adjacent addresses in the frame memory 14;
Convert address. This converted address information is sent to the frame memory 14 through the random access port 14a, and display data is written to the converted address.

Such a display data writing operation is repeated to expand the display data to the frame memory 14, while the display data is read from the frame memory 14 through the serial access port 14a and sent to the display device 12. In reading display data from the frame memory 14 in this case, since the same sending data group has already been stored in adjacent addresses, if the display data is read out serially, the divided display area of the display device 12 can be read out. 12a and 12b are simultaneously displayed on the image.

(Example) FIG. 2 is a diagram showing an image display device to which the present invention is applied. As shown in the embodiment drawing of FIG. 2, this image display device includes a display device 12 having a divided display area, a display timing generation circuit 13 that instructs the display device 12 when to display data, and a random access Port 14a
and a frame memory 14 having a serial access port 14b that can be accessed independently of the random access port and that can continuously read data constituting the same transmission data group;
When writing display data to the frame memory 14 through the random access port 14a, the same sending data group is sent to adjacent addresses of the frame memory 14. an address conversion circuit 15 that performs address conversion for writing to the display timing generation circuit 1;
a selection circuit 16 that selects and outputs one of the transfer address output from the CPU II and the address output from the CPU II based on the address selection signal output from the display timing generation circuit 13; A part of the data continuously output from the port 14b side is transmitted to the display timing generation circuit 13.
The display device 1 is latched according to the output timing of the display device 1.
It is provided with data latch means 17 for simultaneously displaying data in two divided display areas 12a and 12b. The frame memory 14 mentioned above is manufactured by Toshiba (model number: TC5).
24256) and Fujitsu (model number: MB81C42)
51) can be used.

Hereinafter, in this embodiment, the effect when the display screen of 1024 dots horizontally by 768 dots vertically is divided into upper and lower halves of 384 dots vertically will be illustrated and explained.

As shown in FIGS. 2 to 4, the configuration required for this method to function is that the display device 12 has a display screen of 1024 dots horizontally x 384 dots vertically and an upper panel 12a of 1024 dots horizontally x 384 dots vertically. It has a lower panel 12b of 384 dots and a liquid crystal display panel 12c of 1024 dots horizontally by 768 dots vertically divided into two parts. In this case, if a frame memory 14 with an 8-bit/address configuration is used as the frame memory 14, the display device 12
When the data is displayed, the logical address will be as follows.

As shown in Fig. 3, if the address is not converted when writing to the random access port 14a, the writing is as shown in Fig. 2 (a).
As shown in , the data for the upper panel 12a is 0 to 7.
The data at address 0 is stored as the first data in the x0 area, the data at address 1 is stored as the second data in the 8-15x0 area, and the data at address 127 is stored as the 128th data in the 1016-1023xO area. Store the data, and 12
8x384=49151 as the second data
After storing the address data, the data changes to the data for the lower panel 12b, and the lower panel 12b is stored in the 0~7X38-j area.
The data at address 49152 is stored as the first data for the
~491 for lower panel 12b in 1023X767 area
Data at address 98303 is stored as the 52nd data.

Against this 1.・When writing display data to the frame memory 14 through the random access board)-14a, when address information from the CPU II is input to the address conversion circuit 15, the address conversion circuit 15 calculates a new address using the following formula. do.

Address range from 0 to 49151 (The above data is converted to an even address.) New address = 2 x old address ... (1) 49152
Address range from ~98303 (lower address is converted to odd address) New address = 2 x (old address - 49152) + 1
...(2) Therefore, as shown in Figure 3 (b), storage locations 0 to 7X
0 as the first data for the upper panel 12a in the O area.
After storing the address data, store the data of address 49152 as the first data for the lower panel 12b in the 8-15×0 area, and similarly, store the data for the upper panel 12a and the data for the lower panel I2b. Data is stored alternately in even and odd addresses, and finally 1008-1
491 for upper panel 12a in 015 x 767 area
Store the data at address 49151 as the 52nd data, and store 98303 as the data at address 49152 L for the lower panel 12b in the 023x7.67 area.
Store address data.

If the data storage state after this conversion is sequentially stored in the virtual memory 14' whose width is doubled, as shown in C, the storage state will be as shown in FIG. 3(C). The number indicating one line of this virtual memory 14' (the number outside the frame on the left side in FIG. 2(c)) is multiplied by 256 as a transfer address from the display timing generation circuits 1 and 3 to the selection circuit J6.
The data is sent to the frame memory 14 via.

Address conversion [In the address conversion path 15, when address information is input from the CPU II, it performs the above-mentioned at-l-female conversion and sends it to the frame output 14 via the selection circuit 16.

The selection circuit 16'C inputs the converted CPU address from the random access port 14a to the serial access port 1 for display when accessing the CPU II frame memory.
At the time of transfer (transport) to 4b, the transfer address is sent to frame mail 14.

In the frame memory 14, data for one line is transferred from the random access port 14a to the serial access port 14b and displayed according to the transfer address (input from the display timing/timing generation circuit 13) at the transfer timing. Timing generation circuit 13
The display data is sent out according to the serial sending timing signal input from.

Regarding the display data sent out from the frame memory 14, the data for the lower panel 12b is sent as is to the display device 12 side, and the data for the upper panel 12a is sent to the data latch 17.
is latched and sent to the display device 12 side in synchronization with the data for the lower panel 12b.
The data for the upper panel 12a and the data for the lower panel 12b are sent out so that they are displayed simultaneously.

As described above, in this embodiment, the data at address 0 is sent out first, the data at address 49152 is sent out second, and the data at address 49152 is sent out as the first group of identical sending data from the serial access port 14b of the frame memory 14, and the next group of identical sending data is sent out. Toshi C
The data at address 1 is sent out third, the data at address 49153 is sent out fourth, and in the same way, two data at a time are read and sent out, and the upper panel 12a and lower panel 1 of the display screen are read.
2b, and during that period - while the sending data group is being sent out, the random access memory side can receive access from the CPU II side, making it possible to speed up screen display, and at the same time, the CPU II can transfer the frame memory 14 to the screen. Access can be made without waiting for display data to be sent.

In other words, in the frame memory 14, the random access memory side is memory accessed (writing, reading) from the CPU side, regardless of the operation of the serial access memory.
Since the CPU can do this, there is no waiting time, while the serial access memory side simply performs the first call 7.
By simply setting the address, data can only be read out sequentially due to the characteristics of the frame memory 14.

(Effects of the Invention) As described above, in the present invention, using the frame memory 14,
When writing display data to the random access port 14a, the data input to the frame memory 14 is sent to the serial access port 14a by the address conversion circuit 15. 14. The same data group can be output from b to the display device at high speed, and the CP
The random access port 14a can be accessed from the UII regardless of the operation of the serial access port 14b, and screen display and memory access can be speeded up.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a configuration diagram showing a frame memory access method according to an embodiment of the present invention, and FIG. 3 is an explanatory diagram showing an example of address conversion according to the embodiment. , FIG. 4 is an explanatory diagram showing an example of an upper and lower two-part type liquid crystal display panel. 11...CPU 12...Display device 12a...Upper panel 12b...Lower panel 12c...Liquid crystal display panel 13...Display timing generation circuit 14...Frame memory 14a...Random access Port 14b...Serial access port 15...Address conversion circuit 16...Selection circuit 17...Data latch means

Claims (1)

[Claims] A display device (12) having a divided display area, a random access port (14a) and a serial access port (14b), and display data sent to the display device is stored and expanded. Frame memory (14)
a control unit (11) that specifies the address of the frame memory (14) and writes display data to the frame memory via the random access port (14a); and the frame memory (14) and the control unit (11). ), the address conversion circuit (15) converts addresses when writing display data to the frame memory, and the address conversion circuit (15) is arranged between the divided display areas. Frame memories (14
) is sent from the frame memory (1
4) A frame memory access method characterized by converting addresses so that they are written to adjacent addresses within.