JPH02168638A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH02168638A
JPH02168638A JP63324189A JP32418988A JPH02168638A JP H02168638 A JPH02168638 A JP H02168638A JP 63324189 A JP63324189 A JP 63324189A JP 32418988 A JP32418988 A JP 32418988A JP H02168638 A JPH02168638 A JP H02168638A
Authority
JP
Japan
Prior art keywords
electrode pad
metal
semiconductor device
metal layer
metal wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63324189A
Other languages
English (en)
Inventor
Shoichi Ogura
小倉　昭一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63324189A priority Critical patent/JPH02168638A/ja
Publication of JPH02168638A publication Critical patent/JPH02168638A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/4813—Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特にその構造に関する。
〔従来の技術〕
従来、この種の半導体装置は、−主面に電子素子を含む
電子回路が形成された半導体チップを、耐湿性や耐外力
をもたせるように、セラミックや耐湿性のある樹脂の絶
縁体で覆い、半導体チップの入出力端子である電極端子
と接続されるリードを所定の長さだけ前記絶縁体から露
出させて組立ちれていた。
第３図は従来の一例を示す半導体チップを露出させた半
導体装置の部分平面図である。例えば、この半導体装置
がゲートアレー〇場合では、あらかじめ、標準的な論理
回路ゲートが多数形成されている半導体チップ２をリー
ドフレームのアイランド１に載置し、多数の論理ゲート
から所要の論理ゲートを選び、この論理ゲートの入出力
端子である電極パッド３ａとこの電極パッド３ａに対応
するリード４とをアルミニウム等の金属細線５で接続し
、残りのダミー電極パッド３ｂは金属細線を接続しない
ままにして、これらの構成体をセラミックや樹脂である
絶縁体６で覆うように組立られている。
〔発明が解決しようとする課題〕
しかしながら、上述した従来の半導体装置では、金属細
線が接続されていないダミー電極バッドがあり、この電
極パッドは、絶縁体が樹脂である場合は、電極パッドと
樹脂とが直接接触することになる。また、この電極パッ
ド上には、パッシベーション膜が形成されていないので
、樹脂体から浸入する水分に侵され易いという問題があ
る。すなわち、電極パッド上のアルミニュウム金属がこ
の浸入した水分により腐食を起し、更にこの腐食が発展
して電極パッドの周囲の配線を断線するという問題を引
起すことになる。
本発明の目的は、電極パッドや配線が腐食したり断線を
起さない構造をもつ半導体装置を提供することにある。
〔課題を解決するための手段〕
本発明の半導体装置は、−主面に電子素子を含む電子回
路が形成された半導体チップと、この半導体チップの入
出力端子である電極パッドとこの電極パッドと対応して
金属細線で接続される・リードと、このリードの先端部
を所定の長さで露出させて前記半導体チップ及び前記金
属細線並びに前記リードと前記金属細線との接続部を覆
う絶縁体とを有する半導体装置において、少なくとも前
記金属細線が接続されてない前記電極パッドを覆い形成
された前記金属細線と同質材料の金属層を有することを
備え構成される。
〔実施例〕
次に、本発明について図面を参照して説明する。
第１図及び第２図は本発明の一実施例を示す半導体チッ
プを露出させた半導体装置の部分平面図である。この半
導体装置は、金属細線５が接続されている電極パッド３
ａと同様に、ワイヤボンディング装置を利用して、例・
えば、アルミニウムの金属細線５の一端を金属ボール状
にし、この金属ボール７を金属細線５が接続されていな
いダミー電極バッド３ｂに溶着することである。それ以
外は従来例と同じである。
このことは、ハ・ソシベーション膜より露出するアルミ
ニウム金属で蒸着されたダミー電極バッド３ｂの面を被
せる金属層を作ることになる。従って、従来のダミー電
極バッド３ｂに比べ金属層が厚くなり、たとえ、腐食さ
れても、断線に至る迄の時間は非常に長くなるという利
点がある。
また、このときの金属細線５ｂの他端は、例えば、第１
図に示すように、ダミー電極バッド３ｂの最も近いリー
ド４に接続して良いし、また、場合により、金属ボール
７の近接する部分で切断しても良い。更に、第２図に示
すように、隣接したダミー電極パッド３ｂ同志を互いに
金属細線５Ｃで接続しても良い。特に、この方法は、電
極パッドの間隔が狭い場合に適合する。
上述した金属層含形成する他の方法として、例えば、半
導体チップの電極パッドをパッシベーション膜より露出
させた後で、金属層を厚く蒸着し、この金属層の電極パ
ッド以外の部分をエツチング除去して厚い金属層を電極
パッド上に形成しても良い。この場合は半導体チップの
全部の電極パッドに金属層を形成したことになる 〔発明の効果〕 以上説明したように本発明は、未使用の電極パ・ソドを
覆う金属ボールや金属層を形成することによって、絶縁
体より浸入してくる水分等により電極パッドや配線が腐
食されることなく、また、配線の断線が起りにくい半導
体装置が得られるという効果がある。
【図面の簡単な説明】
第１図及び第２図は本発明の一実施例を示す半導体チッ
プを露出させた半導体装置の部分平面図、第３図は従来
の一例を示す半導体チップを露出させた半導体装置の部
分平面図である、 １・・・ア・イランド、２・・・半導体チプ、３ａ・・
・電極パッド、３ｂ・・・ダミー電極バッド、４・・・
リード、５．５ａ、５ｂ、５Ｃ・・・金属細線、６・・
・絶縁体、７・・・金属ボール。

Claims (1)

    【特許請求の範囲】
  1. 一主面に電子素子を含む電子回路が形成された半導体チ
    ップと、この半導体チップの入出力端子である電極パッ
    ドとこの電極パッドと対応して金属細線で接続されるリ
    ードと、このリードの先端部を所定の長さで露出させて
    前記半導体チップ及び前記金属細線並びに前記リードと
    前記金属細線との接続部を覆う絶縁体とを有する半導体
    装置において、少なくとも前記金属細線が接続されてな
    い前記電極パッドを覆い形成された前記金属細線と同質
    材料の金属層を有することを特徴とする半導体装置。
JP63324189A 1988-12-21 1988-12-21 半導体装置 Pending JPH02168638A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63324189A JPH02168638A (ja) 1988-12-21 1988-12-21 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63324189A JPH02168638A (ja) 1988-12-21 1988-12-21 半導体装置

Publications (1)

Publication Number Publication Date
JPH02168638A true JPH02168638A (ja) 1990-06-28

Family

ID=18163068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63324189A Pending JPH02168638A (ja) 1988-12-21 1988-12-21 半導体装置

Country Status (1)

Country Link
JP (1) JPH02168638A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5473514A (en) * 1990-12-20 1995-12-05 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
US7705473B2 (en) * 2003-09-29 2010-04-27 Agere Systems Inc. Methods and apparatus for determining pad height for a wire-bonding operation in an integrated circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482640A (en) * 1987-09-25 1989-03-28 Mitsubishi Electric Corp Semiconductor integrated circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6482640A (en) * 1987-09-25 1989-03-28 Mitsubishi Electric Corp Semiconductor integrated circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5473514A (en) * 1990-12-20 1995-12-05 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
US5613295A (en) * 1990-12-20 1997-03-25 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board and method for manufacturing same
US5646830A (en) * 1990-12-20 1997-07-08 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
US5715147A (en) * 1990-12-20 1998-02-03 Kabushiki Kaisha Toshiba Semiconductor device having an interconnecting circuit board
US7705473B2 (en) * 2003-09-29 2010-04-27 Agere Systems Inc. Methods and apparatus for determining pad height for a wire-bonding operation in an integrated circuit

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