JPH02168637A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02168637A JPH02168637A JP32428088A JP32428088A JPH02168637A JP H02168637 A JPH02168637 A JP H02168637A JP 32428088 A JP32428088 A JP 32428088A JP 32428088 A JP32428088 A JP 32428088A JP H02168637 A JPH02168637 A JP H02168637A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- resin
- semiconductor device
- sealing resin
- mounting piece
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 41
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 239000011347 resin Substances 0.000 claims abstract description 44
- 229920005989 resin Polymers 0.000 claims abstract description 44
- 238000007789 sealing Methods 0.000 claims abstract description 38
- 239000000725 suspension Substances 0.000 claims abstract description 6
- 239000002184 metal Substances 0.000 abstract 4
- 230000000717 retained effect Effects 0.000 abstract 2
- 238000000465 moulding Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 230000009194 climbing Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Moulds For Moulding Plastics Or The Like (AREA)
- Injection Moulding Of Plastics Or The Like (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、リードフレームを樹脂封止して成る電力用等
の半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION <Industrial Field of Application> The present invention relates to a method of manufacturing a semiconductor device for power use or the like in which a lead frame is sealed with resin.
〈従来技術〉
従来の樹脂封止型の電力用半導体装置の製造方法につい
て説明する。<Prior Art> A conventional method for manufacturing a resin-sealed power semiconductor device will be described.
まず、第８図の如く、横枠１と、該横枠１に一端が支持
された複数のリード端子２，３．４と、該複数のリード
端子２，３．４のうち載置片吊りリード端子４に設けら
れた半導体素子載置片５と、該載置片５を連結支持する
載置片吊りタイバー６と、前記各リード端子２，３．４
を連結するリード吊りタイバー７とから成るリードフレ
ーム８に、半導体素子９をグイボンドし、ボンディング
ワイヤーＩＯにより内部結線を施して回路形成する。First, as shown in FIG. 8, a horizontal frame 1, a plurality of lead terminals 2, 3.4 whose ends are supported by the horizontal frame 1, and a mounting piece of the plurality of lead terminals 2, 3.4 are suspended. A semiconductor element mounting piece 5 provided on the lead terminal 4, a mounting piece hanging tie bar 6 that connects and supports the mounting piece 5, and each of the lead terminals 2, 3.4.
A semiconductor element 9 is firmly bonded to a lead frame 8 consisting of a lead suspension tie bar 7 that connects the leads, and internal connections are made using bonding wires IO to form a circuit.
そして、第９図の如く、リードフレーム８をモールド金
型１１．１２にセットアツプ後、横枠１とタイバー６．
７とを支持し、封止樹脂１３を用いてトランスファーモ
ールド法により樹脂封止する。この樹脂封止後の状態を
第１０図に示す。As shown in FIG. 9, after setting up the lead frame 8 in the molding die 11.12, the horizontal frame 1 and the tie bar 6.
7 are supported, and resin-sealed using a sealing resin 13 by a transfer molding method. The state after resin sealing is shown in FIG.
その後、タイバー６．７を切断して第１１図の如き半導
体装置が完成する。Thereafter, the tie bars 6.7 are cut to complete the semiconductor device as shown in FIG.
なお、第１０図中１４は封止樹脂１３により形成された
外装、１５は放熱板取付用ビス孔である。In addition, in FIG. 10, 14 is an exterior formed of the sealing resin 13, and 15 is a screw hole for attaching a heat sink.
〈 発明が解決しようとする問題点 〉しかし、従来の
樹脂封止型の電力用半導体装置の製造方法では、第８図
の如く、リードフレーム８に載置片吊りタイバー６が設
けられているので、リードフレーム８を樹脂封止した後
にタイバー６を切断しても、第２図の如く、タイバー６
の切断片６ａが露出する。<Problems to be Solved by the Invention> However, in the conventional method of manufacturing a resin-sealed power semiconductor device, as shown in FIG. , even if the tie bars 6 are cut after the lead frame 8 is sealed with resin, the tie bars 6 will not work as shown in FIG.
The cut piece 6a is exposed.
このため、半導体装置に放熱板を取付けたとき、タイバ
ー６の切断片６ａと放熱板との絶縁耐圧に制約が生じ、
絶縁シートが必要となる。Therefore, when a heat sink is attached to a semiconductor device, there are restrictions on the dielectric strength between the cut pieces 6a of the tie bars 6 and the heat sink.
An insulation sheet is required.
そこで、本発明は、上記問題点に鑑み、放熱板の取付時
に絶縁シートを必要とせず、かつ放熱板と高絶縁耐圧を
有する半導体装置の提供を目的とする。SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to provide a semiconductor device that does not require an insulating sheet when attaching a heat sink and has a heat sink and a high dielectric strength.
〈 問題点を解決するための手段 〉
本発明による問題点解決手段は、第１〜５図の如く、載
置片吊りリード端子２９のみに支持された半導体素子載
置片３０を有するリードフレーム２１に、半導体素子２
０を搭載し、該リードフレーム２１をモールド金型３４
．３５およびこの金型３４３５内に突出する位置決めピ
ン３６．３７により支持し、封止樹脂２２を射出後、該
封止樹脂２２が半硬化状態になったときに前記位置決め
ピン３６．３７を成形品の表面まで持ち上げる製造方法
である。<Means for solving the problem> The problem solving means according to the present invention is a lead frame 21 having a semiconductor element mounting piece 30 supported only by the mounting piece suspension lead terminal 29, as shown in FIGS. 1 to 5. , semiconductor element 2
0, and the lead frame 21 is placed in the mold 34.
．． 35 and positioning pins 36, 37 protruding into the mold 3435, and after injecting the sealing resin 22, when the sealing resin 22 is in a semi-hardened state, the positioning pins 36, 37 are attached to the molded product. This is a manufacturing method that lifts the material up to the surface.
〈作用〉
上記問題点解決手段において、成形時に位置決めピン３
６．３７により載置片３０を支持しているので、従来の
ようにリードフレーム２１に載置片３０を連結する載置
片吊りタイバーを設けなくても、金型３４，３５内で載
置片３０を移動させることなく位置決めできる。そして
、位置決めピン３６．３７は、封止樹脂２２が半硬化状
態になったときに成形品の表面まで持ち上げるので、リ
ードフレームを完全に樹脂封止した半導体装置が完成す
る。<Function> In the above problem solving means, the positioning pin 3 is
Since the mounting piece 30 is supported by 6.37, the mounting piece 30 can be placed in the molds 34 and 35 without providing a tie bar for hanging the mounting piece to connect the mounting piece 30 to the lead frame 21 as in the conventional case. Positioning can be performed without moving the piece 30. Then, the positioning pins 36 and 37 lift up to the surface of the molded product when the sealing resin 22 is in a semi-hardened state, thereby completing a semiconductor device in which the lead frame is completely sealed with the resin.
したがって、リードフレームの出力部を除きその他の部
分が露出することがなく、半導体装置に放熱板を取付け
る際に絶縁シートが不要となり、かつ放熱板と高絶縁耐
圧を有する半導体装置を得ることができる。Therefore, other parts except the output part of the lead frame are not exposed, an insulating sheet is not required when attaching a heat sink to a semiconductor device, and a semiconductor device having a heat sink and a high dielectric strength voltage can be obtained. .
〈実施例〉 以下、本発明の一実施例について図面により説明する。<Example> An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例を示す半導体装置の製造方法
における樹脂封止前のリードフレームの状態を示す平面
図、第２図は同じくモールド金型内に封止樹脂を射出し
た状態を示す断面図、第３図は同じくモールド金型内で
封止樹脂が半硬化した状態を示す断面図、第４図は同じ
くモールド金型内で封止樹脂が硬化した状態を示す断面
図、第５図は封止樹脂の粘度と成形時間の関係を示す図
、第６図は同じくその製造方法において樹脂封止後の状
態を示す平面図、第７図（ａ）は同じくその半導体装置
の完成品を示す側面図、第７図（ｂ）は同じくその断面
図である。FIG. 1 is a plan view showing the state of a lead frame before resin sealing in a semiconductor device manufacturing method according to an embodiment of the present invention, and FIG. 2 similarly shows a state after the sealing resin is injected into the mold. FIG. 3 is a cross-sectional view showing a semi-hardened state of the sealing resin within the mold, and FIG. 4 is a cross-sectional view showing the hardened state of the sealing resin within the mold. Figure 5 is a diagram showing the relationship between the viscosity of the sealing resin and molding time, Figure 6 is a plan view showing the state after resin sealing in the same manufacturing method, and Figure 7 (a) is a diagram showing the completed semiconductor device. The side view showing the product, FIG. 7(b) is also a sectional view thereof.
まず、本発明の樹脂封止型の電力用半導体装置の構造に
ついて説明する。First, the structure of the resin-sealed power semiconductor device of the present invention will be explained.
第７図（ａＸｂ）の如く、半導体素子２０と、該半導体
素子２０が搭載されるリードフレーム２１と、該リード
フレーム２Ｉを封止樹脂２２により樹脂封止されて成る
外装２３とから構成され、前記リードフレーム２１がそ
の出力部２１ａを除いて外装２３により完全に覆われて
いる。As shown in FIG. 7 (aXb), it is composed of a semiconductor element 20, a lead frame 21 on which the semiconductor element 20 is mounted, and an exterior 23 in which the lead frame 2I is sealed with a sealing resin 22, The lead frame 21 is completely covered with an exterior 23 except for its output portion 21a.
なお、第７図（ａ）（ｂ）中、２４は放熱板取付用ビス
孔、２５は半導体素子２０とリードフレーム２１とを内
部結線するボンディングワイヤーである。In addition, in FIGS. 7(a) and 7(b), 24 is a screw hole for attaching a heat sink, and 25 is a bonding wire for internally connecting the semiconductor element 20 and the lead frame 21.
前記リードフレーム２１は、第１図の如く、前記横枠２
６と、該横枠２６に一端が示されたリード端子２７，２
８．２９と、該リード端子２７．２８．２９のうち載置
片吊りリード端子２９のみに支持された半導体素子２０
が搭載される載置片３０と、前記各リード端子２７，２
８．２９のみを連結支持するリード吊りタイバー３１と
から回路パターンを形成している。The lead frame 21 is connected to the horizontal frame 2 as shown in FIG.
6, and lead terminals 27, 2, one end of which is shown on the horizontal frame 26.
8.29, and the semiconductor element 20 supported only by the mounting piece hanging lead terminal 29 among the lead terminals 27, 28, and 29.
mounting piece 30 on which is mounted, and each of the lead terminals 27, 2
A circuit pattern is formed from lead suspension tie bars 31 that connect and support only 8.29.
前記リード端子２７．２８は、前記載置片吊りリード端
子２９を挟んで対向配置されるとともに、前記半導体素
子２０とボンディングワイヤー２５により内部結線され
ている。The lead terminals 27 and 28 are arranged opposite to each other with the mounting piece suspension lead terminal 29 interposed therebetween, and are internally connected to the semiconductor element 20 by a bonding wire 25.
該載置片吊りリード端子２９の先端には、前記載置片３
０が一体形成され、該載置片３０は、第１〜４図の如く
、放熱効果が向上するように肉厚に形成された載置片本
体３２と、該本体３２の略中央に形成されたモールド金
型挿入用孔３３とから成る。The mounting piece 3 is attached to the tip of the mounting piece hanging lead terminal 29.
As shown in FIGS. 1 to 4, the placement piece 30 is formed approximately in the center of the placement piece main body 32, which is thickly formed to improve the heat dissipation effect. and a mold insertion hole 33.
次に、本発明半導体装置の製造方法について説明する。Next, a method for manufacturing the semiconductor device of the present invention will be explained.
まず、第１図の如く、半導体素子２０をリード端子２９
の載置片３０にグイボンドし、半導体素子２０とリード
端子２７．２８とをボンディングワイヤー２５により内
部結線を施し回路形成する。First, as shown in FIG.
The semiconductor element 20 and the lead terminals 27 and 28 are internally connected by the bonding wire 25 to form a circuit.
そして、リードフレーム２１を、第２図の如く、下面モ
ールド金型３４にセットアツプ後、上面モールド金型３
５の凸部３５ａを金型挿入用孔３３に挿入して横枠２０
およびリード端子２７，２８゜２９を支持し、さらにモ
ールド金型３４．３５内から突出した位置決めピン３６
．３７で載置片３０の一端部３０ａ、３０ｂを支持し、
モールド金型３４．３５内に封止樹脂２２をトランスフ
ァーモールド法により射出する。After setting up the lead frame 21 in the lower molding die 34 as shown in FIG.
Insert the convex portion 35a of No. 5 into the mold insertion hole 33 and
and a positioning pin 36 that supports the lead terminals 27, 28° 29 and protrudes from inside the mold die 34.35.
．． 37 supports one end portions 30a and 30b of the mounting piece 30,
The sealing resin 22 is injected into the molds 34 and 35 by transfer molding.
このように、位置決めピン３６．３７によりリード端子
２９のみに支持された載置片３０を支持しているので、
従来のようにリードフレーム２１に載置片３０を連結す
る載置片吊りタイバーを設けなくても、モールド金型３
４．３５内で載置片３０を移動させることなく位置決め
できる。In this way, since the mounting piece 30 supported only by the lead terminal 29 is supported by the positioning pins 36 and 37,
The molding die 3 does not have to be provided with a mounting piece hanging tie bar that connects the mounting piece 30 to the lead frame 21 as in the conventional case.
It is possible to position the mounting piece 30 within 4.35 mm without moving it.
その後、封止樹脂２２の硬化前に位置決めピン３６．３
７を、第３図の如く、成形品の表面まで持ち上げる。Thereafter, before the sealing resin 22 hardens, the positioning pin 36.3 is
7 to the surface of the molded product as shown in FIG.
この位置決めピン３６．３７を持ち上げるタイミングは
、封止樹脂の粘度と成形時間とに依存する。すなわち、
第５図の如く、封止樹脂２２を射出して成形時間Ａの範
囲までは、封止樹脂２２の粘度が低いため、第２図の如
く、位置決めピン３６．３７で載置片３０を支持する。The timing of lifting the positioning pins 36 and 37 depends on the viscosity of the sealing resin and the molding time. That is,
As shown in FIG. 5, the viscosity of the sealing resin 22 is low until the molding time A range after injecting the sealing resin 22, so as shown in FIG. do.
そして、封止樹脂２２が半硬化状態となる成形時間Ｂの
範囲になったときに、第３図の如く、位置決めピン３６
゜３７を成形品の表面まで持ち上げる。このとき、位置
決めピン３６．３７を持ち上げても封止樹脂２２の粘度
がある程度高くなっている（半硬化状態）ため載置片３
０は動かない。そして、成形時間Ｃの範囲になると、第
４図の如く、封止樹脂２２は硬化する。Then, when the molding time B reaches the range where the sealing resin 22 is in a semi-hardened state, as shown in FIG.
゜37 Lift up to the surface of the molded product. At this time, even if the positioning pins 36 and 37 are lifted, the viscosity of the sealing resin 22 is still high to some extent (semi-hardened state), so the placement piece 3
0 does not move. Then, when the molding time reaches the range C, the sealing resin 22 hardens as shown in FIG.
そして、樹脂封止後、タイバー３１を切断して第７図（
ａＸｂ）の如き半導体装置が完成する。After resin sealing, the tie bar 31 is cut and shown in Fig. 7 (
A semiconductor device such as aXb) is completed.
このように、封止樹脂２２を射出後、位置決めピン３６
．３７を封止樹脂２２の半硬化状態のときに成形品表面
まで持ち上げることにより、第７図（ａ）の如く、リー
ドフレーム２１の出力ｇ５２１ａを除いて完全に樹脂封
止できる。In this way, after injecting the sealing resin 22, the positioning pin 36
．． 37 to the surface of the molded product when the sealing resin 22 is in a semi-hardened state, it is possible to completely seal the lead frame 21 with the resin except for the output g521a, as shown in FIG. 7(a).
したがって、半導体装置に放熱板を取付ける際に絶縁シ
ートが不要となり、かつ放熱板と高絶縁耐圧を有する半
導体装置を得ることができる。Therefore, an insulating sheet is not required when attaching a heat sink to a semiconductor device, and a semiconductor device having a heat sink and a high dielectric strength can be obtained.
なお、本発明は、上記実施例に限定されるものではなく
、本発明の範囲内で上記実施例に多くの修正および変更
を加え得ることは勿論である。It should be noted that the present invention is not limited to the above embodiments, and it goes without saying that many modifications and changes can be made to the above embodiments within the scope of the present invention.
〈発明の効果〉
以上の説明から明らかな通り、本発明によると、成形時
に位置決めピンに上り載置片を支持しているので、従来
のようにリードフレームに載置片を連結する載置片吊り
タイバーを設けなくても、金型内で載置片を移動させる
ことなく位置決めできる。<Effects of the Invention> As is clear from the above description, according to the present invention, the mounting piece is supported by climbing up to the positioning pin during molding, so that the mounting piece is not connected to the lead frame as in the conventional case. Even without providing a hanging tie bar, the mounting piece can be positioned within the mold without moving it.
そして、位置決めピンは、封止樹脂が半硬化状態になっ
たときに成形品の表面まで持ち上げるので、リードフレ
ームを完全に樹脂封止した半導体装置が完成する。Then, the positioning pins are lifted up to the surface of the molded product when the sealing resin is in a semi-hardened state, thereby completing a semiconductor device in which the lead frame is completely resin-sealed.
したがって、リードフレームの出力部を除きその他の部
分が露出することがなく、半導体装置に放熱板を取付け
る際に絶縁シートか不要となり、かつ放熱板と高絶縁耐
圧を有する半導体装置を得ることかできるといった優れ
た効果がある。Therefore, no parts other than the output part of the lead frame are exposed, no insulating sheet is required when attaching a heat sink to a semiconductor device, and a semiconductor device having a heat sink and high dielectric strength can be obtained. It has such excellent effects.
第１図は本発明の一実施例を示す半導体装置の製造方法
における樹脂封止前のリードフレームの状態を示す平面
図、第２図は同じくモールド金型内に封止樹脂を射出し
た状態を示す断面図、第３図は同じくモールド金型内で
封止樹脂が半硬化した状態を示す断面図、第４図は同じ
くモールド金型内で封止樹脂が硬化した状態を示す断面
図、第５図は封止樹脂の粘度と成形時間の関係を示す図
、第６図は同じくその製造方法において樹脂封止後の状
態を示す平面図、第７図（ａ）は同じくその半導体装置
の完成品を示す側面図、第７図（ｂ）は同じくその断面
図、第８図は従来の半導体装置の製造方法における樹脂
封止前のリードフレームの状態を示す平面図、第９図は
同じくリードフレームをモールド金型に固定した状態を
示す断面図、第１Ｏ図は同じく樹脂封止後の状態を示す
平面図、第１１図は同じくその半導体装置の完成品を示
す側面図である。
２０；半導体素子、２１コリートフレーム、２２封止樹
脂、２６；横枠、２７，２８，２９：リード端子、３０
：載置片、３１：タイバー、３４，３５：モールド金型
、３６．３７：位置決めピン。
出 願 人 シャープ株式会社FIG. 1 is a plan view showing the state of a lead frame before resin sealing in a semiconductor device manufacturing method according to an embodiment of the present invention, and FIG. 2 similarly shows a state after the sealing resin is injected into the mold. FIG. 3 is a cross-sectional view showing a semi-hardened state of the sealing resin within the mold, and FIG. 4 is a cross-sectional view showing the hardened state of the sealing resin within the mold. Figure 5 is a diagram showing the relationship between the viscosity of the sealing resin and molding time, Figure 6 is a plan view showing the state after resin sealing in the same manufacturing method, and Figure 7 (a) is a diagram showing the completed semiconductor device. FIG. 7(b) is a side view showing the product, FIG. 7(b) is a cross-sectional view thereof, FIG. 8 is a plan view showing the state of the lead frame before resin sealing in the conventional semiconductor device manufacturing method, and FIG. 9 is the same lead frame. FIG. 10 is a sectional view showing the frame fixed to the mold, FIG. 1O is a plan view showing the state after resin sealing, and FIG. 11 is a side view showing the finished product of the semiconductor device. 20; Semiconductor element, 21 Coret frame, 22 Sealing resin, 26; Horizontal frame, 27, 28, 29: Lead terminal, 30
: Placement piece, 31: Tie bar, 34, 35: Mold die, 36.37: Positioning pin. Applicant Sharp Corporation
Claims (1)
片を有するリードフレームに、半導体素子を搭載し、該
リードフレームをモールド金型およびこの金型内に突出
する位置決めピンにより支持し、封止樹脂を射出後、該
封止樹脂が半硬化状態になつたときに前記位置決めピン
を成形品の表面まで持ち上げることを特徴とする半導体
装置の製造方法。A semiconductor element is mounted on a lead frame having a semiconductor element mounting piece supported only by the mounting piece suspension lead terminal, and the lead frame is supported by a mold die and positioning pins protruding into this die, and then sealed. 1. A method of manufacturing a semiconductor device, which comprises lifting the positioning pin to the surface of a molded product when the sealing resin is in a semi-hardened state after injecting the sealing resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63324280A JP2596995B2 (en) | 1988-12-21 | 1988-12-21 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63324280A JP2596995B2 (en) | 1988-12-21 | 1988-12-21 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02168637A true JPH02168637A (en) | 1990-06-28 |
| JP2596995B2 JP2596995B2 (en) | 1997-04-02 |
Family
ID=18164041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63324280A Expired - Fee Related JP2596995B2 (en) | 1988-12-21 | 1988-12-21 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2596995B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014065176A (en) * | 2012-09-25 | 2014-04-17 | Yoshii Denshi Kogyo:Kk | Method for manufacturing insert molding |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60130129A (en) * | 1983-12-16 | 1985-07-11 | Nec Corp | Method for sealing isolation-type semiconductor element with resin |
| JPS6362239A (en) * | 1986-08-27 | 1988-03-18 | エスジ−エス・マイクロエレットロニカ・エス・ピ−・エ− | Manufacture of semiconductor device enclosed in plastic capsule |
| JPS63159422A (en) * | 1986-12-23 | 1988-07-02 | Sumitomo Bakelite Co Ltd | Insulating resin paste for semiconductor |
-
1988
- 1988-12-21 JP JP63324280A patent/JP2596995B2/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60130129A (en) * | 1983-12-16 | 1985-07-11 | Nec Corp | Method for sealing isolation-type semiconductor element with resin |
| JPS6362239A (en) * | 1986-08-27 | 1988-03-18 | エスジ−エス・マイクロエレットロニカ・エス・ピ−・エ− | Manufacture of semiconductor device enclosed in plastic capsule |
| JPS63159422A (en) * | 1986-12-23 | 1988-07-02 | Sumitomo Bakelite Co Ltd | Insulating resin paste for semiconductor |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2014065176A (en) * | 2012-09-25 | 2014-04-17 | Yoshii Denshi Kogyo:Kk | Method for manufacturing insert molding |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2596995B2 (en) | 1997-04-02 |
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