JPH02164280A - Driving method for insulated gate type bipolar transistor - Google Patents

Abstract

PURPOSE:To prevent a short-circuit accident by providing a period of short- circuiting a gate and an emitter with a resistor when ON and OFF states are switched. CONSTITUTION:An anti-parallel circuit of an N-channel IGBT 10 and a free wheel diode 11 is connected in series with an antiparallel circuit of a P-channel IGBT 20 and a free wheel diode 21, it is connected to a DC power source, and alternately turned ON and OFF for power conversion. A short-circuit switch 30, a short-circuit resistor, an edge detector 32A and a waiting time circuit 32 of a timer 32B are provided, and a pulse becoming a logic H signal is output only for a predetermined period of time from the time point of inputting of an ON signal. As a result, a short-circuit accident in which the series circuit of the IGBT simultaneously turned ON can be avoided.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention connects an N-channel insulated gate bipolar transistor (hereinafter abbreviated as IC; BT) and a P-channel IGBT in series, When a DC power supply is connected to both ends of this series circuit and both IGBTs are turned on and off alternately to perform power conversion, this is to avoid an accident in which both IGBTs turn on at the same time and short circuit the power supply. I
This invention relates to a method for driving a GBT.

[Conventional technology]

IGBT has the advantages of bipolar transistors,
In other words, it is easy to increase the breakdown voltage and capacity, and the metal oxide semiconductor field effect transistor (hereinafter referred to as MOSFE)
This is an element that has the advantages of the T-type (abbreviated as T), that is, it can perform high-speed switching and is easy to drive.

FIG. 5 is a circuit diagram showing an equivalent circuit of an N-channel IGBT.

As shown in FIG. 5, it consists of an N-channel MOSFET I (1; BT is N-channel MO3FETIOA, NPN) run risk IOB, PNP) run risk IOC and a resistor 10D. The collector and emitter of the transistor IOB are connected in parallel, and the NPN transistor IO
B and the PNP transistor IOC can be used to form a circuit.

To turn on this N-channel IGBT, a forward bias voltage is applied between its gate (labeled G) and emitter (labeled E). As a result, N-channel MO3FET
A channel is formed in the IOA, which becomes conductive,
Since the emitter-base of the PNP run risk 10C is forward biased, conduction occurs between the collector (symbol C) of the N-channel IGBT and the emitter E.

On the contrary, the gate G of this N-channel IGBT
When a reverse bias voltage is applied across the emitter E, the N-channel MOSFET Tl0A turns off and the PNP
The base current of the transistor IOC is cut off and the corresponding PN
Since the P transistor IOC is turned off, the 20N channel IGBT is turned off.

FIG. 6 is a circuit diagram showing an isotube circuit of a P-channel ICBT.

P channel I GBT is P channel MO3FET20
It is composed of an ASP N P transistor 20B, an NPN transistor 20C, and a resistor 20D, and in order to turn on the 20P channel IGBT, the gate G of this
・Apply reverse bias voltage between emitter E. As a result, a channel is formed in the P-channel MOSFET 20A and it becomes conductive, so NP, N) run risk 2
A forward bias is applied between the base and emitter of 0C, and the current P-channel IGBT starts to conduct.

Furthermore, when a forward bias voltage is applied between the gate G and emitter E of the P-channel IGBT, the P-channel MO3FET
2OA is turned off, cutting off the base current to the NPN transistor 20C, which turns off this NPN transistor 20C, and as a result, this 8P channel I
GBT is turned off.

By the way, power conversion can be performed by connecting two IGBTs in series, connecting a power supply to both ends of this series circuit, and repeatedly turning both IGBTs on and off alternately. It is well known.

However, even if an off signal is applied to an IGBT that is in an on state, the current cannot be immediately interrupted because there is a charge accumulation time in the IGBT.

Therefore, two IGBTs connected in series as described above,
When performing power conversion by alternately turning on and off,
Appropriate measures must be taken to prevent both from turning on at the same time and causing a power short circuit.

FIG. 7 is a circuit diagram showing a conventional example of an IGBT drive circuit with a short-circuit prevention function added when power conversion is performed by connecting two IGBTs in series.

In FIG. 7, an N-channel IGBTIO with a freewheeling diode 11 connected in antiparallel and a P-channel IGBT20 with a freewheeling diode 21 connected in antiparallel are connected in series, and a DC current is applied to both ends of the series circuit. Connect tA1.

On/off signals for driving the IGBTs that alternately turn on and off both IGBTIOs and 20 are isolated and supplied by the photocoupler 2. Now, Hotoka'Pla 2-1
When a current is passed to the next side as an on/off signal, the current flows to the secondary side of the MOSFET 8, turning off the MOSFET 8, and thus turning on the transistor 13. This transistor 1
3 turns on, the gate drive current tA12 is applied as a forward bias voltage between the gate and emitter of the N-channel IGBTIO via the transistor 13 and the upper arm resistance circuit 14, turning on the N-channel IGBTIO. At the same time, the gate-emitter of the P-channel IGBT 20 is reverse biased via the lower arm resistance circuit 24, so the P-channel IGBT 20
BT20 will be turned off.

At this time, since the diode 14C constituting the upper arm resistance circuit 14 is reverse biased, only the resistance 14A acts on this upper arm resistance circuit 14, so its resistance value is large, but the lower arm resistance The diode 24C constituting the circuit 24 is forward biased, so the lower arm resistor circuit 24 is connected to the resistor 24A and the resistor 24.
Since a parallel circuit with B is formed, its resistance value is small.

In a voltage-driven semiconductor element, the switching time becomes longer as the value of the resistance connected to its gate increases. Therefore, in the circuit shown in FIG. 7, the upper arm, ie, the N-channel IGBTIO, is turned on later, and the lower arm, ie, the P-channel IGBT 20, is turned off earlier.

Next, when the primary current of photocoupler 2 is turned off, this 2
The next f current is also turned off, and a voltage is applied between the gate and source of MOSFET 8, turning this MOSFET 8 on. As a result, the transistor 23 is turned on, and the voltage of the gate drive power supply 22 is applied as a reverse bias voltage between the gate and emitter of the N-channel IGBTIO, turning it off. At this time, the diode 14C is forward biased. Therefore, this N channel I GBTlo
The resistance value of the upper arm resistance circuit 14 connected to the gate of the upper arm resistor circuit 14 becomes small, so that the N-channel IGBTIO is turned off quickly.

At the same time, the gate drive voltage a22 is connected to the P-channel IC;
A forward bias voltage is applied between the gate and emitter of BT20 to turn it on, but at this time the diode 24C is reverse biased and the lower arm resistance circuit 24
The resistance value of is large, so the P-channel IGBT 20 is turned on late.

[Problems to be Solved by the Invention] As described above, in the conventional IGBT drive circuit, the resistance value of the gate circuit of the rGBT that is about to be turned on is increased to lengthen the turn-on time, and the IGBT that is about to be turned off is increased. Conversely, by reducing the resistance value of the gate circuit and shortening its turn-off time,
This prevents short-circuit accidents where both the upper and lower arms are turned on.

In this case, the short-circuit prevention period depends on the value of the resistor connected to the gate, and (1) the input capacitance of the BT and its time constant, so the short-circuit prevention period cannot be set to a reliable value. was there.

Therefore, an object of the present invention is to provide a reliable short-circuit prevention period in order to avoid a short-circuit state in which both are turned on when two lGBTs are connected in series and both are turned on and off alternately. It's all about setting.

[Means for Solving the Problems] In order to achieve the above object, the driving method of the present invention has the following features:
The emitter of the N-channel insulated gate bipolar transistor is coupled to the emitter of the P-channel insulated gate bipolar transistor, and a DC power source is connected between the collectors of both insulated gate bipolar transistors.
In a driving method in which both insulated gate bipolar transistors are alternately turned on and off, when switching between the on state and off state of both insulated gate bipolar transistors, the gate and emitter of each insulated gate bipolar transistor are For example, a period is provided in which they are short-circuited via a resistor.

[Operation] The present invention provides the following advantages in a series circuit of two IGBTs.
When switching one IGBT from on to off and the other IGBT from off to on, these ICs; Dissipates the charge accumulated in the After this certain period of time has passed, these I
By giving the GBT an on or off signal to be switched, it is possible to avoid a short-circuit accident in a series circuit of IGBTs and to set a reliable short-circuit prevention period.

〔Example〕

FIG. 1 is a functional block diagram showing the gist of the present invention.

In FIG. 1, an anti-parallel circuit of an N-channel IGBTIO and a freewheeling diode 11 and an anti-parallel circuit of a P-channel IGBT 20 and a freewheeling diode 21 are connected in series, and this series circuit is connected to a direct current (not shown). Connect to power supply, N-channel IGBTIO
Power conversion is performed by alternately repeating on/off operations of the P-channel IGBT 20 and the P-channel IGBT 20.

Now, considering the case where the upper arm, that is, N channel IGBTlo, turns from off to on, the lower arm, that is, P
Channel IGBT 20 will be switched from on to off. Therefore, initially switch 16 is off and switch 2
6 is on.

Note that the short circuit switch 30 is off.

When a signal that turns on the upper arm, that is, a logic H signal, is applied, the output of the inverting element 33 becomes a logic OR signal, so the switch 26 is immediately turned off via the AND element 25. At the same time, the waiting time circuit 32, which is composed of an edge detection circuit 32A and a timer 32B, outputs a pulse that becomes a logic H signal for a predetermined time determined by the timer 32B from the time when this ON signal is input. Therefore, the shorting switch 30 is ON only while the wait time circuit 32 is generating a pulse, and when this pulse ends, the switch 16 is ON, and the gate drive power supply 12 forward biases the N-channel IGBTIO. Make this conductive.

As mentioned above, the short circuit switch 30 is closed only for a predetermined period of time (that is, the period during which the waiting time circuit 32 is generating pulses) from the moment when the signal that turns on the upper arm is output. Due to the closed circuit, there is a connection between the gate and emitter of the N-channel rGBT10, and P
Between the gate and emitter of the channel IGBT 20,
Since a short circuit occurs through the short circuit resistor 31, both these IGB
A zero volt voltage is applied between the gates and emitters of T10 and T20, and both IGBTIO and T20 are turned off.

When the switch 16 is on and the switch 26 is off, when an off signal, that is, a logic signal is input next, the output of the AND element 15 changes to a logic signal, and the switch 16 is immediately turned off. However, the edge detection circuit 32A is
Detects the edge of switching from an on signal to an off signal,
In addition, due to the action of the timer 32B, the wait time circuit 32 outputs a pulse signal with a time width determined by the timer 32B, so that between the gate and emitter of both IGBTIO and 20,
It is short-circuited via the short-circuiting resistor 31 for a period of this pulse width, and at the same time as this pulse ends, the switch 26 is turned on, and the gate drive power supply 22 forward biases the P-channel 1GBT 20, making it conductive.

FIG. 2 is a timing chart showing the operation of the functional block circuit of the present invention shown in FIG. Changes in the output signal of the time circuit 32, FIG. 2(c) shows changes in the output signal of the inverting element 34, and FIG.
Figure 2 (e) shows the change in the output signal of the AND element 15, Figure 2 (e) shows the change in the output signal of the AND element 25, and Figure 2 (g) shows the change in the output signal of the AND element 25. Each of them shows the change in gate-emitter voltage of .

As is clear from FIG. 2, during the period when the waiting time circuit 32 is outputting the pulse signal, the ICBT gate
It can be seen that the emitter voltage is zero, and after this pulse signal ends, an on signal is given to one of the IGBTs.

FIG. 3 is a circuit diagram showing an example of implementing the functional block circuit of the present invention shown in FIG. 1.

In this FIG. 3, N-channel IGBTIO1P-channel IC, BT20, freewheel diode 11
and 21), gate drive power supplies 12 and 22) and short circuit resistor 3
Since the name, purpose, and function of 1 are the same as those already described in the functional block circuit of FIG. 1, their explanation will be omitted.

The operation of the embodiment circuit shown in FIG. 3 is as follows. In other words, an on signal is input to photocoupler 2, and one of these
When a current flows to the next side, the current flows to the phototransistor 2B via the photodiode 2A, so the input of the Schmitt inversion element 45 becomes a logic low signal, and the output thereof becomes a logic high signal.

A wait time circuit 47 is configured by a resistor 47A, a capacitor 47B, and an exclusive OR element 47C, and the logic signal from the Schmitt inversion element 45 changes to a logic H signal (or from a logic H signal to a logic OR signal). The wait time circuit 47
The output is a logic H signal, and this time becomes the aforementioned short circuit prevention period.

When the ON signal is input to the photocoupler 2 and the output of the Schmitt inversion element 45 is a logic H signal as described above, the output of the inversion element 48 is a logic logic signal, so the output of the AND element 27 is also a logic logic signal. becomes.

Therefore, the MO corresponding to switch 26 in FIG.
The gate potential of 3FET28 becomes zero volts, and the current
O3FET28 is turned off. At the same time, the output pulse of the waiting time circuit 47 described above turns on the MO3FET 40, which corresponds to the shorting switch 30 in FIG. 1, only during this pulse period. As a result, the charges accumulated in the parasitic capacitance between the gate and emitter of the N-channel IGBT 10 and the similar accumulated charges in the P-channel IGBT 20 are
and the short-circuit resistor 31.

At the end of the output pulse period of the waiting time circuit 47, that is, at the end of the short-circuit prevention period, when its output changes to a logic high signal, the MO3FET 40 turns off, but at the same time, the output of the inverting element 4G changes to a logic high signal. Therefore, the output of the NAND element 17 becomes a logical OR signal. Therefore, MO3FET1B corresponding to switch 16 in FIG.
Since its emitter potential is H and its gate potential is L, the PjMO3FET 18 is turned on. As a result, the voltage of the gate drive/driving power supply 12 is changed to MO
The voltage is applied between the gate and emitter of the N-channel IGBTIO and the P-channel IGBT 20 through the path of 3FET 18 - resistor 41 → short-circuit resistor 31, and as a result, the P-channel IGBT 20 remains off, but the N-channel IGBTIO
C, BTIO is turned on.

Next, when the primary side current of the photocoupler 2 is turned off, the secondary side phototransistor 2B is turned off and the input of the Schmitt inversion element 45 changes to a logic H signal, and its output becomes a logic logic signal. In response to the change in the signal, the waiting time circuit 47 outputs a pulse signal having the same time width as described above. During the output period of this pulse signal, MO3FE is
By turning on T40 and shorting between both IGBTIOs and the gate/emitter of 20 via the shorting resistor 31,
The accumulated charge is discharged. At this time, the N-channel IGBTIO, which had been on until then, turns off, and the P-channel I (1; BT20, which is in the off state) continues to be in the off state, but when the short circuit prevention period ends, the operation is opposite to that described above. , the P-channel IGBT 20 in the off state is turned on.

FIG. 4 is a timing chart showing the operation of the embodiment circuit shown in FIG. 3, and FIG.
Figure (b) shows changes in the output signal of the Schmitt inversion element 45,
FIG. 4(C) shows changes in the output signal of the waiting time circuit 47, FIG. 4(D) shows changes in the output signal of the inverting element 46, and FIG.
4(e) shows the change in the output signal of the inverting element 48, FIG. 4(f) shows the change in the output signal of the NAND element 17, and FIG. (ch) is TG
Each shows the change in voltage between the gate and emitter of BT 10 and BT 20.

〔Effect of the invention〕

According to this invention, when two IGETs are connected in series and both are turned on and off alternately to perform power conversion, first, both IGBTs are turned off, and then both IGBTs are turned off.
By short-circuiting the gate and emitter of the IGBT via a resistor for a certain period of time to discharge the accumulated charge, one of the IGBTs is driven to turn on.
Avoiding short-circuit accidents where the series circuits of ETs turn on at the same time,
This provides the effect of reliably setting the short-circuit prevention period of the brackets.

[Brief explanation of the drawing]

Fig. 1 is a functional block diagram showing the gist of the present invention, Fig. 2 is a timing chart showing the operation of the functional circuit of the invention shown in Fig. 1, and Fig. 3 is a functional block diagram showing the invention shown in Fig. 1. FIG. 4 is a timing chart showing the operation of the example circuit shown in FIG. 3, and FIG. 5 is a circuit diagram showing an example of implementing the functional block circuit of FIG.
A circuit diagram showing the equivalent circuit of BT, Figure 6 is P channel I
C. A circuit diagram showing the equivalent circuit of BT, Figure 7 shows two IG
FIG. 2 is a circuit diagram showing a conventional example of an fGBT drive circuit with a short-circuit prevention function added when performing power conversion by connecting BTs in series. 1... DC power supply, 2... Photocoupler, 2A... Photodiode, 2B... Phototransistor, 10...
・N-channel IGBT, IOA...N-channel MO3
FET. 11, 21...freewheel diode, 12.2
2... Gate drive power supply, 14... Upper arm resistance circuit, 20... P channel IGBT, 2OA... P channel MO5FET, 24... Lower arm resistance circuit, 30
...Short circuit switch, 31...Short circuit resistance, 32.47
...Waiting time circuit, 32A...edge diagram Σ

Claims (1)

[Claims] 1) The emitter of an N-channel insulated gate bipolar transistor is coupled to the emitter of a P-channel insulated gate bipolar transistor, and a DC power supply is connected between the collectors of both insulated gate bipolar transistors. In a driving method in which both insulated gate bipolar transistors are alternately turned on and off, when switching between the on state and off state of both insulated gate bipolar transistors, the gate of each insulated gate bipolar transistor and A method for driving an insulated gate bipolar transistor characterized by providing a period in which the emitter is short-circuited. 2) A method for driving an insulated gate bipolar transistor according to claim 1, wherein the gate and emitter of each insulated gate bipolar transistor are short-circuited via a resistor.