JPH02163973A - Insulated-gate type bipolar transistor - Google Patents
Insulated-gate type bipolar transistorInfo
- Publication number
- JPH02163973A JPH02163973A JP31789288A JP31789288A JPH02163973A JP H02163973 A JPH02163973 A JP H02163973A JP 31789288 A JP31789288 A JP 31789288A JP 31789288 A JP31789288 A JP 31789288A JP H02163973 A JPH02163973 A JP H02163973A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- type
- resistance
- source
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 8
- 238000000034 method Methods 0.000 abstract description 3
- 238000000605 extraction Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 62
- 239000000758 substrate Substances 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 210000004303 peritoneum Anatomy 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/083—Anode or cathode regions of thyristors or gated bipolar-mode devices
- H01L29/0834—Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/1015—Shape
- H01L2924/10155—Shape being other than a cuboid
- H01L2924/10158—Shape being other than a cuboid at the passive surface
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、電力用ＭＯ３ＦＥＴのドレイン層の電子と正
孔の２種のキャリア伝導度変調を利用して導通状態での
電圧降下を小さくする絶縁ゲート型バイポーラトランジ
スタ （以下ＭＢＴと略す）に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention utilizes two types of carrier conductivity modulation of electrons and holes in the drain layer of a power MO3FET to reduce the voltage drop in a conductive state. The present invention relates to an insulated gate bipolar transistor (hereinafter abbreviated as MBT).
ＭＢＴは、従来の電力用たて型ＭＯＳ Ｆ ＥＴと同様
な構造でありながら、バイポーラトランジスタを内部に
含み、いわゆる伝導度変調を利用することによって導通
状態での電圧降下を小さくできる利点を持たせたもので
ある。その断面構造は第２図に示す通りで、ドレイン層
ｌとしてのｐ′基板上にｎ゛バフ２１層２介してれ一高
抵抗層３がエピタキシャル法で積層され、このｎ−高抵
抗層３の表面部にｐ形ベース層４が、さらにその表面部
にｎ゛ソース１１５形成されている。このソース層５と
高抵抗層３の間の表面層６にｎチャネルを形成するため
、ゲート絶縁膜７１を介して多結晶シリコンゲート電極
８が設けられている。このゲート１陽の設けられる側の
半導体素体表面からはＡｕが拡散されている。そして、
ソース層５の一部とその間のベース層４には、ゲート電
１８を覆うｗＡ緑腹膜７２開口部でソース電極９が接触
するが、ベース層４の表面部にはこの接触部を含めてｐ
゛領域１０が設けられている。このソース電極９に対向
して、ｐ゛ ドレイン層１にはドレイン電極１１が接触
している。このような半導体素子は、ゲート″を極８に
ソース電極９に対して正の電圧を印加すると、ゲート絶
縁膜７１直下のｐ形ベース層４の表面１！６にｎチャネ
ルが形成され、ソース層５から電子がチャネル６を通り
、高抵抗層３と低抵抗層２からなる０層を通ってｐ゛層
ｌ注入され、それに呼応してｐ゛ ドレイン層１からｎ
゛バフフ１層２通ってｎ−層３に正孔が注入され、ｎ＝
層３が伝導度変調をおこして低抵抗となる。また、ゲー
）１ｉｔ８ｉ８をソース電極９と同電位または負にバイ
アスすることによってチャネルが消滅し、阻止状態とな
り、いわゆるスイッチング素子としてのはたらきを持つ
。Although the MBT has a structure similar to a conventional power vertical MOSFET, it contains a bipolar transistor inside and has the advantage of reducing voltage drop in the conductive state by using so-called conductivity modulation. It is something that Its cross-sectional structure is as shown in FIG. 2, in which a high-resistance layer 3 is epitaxially laminated on a p' substrate as a drain layer l with an n-buff 21 layer 2 interposed therebetween. A p-type base layer 4 is formed on the surface thereof, and an n source 115 is further formed on the surface thereof. In order to form an n-channel in the surface layer 6 between the source layer 5 and the high resistance layer 3, a polycrystalline silicon gate electrode 8 is provided with a gate insulating film 71 interposed therebetween. Au is diffused from the surface of the semiconductor element on the side where the gate 1 is provided. and,
The source electrode 9 contacts a part of the source layer 5 and the base layer 4 between them at the opening of the wA green peritoneum 72 that covers the gate electrode 18, but the surface part of the base layer 4 including this contact part
A region 10 is provided. Opposed to this source electrode 9, a drain electrode 11 is in contact with the p-drain layer 1. In such a semiconductor element, when a positive voltage is applied to the source electrode 9 with the gate as the pole 8, an n-channel is formed on the surfaces 1 to 6 of the p-type base layer 4 directly under the gate insulating film 71, and the source Electrons from the layer 5 pass through the channel 6 and are injected into the p' layer l through the zero layer consisting of the high-resistance layer 3 and the low-resistance layer 2, and in response, the p' drain layer 1 to n
゛Hole is injected into n- layer 3 through buff 1 layer 2, n=
Layer 3 causes conductivity modulation and has low resistance. Furthermore, by biasing the gate electrode 1it8i8 to the same potential as the source electrode 9 or to a negative bias, the channel disappears and becomes a blocking state, so that it functions as a so-called switching element.
このＭＢＴは、ＭＯ３型構造を有しているがゆえに、バ
イポーラトランジスタに比較して高速性能を有しており
、例えば６００ Ｖ 、 １００ Ａ素子でオン時１０
０〜２００ｎｓ 、オフ時１μＳ程度のスイッチング速
度が得られている。この高速化を図ることによりさらに
多くの用途が期待される。スイッチング速度は素子のオ
ンする速度とオフする速度で決まるが、特にオフ速度は
、ｎ−層３に存在する電子を引きぬく速度に支配される
。従って如何に電子を速く引きぬくかという点に問題が
存在する。Because this MBT has an MO3 type structure, it has high-speed performance compared to bipolar transistors.
A switching speed of 0 to 200 ns and about 1 μS when off is obtained. By increasing this speed, even more applications are expected. The switching speed is determined by the speed at which the element turns on and the speed at which it turns off, and the off speed in particular is dominated by the speed at which electrons present in the n-layer 3 are extracted. Therefore, the problem is how to extract electrons quickly.
本発明の課題は、上記の問題に対応して電子を速く引き
ぬくことができるｎチャネルＭＢＴを提供することにあ
る。An object of the present invention is to provide an n-channel MBT that can quickly extract electrons in response to the above-mentioned problems.
上記の課題の解決のために、本発明は、高抵抗のｎ形層
の一側の表面部に選択的にｐ形のベース層を、さらにそ
のベース層の表面部に選択的にｎ形の低抵抗ソース層を
備え、高抵抗のｎ形層とソース層の間にはさまれたベー
ス層のチャネル形成領域表面上に絶縁膜を介してゲート
電極が設けられ、ソース層のチャネル形成領域と反対側
およびそれにｌｉＪ接するベース層の表面にソース電極
が接触し、前記高抵抗のｎ形層の他側には低抵抗のｎ形
バンファ層を介して低抵抗のｐ形ドレイン層が設けられ
、そのｐ形ドレイン層にドレイン電極が接触するＭＢＴ
において、ｐ形ドレイン層はソース電極に対向する領域
が薄く、その周囲の領域が厚いものとする。In order to solve the above problems, the present invention selectively forms a p-type base layer on one surface of a high-resistance n-type layer, and further selectively forms an n-type base layer on the surface of the base layer. A gate electrode is provided via an insulating film on the surface of the channel formation region of the base layer, which has a low resistance source layer and is sandwiched between the high resistance n-type layer and the source layer, and is connected to the channel formation region of the source layer. A source electrode is in contact with the surface of the base layer on the opposite side and in contact therewith, and a low-resistance p-type drain layer is provided on the other side of the high-resistance n-type layer via a low-resistance n-type bumper layer, MBT whose drain electrode is in contact with its p-type drain layer
In the p-type drain layer, the region facing the source electrode is thin and the surrounding region is thick.
ｐ形ドレイン層にソース電極に対向して厚さの薄い領域
が存在するので、オフ時にｎ形高抵抗層に存在する電子
はドレイン層の厚い領域を経ないで、この薄い領域から
引き抜かれるので高速のオフ速度が得られる。厚い９貫
域はバッファ層を介しての正孔の注入の際に役立つ。Since there is a thin region in the p-type drain layer facing the source electrode, the electrons present in the n-type high resistance layer when off are extracted from this thin region without passing through the thick region of the drain layer. A fast off speed is obtained. The thick 9-channel region aids in hole injection through the buffer layer.
第１図は本発明の一実施例を示し、第２図と共通の部分
には同一の符号が付されている。この場合はｎ−シリコ
ン基板を用い、その−面にｎ゛バフ２１層２形成したの
ち、他面側のｐ°屡ｌＯ形成の際の拡散工程と同工程で
１〜１００−の厚さのｐ゛ ドレイン層１を形成する。FIG. 1 shows an embodiment of the present invention, and parts common to those in FIG. 2 are given the same reference numerals. In this case, an n-silicon substrate is used, and after forming 2 layers of n-buff on its - side, a layer of 1 to 100-m thick is formed in the same process as the diffusion process used to form pO on the other side. p゛ Drain layer 1 is formed.
別にｐ′シリコン基板１２を用意し、超音波加工で１０
０〜５００ ｐの径の穴１３を明ける０次にイオン注入
装置を用いて硼素を全面に打込み、ｐ゛ ドレイン層１
と同程度の不純物濃度にしたのち、表面を弗酸で軽くエ
ツチングする。これによって穴１３に傾斜がつく、この
穴明き基板１２の表面を研磨して滑らかな面にしたあと
、ドレイン層ｌの表面と接着する。接着には、例えば１
０′□’Ｐａの減圧下で５００〜８００℃に加熱し、２
００〜５００ Ｖ 、 ５００ｍ５のパルス電圧を印加
して行う静電接着法を通用した０次いで、ｐシリコン基
ｐのときオフ速度は従来のＩ ｕｓからｏ、７μｓに改
善され、特性のばらつきは±ｌＯ％程度であった。Separately, prepare a p′ silicon substrate 12 and use ultrasonic processing to
A hole 13 having a diameter of 0 to 500p is made, and boron is implanted into the entire surface using an ion implantation device to form a p'' drain layer 1.
After bringing the impurity concentration to the same level as above, the surface is lightly etched with hydrofluoric acid. As a result, the holes 13 are inclined. After the surface of the perforated substrate 12 is polished to a smooth surface, it is bonded to the surface of the drain layer l. For adhesion, for example, 1
Heating to 500-800℃ under reduced pressure of 0'□'Pa,
When the electrostatic adhesion method was applied by applying a pulse voltage of 00 to 500 V and 500 m5, the off-speed was improved from the conventional I us to 7 μs when the p silicon base was used, and the variation in characteristics was ± It was about 10%.
第３図は別の実施例で、第１図、第２図と共通の部分に
は同一の符号が付されている。この場合はｎ−シリコン
基板の一面側にはｎ°バ７ファ層２のみ形成し、ドレイ
ン層１を形成せず、穴明きｐ゛シリコン基板１２が直接
バッファ層２に接着されている０Ｍからなるドレイン電
極１１はｎ゛バフフ１層２上にも被着するが、その際界
面にｐ層が形成されるため、バッファ層２とドレイン電
極と短絡されることはない、この構造はドレイン層１の
形成は不要となるが、接着界面に生ずるｐ層とｎ゛バ、
ファ層との間の接合が不安定なため特性のばらつきは±
２０％程度に増大した。FIG. 3 shows another embodiment, in which parts common to FIGS. 1 and 2 are given the same reference numerals. In this case, only the n° buffer layer 2 is formed on one side of the n-silicon substrate, the drain layer 1 is not formed, and the perforated p-silicon substrate 12 is directly bonded to the buffer layer 2. The drain electrode 11 consisting of the Although the formation of layer 1 becomes unnecessary, the p layer and n layer formed at the adhesive interface,
Due to the instability of the bond with the fiber layer, the variation in characteristics is ±
It increased to about 20%.
本発明によれば、ドレイン層のソース電極に対向する部
分を薄くすることにより、ｎ形高抵抗層内に残る電子の
オフ時における引き抜き速度を高めることができ、その
結果オフ速度を向上させることができた。このような構
造は半導体基板と穴明き半導体基板の接着で容易に得ら
れ、高価なエピタキシャル半導体基板を用いる必要がな
いため、低コスト化の点でも可能である。According to the present invention, by thinning the portion of the drain layer that faces the source electrode, it is possible to increase the extraction speed of electrons remaining in the n-type high-resistance layer during the OFF state, and as a result, the OFF speed can be improved. was completed. Such a structure can be easily obtained by adhering a semiconductor substrate and a perforated semiconductor substrate, and there is no need to use an expensive epitaxial semiconductor substrate, so it is possible to reduce costs.
第１図は本発明の一実施例のＭＢＴの断面図、第２図は
従来のＭＢＴの断面図、第３図は本発明の別の実施例の
ＭＢＴの断面図である。
１：ｐ層 ドレイン層、２：ｎ゛バンフ１層、３：ｎ形
高抵抗層、４；ｐ形ベース層、５：ｎ。
ソース層、６：チャネル形成領域、７１．７２ ：絶
縁膜、８：ゲート電極、９：ソース電極、１１ニドレイ
ン電極、１２：ｐ層 シリコン基板、１３；穴。
０″”）ｄｔ４：”Ｑ ｏ Ｍ ｓ、。
第 １ 図FIG. 1 is a cross-sectional view of an MBT according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a conventional MBT, and FIG. 3 is a cross-sectional view of an MBT according to another embodiment of the present invention. 1: p layer drain layer, 2: n゛ banff 1 layer, 3: n type high resistance layer, 4: p type base layer, 5: n. Source layer, 6: Channel formation region, 71.72: Insulating film, 8: Gate electrode, 9: Source electrode, 11 Nidrain electrode, 12: P layer silicon substrate, 13: Hole. 0″”)dt4:”Q o M s,. Figure 1
Claims (1)
ース層を、さらにそのベース層の表面部に選択的にｎ形
の低抵抗ソース層を備え、高抵抗のｎ形層とソース層の
間にはさまれたベース層のチャネル形成領域表面上に絶
縁膜を介してゲート電極が設けられ、ソース層のチャネ
ル形成領域と反対側およびそれに隣接するベース層の表
面にソース電極が接触し、前記高抵抗のｎ形層の他側に
は低抵抗のｎ形バッファ層を介して低抵抗のｐ形ドレイ
ン層が設けられ、そのｐ形ドレイン層にドレイン電極が
接触するものにおいて、ｐ形ドレイン層はソース電極に
対向する領域が薄く、その周囲の領域が厚いことを特徴
とする絶縁ゲート型バイポーラトランジスタ。1) A p-type base layer is selectively provided on the surface of one side of the high-resistance n-type layer, and an n-type low-resistance source layer is selectively provided on the surface of the base layer. A gate electrode is provided on the surface of the channel formation region of the base layer sandwiched between the shape layer and the source layer via an insulating film, and a gate electrode is provided on the surface of the base layer opposite to and adjacent to the channel formation region of the source layer. A source electrode contacts the high-resistance n-type layer, and a low-resistance p-type drain layer is provided on the other side of the high-resistance n-type layer via a low-resistance n-type buffer layer, and the drain electrode contacts the p-type drain layer. An insulated gate bipolar transistor characterized in that the p-type drain layer is thin in the region facing the source electrode and thick in the surrounding region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31789288A JPH02163973A (en) | 1988-12-16 | 1988-12-16 | Insulated-gate type bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31789288A JPH02163973A (en) | 1988-12-16 | 1988-12-16 | Insulated-gate type bipolar transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02163973A true JPH02163973A (en) | 1990-06-25 |
Family
ID=18093218
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31789288A Pending JPH02163973A (en) | 1988-12-16 | 1988-12-16 | Insulated-gate type bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02163973A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0525587A1 (en) * | 1991-07-29 | 1993-02-03 | Siemens Aktiengesellschaft | Field effect controllable semi-conductor device |
| US5289019A (en) * | 1991-07-24 | 1994-02-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate bipolar transistor |
| JP2000040825A (en) * | 1998-06-30 | 2000-02-08 | Harris Corp | Semiconductor device having reduced effective resistivity of substrate and manufacture thereof |
| WO2014206189A1 (en) * | 2013-06-27 | 2014-12-31 | 无锡华润上华半导体有限公司 | Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor |
-
1988
- 1988-12-16 JP JP31789288A patent/JPH02163973A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5289019A (en) * | 1991-07-24 | 1994-02-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate bipolar transistor |
| EP0525587A1 (en) * | 1991-07-29 | 1993-02-03 | Siemens Aktiengesellschaft | Field effect controllable semi-conductor device |
| JP2000040825A (en) * | 1998-06-30 | 2000-02-08 | Harris Corp | Semiconductor device having reduced effective resistivity of substrate and manufacture thereof |
| WO2014206189A1 (en) * | 2013-06-27 | 2014-12-31 | 无锡华润上华半导体有限公司 | Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor |
| US10096699B2 (en) | 2013-06-27 | 2018-10-09 | Csmc Technologies Fab1 Co., Ltd. | Field-stop reverse conducting insulated gate bipolar transistor and manufacturing method therefor |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0671079B2 (en) | Bidirectionally conductive monolithic integrated semiconductor device and manufacturing method thereof | |
| JP2896141B2 (en) | High voltage semiconductor device | |
| JPH043981A (en) | Conductivity-modulation mosfet | |
| US4199860A (en) | Method of integrating semiconductor components | |
| JPH02163973A (en) | Insulated-gate type bipolar transistor | |
| JP2501810B2 (en) | Vertical MOSFET | |
| JP3249891B2 (en) | Semiconductor device and method of using the same | |
| JP2903749B2 (en) | Semiconductor device provided with conductivity-modulated MISFET | |
| JP3312691B2 (en) | Semiconductor device | |
| JPH0529628A (en) | Insulating-gate type bipolar transistor | |
| JPH05121425A (en) | Bipolar electrostatic-induction transistor | |
| JPS606104B2 (en) | MIS semiconductor device | |
| JP2808882B2 (en) | Insulated gate bipolar transistor | |
| JPS6276557A (en) | Insulated gate type self-turn-off element | |
| JPS6031267Y2 (en) | semiconductor switch | |
| JPS6381862A (en) | Insulated-gate bipolar transistor | |
| JPH0472669A (en) | Insulated-gate bipolar transistor | |
| JP2502696B2 (en) | Semiconductor integrated circuit device | |
| JPS6212665B2 (en) | ||
| JPH0582786A (en) | Mos-type transistor | |
| JPH06204463A (en) | Semiconductor device | |
| JPH02267969A (en) | Horizontal type conductivity modulation type mosfet | |
| JPH03218634A (en) | Semiconductor device and manufacture thereof | |
| JPH04144289A (en) | Insulated gate type bipolar transistor | |
| JP2001210838A (en) | Semiconductor device |