JPH02158988A - Signal recorder and signal reproducer - Google Patents

Abstract

PURPOSE:To reduce the error of editing by selecting a correct time code corresponding to position information. CONSTITUTION:A latch 2 outputs latched read time code data synchronously with a first frame reference signal. A phase counting part 3 outputs a first counted value and is reset by the first frame reference signal in every frame to start counting from 0. Delay parts 4 and 5 output first and second delay frame signals respectively, and delay times of delay parts 4 and 5 are so selected that they have not a great influence upon phase counting and are sufficiently longer than the delay of operation processing. They are operated, to latch the latch time code data just before and after the operation of a latch 9. The next frame is selected at the timing of approximate coincidence of switching between both frames by the select signal of a phase information comparing part 10 when recording phase information is smaller, but the preceding frame is selected when recording phase information is larger, thereby reducing erroneous editing.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention uses a signal recording means having a frame to record a time code with a frame period different from the signal recording means, and reproduces a signal having the same frame period as the signal recording means. For example, a rotary head type digital audio recorder (hereinafter referred to as R-
The present invention relates to a signal recording device and a signal reproducing device for recording and reproducing, for example, an SMPTE time code, which is a VTR time code, using a DAT (abbreviated as DAT) as a signal recording and signal reproducing means.

BACKGROUND OF THE INVENTION In recent years, in response to the increasing image quality of VTRs, there has been an increasing demand for audio tape recorders with higher sound quality. R-DAT is considered as a high-quality recording device to replace conventional analog recording, but the problem is synchronous recording and synchronous playback of video and audio.

Conventionally, when operating VTRs in synchronization, time codes were simultaneously recorded to specify absolute addresses on the tape, and during playback, the time codes of both VTRs were compared and the tape running of the VTRs was controlled so that the two matched. A method is being adopted. In order to do the same thing when the VTR and R-DAT operate in synchronization, it is necessary to record the same time code as the VTR's time code on the R-DAT.
VTR time code and VTR in the T subcode area
A signal recording and reproducing apparatus can be considered that records phase information between a frame and an R-DAT frame and synchronizes the two frames based on this time code and phase information during reproduction. For example, there is a rotary head type recording/reproducing device as disclosed in Japanese Patent Application Laid-Open No. 63-29391.

An example of a conventional signal recording/reproducing device will be described below.

FIG. 7 shows a block diagram of this conventional signal recording/reproducing apparatus.

In FIG. 7, reference numeral 41 denotes a signal recording/reproducing unit, such as the well-known R-
DAT, 42 is a time code reading section that reads, for example, an SMPTE time code, 43 is a phase measurement section, 44 is a time code generation section that generates, for example, an SMPTE time code, and 45 is a phase control section.

The operation of the signal recording and reproducing apparatus configured as described above will be explained below.

During recording, the time code reading section 42 reads an input time code having a first frame period, and outputs recording time code data and a first frame reference signal.

The phase measuring section 43 uses the first frame reference signal output from the time code reading section 42 and the signal recording/reproducing section 4.
The recording phase information is output from the second frame reference signal which is the first frame signal. A, B, C in Figure 8
, D, and E are diagrams explaining the operation, where A is the first frame, B is the first frame reference signal, C is the count of the counter of the phase difference measuring section, D is the second frame reference signal, and E is the second frame. As shown in FIG. 8, the counter in the phase measuring section 43 is reset at the falling edge of the first frame synchronization signal B and starts counting from 0, as shown in C. The counter value is read at the falling edge. In the example shown in this figure, 2 is output as the recording phase information. For the sake of explanation, this counter is a decimal counter that divides the first frame into 10 equal parts. The signal recording/reproducing section 41 samples and records recording time code data, recording phase information, and recording signals at a second frame period.

During reproduction, time code data, phase information, and reproduction signals are reproduced from the signal recording/reproducing section 41 and input to the time code generating section 44 and the phase controlling section 45 at a second frame period, respectively. The phase control section 45 performs an operation exactly opposite to that of the phase measurement section 43. That is, the reproduced phase information is sent to a counter whose maximum value is the first frame period in the second frame period, and the counter outputs a pulse when the maximum value reaches O from 9. In this way, the first frame reference signal is generated in the same phase state as the sentence recording time. The time code generating section 44 outputs a time code based on the time code data set in the second frame period from the signal recording/reproducing section 41 in synchronization with the first frame reference signal.

Problems to be Solved by the Invention However, in the above-described conventional configuration, the time code data and phase information are not correct at the timing when the first frame boundary and the second frame boundary almost coincide temporally. However, there have been problems in that the time code may not be compatible, and the time code may be recorded or played back incorrectly, resulting in the correct time code not being output. These timecode errors can cause errors during harmonization or editing.

Figure 9 is for explaining this, where F is the input time code during recording, G is the first frame reference signal during recording, and H is the second frame reference signal. Phase information as described in is measured. The time code data and phase information recorded in the signal recording and reproducing section are
J indicates the first frame reference signal generated by the phase control section based on the phase information output from the signal recording/reproducing section during reproduction, and K indicates the output time code output from the time code generation section. The number (3) indicates the time code sampled by the signal recording/reproducing section in the 1's digit, and the phase information measured by the phase measuring section below the decimal point. Point a in the figure indicates an example of an error at a timing where the first and second frame boundaries almost coincide in time.

Point a is the point where the input time code F changes from 1 to 2, and the time code data is sampled at 2 by the signal recording device, but the first frame reference signal G and the second frame reference signal H are different from each other. The output of the phase measuring section that measures the phase from 9 is 9, that is, 0. 9 is sampled. At this time, in this example, the time code data and phase information are recorded as 2.9, as shown in ■, where 1 should originally be sampled as time code data and 1.9. This occurs because the recorded time code data and the recorded phase difference information cannot be updated or sampled at exactly the same timing due to, for example, a delay in the output of the phase difference measuring section relative to the reset.

At point b, the time code data 6 output from the information reproducing device is set in the time code generator during the five output frames.

Immediately after that, the frame of the time code generation part is updated,
K because the timecode is incremented by one frame.
As shown in the figure, 7 is output as the output time code.

This means, for example, that the reproduced phase information is input to the phase control section and the
This occurs because the phases of the first frame during recording and the first frame during playback cannot be reproduced at completely the same timing due to factors such as a time delay before being reflected in the frame signal.

The present invention solves the above conventional problems, and when recording a time code with a frame period different from that of a signal recording device having a frame, the value of phase information recorded together with the time code is changed to the time code value. A signal recording device that can prevent time code data from being erroneously recorded by using it for determining validity, and a signal reproducing device that has a frame when reproducing time codes with a different cycle. The present invention provides a signal reproducing device that can prevent a time code from being output differently from when it was recorded by using the value of reproduced phase information to determine the validity of the time code value.

Means for Solving the Problems In order to eliminate errors in the correspondence between time codes and phases during recording, a first signal recording device of the present invention includes time code reading means for reading a time code having a first frame period; a first latch means for latching the read time code data obtained from this using a first frame reference signal and outputting first latched time code data;
a first phase counting means for counting the phase with respect to the first frame reference signal; a first delay means for delaying the second frame reference signal; and a first delay output from the first delay means. a second delay means for delaying the frame signal; a third delay means for delaying the second delayed frame signal output from the second delay means; and a first latch time code for the second frame reference signal. a second latch means for latching data; a third latch means for latching first latch time code data with a second delayed frame signal; and a first count value output from the first phase counting means. a fourth latch means for latching the first delayed frame signal with the first delayed frame signal and outputting recording phase information; a phase information determining means for outputting a select signal according to the value of the recording phase information; a time code selection means for selecting the second latch time code data and the third latch time code data output from the third latch using a select signal; and a third delayed frame signal output from the third delay means. a fifth latch means for latching the selected time code and outputting the recording time code data; and a signal recording means for recording the recording time code data, the recording phase information, and the recording signal in a second frame period. There is.

Similarly, a second signal recording device of the present invention includes a time code reading unit that reads a time code having a first frame period, and a time code reading unit that delays the first frame reference signal and outputs a fourth delayed frame signal. 4 delay means, 6th latch means for latching the time code data obtained from this by the 4th delayed frame signal, 2nd phase counting means for counting the phase with reference to the 1st frame reference signal, A seventh latch means that latches the second count value output from the second phase counting means with the second frame reference signal and outputs recording phase information, and compares the second count value and the recording phase information. a first phase information comparison means that outputs a first gate signal; a fifth delay means that delays a second frame reference signal; and a first phase information comparison means that delays a second frame reference signal; latch control means;
an eighth latch means for latching fourth latch time code data obtained from the sixth latch means with a first latch signal output from the first latch control means and outputting recording time code data; It has signal recording means for recording code data, recording phase information, and recording signals in a second frame period.

Furthermore, in order to eliminate errors in time code output during playback, the third signal reproducing device of the present invention stores time code data and recording phase information on a signal recording medium together with the recording signal in advance using the second frame reference signal as a reference. Record it.

a signal reproducing means for reproducing time code data, reproduction phase information, and reproduction signals from the signal recording medium; a phase control means for outputting a synchronization control signal from the reproduction phase information and the second frame reference signal; and a phase control means. synchronization signal generation means for outputting a first frame reference signal and a third count value based on the synchronization control signal output from the synchronization signal generation section; and reproduction phase information and a third count value output from the synchronization signal generation section. and a second phase information comparison means that outputs a second gate signal for opening the gate when the difference is within a certain value; a second latch control means for opening and closing the second frame reference signal and outputting a second latch signal;
a ninth latch means that latches the reproduced time code data reproduced from the signal recording medium by the latch signal and outputs the fifth latch time code data; and a first frame reference signal output from the synchronization signal generator. Fifth
a tenth latch means for latching the latch time code data of and outputting the sixth latch time code data; and time code generating means for generating an output time code in synchronization with the time code.

Operation The first signal recording device of the present invention has the above-described configuration, and when recording a time code and phase information having a frame period of if on a signal recording device having a second frame period, the latched phase information is By selecting either the time code data immediately before or immediately after latching the phase information depending on the value and passing it to the signal recording section, errors during time code recording can be eliminated.

Further, the second signal recording device of the present invention has the above-described configuration, and when recording a time code and phase information having a first frame period on a signal recording device having a second frame period, the latched phase information It is determined whether the input frame has changed by comparing the value of the phase counter with the value of the phase counter immediately after that, and depending on the result, either the time code data at the time of comparison or the time code data of the previous frame is selected. By passing this information to the signal recording section, errors in time code recording can be eliminated.

Further, the signal reproducing device according to claim 3 of the present invention has the above-described configuration, and when outputting a time code having the first frame period from the signal reproducing device having the second frame period, By comparing the value of the phase information to be reproduced and the phase state of the frame currently being output, and invalidating time code data that has reproduction phase information inconsistent with the phase information being output, Errors in can be removed.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 shows a block diagram of a signal recording device in a first embodiment of the present invention. In FIG. 1, 1 is a time code reading section that reads, for example, an SMPTE time code, 2 is a first latch, 3 is a first phase counter,
4 is a first delay section, 5 is a second delay section, 6 is a third delay section, 7 is a second latch, 8 is a third latch, 9 is a fourth latch, 10 is a phase information determination 11 is a time code selection section, 12 is a fifth latch, and 13 is a signal recording section having a second frame period, such as R-DAT.

The operation of the signal recording device configured as described above will be explained below. In the time code reading section 1, the first
The first latch 2 latches the read time code data and outputs the first latch time code data in synchronization with the first frame reference signal. do. The first phase counting section 3 is composed of, for example, a decimal counter, and outputs a first count value from 0 to 9 so as to divide the first frame period into 10 equal parts. Then, each frame is reset by the first frame reference signal and starts counting from 0. The first delay section 4 delays the second frame reference signal for a certain period of time and outputs a first delayed frame signal, and the second delay section 5 further delays the first delayed frame signal for a certain period of time and outputs a second delayed frame signal. Outputs a delayed frame signal. The delay times of the first delay section 4 and the second delay section 5 are used to generate pulses for latching the first latch time code data immediately before and after the recording phase information is latched. A time such as 1/10 of the count period of the counting section 3 is selected so as not to have much influence on the phase count and yet to be large enough to avoid delays in processing due to the operation of each section.

The second latch 7 and the third latch 8 function to latch the first latch time code data immediately before and after the operation of the fourth latch 9, which latches phase information, respectively. . When the value of the recording phase information latched at the temporal center is a large value, for example from 5 to 9, the first phase information comparator 10 outputs a logic value "L" as a select signal.
”, and when the value is small, for example from 0 to 4, the logical value IHI is output as a select signal.Time code selection section 1
1 selects the third latch time code data when the select signal is 'H', and selects the second latch time code data when the select signal is 'H'.
When the recording phase information has a small value, the next frame is selected, and when the recording phase information has a large value, the previous frame is selected at a timing such that the switching of the second frame and the second frame almost coincides with each other. Correct correspondence between phase information and time code data can be obtained.

The third delay unit 6 delays the second delayed frame signal by the time necessary for processing the third latch to ensure that the data in the third latch can be latched in the fifth latch. The fifth latch 12 latches the selected time code data with the third delayed frame signal from the third delay unit 6,
Output recording time code data. The signal recording unit 13 records recording time code data, recording phase information, and recording signals in a second frame period.

FIG. 4 is a timing chart for explaining this operation.

L is the first latch time code data, M is the first frame reference signal, and N is the first count value output from the first phase counting section 3, which is shown in a stepwise manner with a vertical line and above it. The numerical value indicates the recording phase information latched by the fourth latch 9. U is the second frame reference signal of the signal recording section, P is the second latch time code data, Q is the third latch time code data, and R is the time code data and recording phase information recorded in the signal recording section 13. and the fifth
The recording time code supplied from the latch 12 and the recording phase information of the fourth latch 9 are shown in the ones place and below the decimal point, respectively.

Point C and point d in the figure indicate an example at a timing where the transition between the first and second frames almost coincides in time. At point 0, 1 and 2 are latched as time codes as shown in P and Q, respectively, but 0 is latched as recording phase information, so the select signal is "H".
Then, the third latch time code data Q is selected as the selected time code. Therefore, as shown in R in the signal recording section, 2. Recorded as 0.

Similarly, at point d, time code data 5 and 6 are latched as shown by P and Q, respectively, but at the point where the fourth latch 9 that latches the phase information operates,
The count value changes from 9 to O, and at this time the select signal becomes 'L' and 5 of the second latch time code data is selected as the selected time code. Therefore, it is recorded as 5.9 in the signal recording section 13. In this way, time code data and phase information can be correctly correlated in both cases of point C and point d.

As described above, according to this embodiment, the appropriate one of the two time code data latched immediately before and immediately after latching the phase information is selected depending on the value of the latched recording phase information. By preventing the time code data from being passed to the signal recording section, it is possible to record correctly corresponding time code and phase information.

FIG. 2 shows a block diagram of a signal recording device in a second embodiment of the invention. In FIG. 2, 21 is a time code reading section for reading, for example, an SMPTE time hood, 22 is a fourth delay section, 23 is a sixth latch section, 24 is a second phase counting section, and 25 is a seventh latch section. ,
26 is a first phase information comparison section, 27 is a fifth delay section, 2
8 is a first latch control section, 29 is an eighth latch section, 30
is a signal recording section having a second frame period shorter than the first frame period, such as R-DAT.

The operation of the signal recording device configured as described above will be explained below. Time code reading section 21, second
The operation of the phase counting section 24 is the same as that of the time code reading section 1 and the first phase counting section 3 of the first embodiment. In the fourth delay section 22, in order to ensure the eighth latch operation, the fourth delay section 22 waits for a time necessary for processing the second phase counting section 24 and the seventh latch 25, and for a time sufficiently smaller than the fifth delay section. The first frame reference signal is delayed and output as a fourth delayed frame signal. The sixth latch 23 latches the read time code data in synchronization with the fourth delayed frame signal and outputs the fourth latched time code data. The seventh latch 25 latches the second count value output from the second phase counting section 24 in response to the second frame reference signal of the signal recording section 30, and outputs it as recording phase information.

The first phase information comparator 26 compares this recorded phase information with the second
A logic value "H" is output as a gate signal only when the count value of and the count value match or are close to each other, for example, when the difference is 1.

, the fifth delay unit 27 uses the second frame reference signal to change the frame of the first frame reference signal and the frame of the first count value, that is, the first count value changes from 9 to O. The signal is input to the first latch control unit with a sufficiently large time delay relative to the time difference from the time point. The first latch control unit 28 outputs the first latch signal only when the gate control signal is “H” and the fifth delayed frame signal is input.The eighth latch 29 outputs the first latch signal In other words, only when the phase information consistently corresponds to the time code, the fourth latch time code data from the first latch 23 is relatched and output as recording time code data.Signal recording section Reference numeral 30 records recording time code data, recording phase information, and recording signals in a second frame period.

FIG. 5 is a timing chart for explaining this operation.

S is the fourth latch time code data output from the sixth latch, T is the fourth delayed frame signal, and U is the second count value output from the second phase counter. Recording phase information latched by the seventh latch, ■ is the second frame reference signal, W is the fifth delayed frame signal,
X indicates the recording time code data output from the eighth latch, and Y indicates the time code and phase information recorded in the signal recording section in the ones place and below the decimal point, respectively.

Points e and f in the figure indicate an example where the transition between the first and second frames almost coincides in time. At point e, after the recording phase information is latched as 0 by the seventh latch, the count value remains 0 even at the falling edge of the delayed frame reference signal W, so the first latch signal is 'H'. Recording time code data X of the eighth latch has been updated to 2. At point f, after the recording phase information is 9 and latched by the seventh latch, the count value has already become 0 at the falling edge of the delayed frame reference signal W, and the first latch signal is l L l. The time code data of the third latch is not updated and remains at 5 of the previous frame.

In this way, time code data and phase information can be correctly correlated at both points e and f.

As described above, according to this embodiment, by comparing the latched recording phase information and the count value of the phase counter at the time of time code latch, it is determined whether or not the frame has changed during this time, and the time code data is By controlling the latch, if the frame has changed, the time code data of the previous frame is passed to the signal recording section, and if the frame has not changed, the current time code data is passed to the signal recording section. Phase information can be recorded.

FIG. 3 is a block diagram of a signal reproducing device showing one embodiment of the present invention. In the figure, 31 is a signal reproducing unit having a second frame period shorter than the first frame period, such as R-DAT, 32 is a phase control unit, 33 is a synchronization signal generation unit, and 34 is a second phase The information comparison section 35 is a second latch control section, 36 is a ninth latch, 37 is a tenth latch, and 38 is a time code generation section that generates a time code such as SMPTE.

The operation of the signal reproducing device configured as described above will be explained below.

It is assumed that second time code data and phase information are previously recorded on the signal recording medium together with the recording signal using the second frame reference signal as a reference. The signal reproducing unit 31 having a first frame period outputs time code data, reproduction phase information, and a reproduction signal from this signal recording medium at a second frame period. The phase control unit 32 is composed of a decimal counter having a maximum value of 9, for example.
Reproduction phase information is set in synchronization with the second frame reference signal of the signal reproduction section 31. Then, when the value of the counter becomes 0 from the maximum value 9, a synchronization control signal is output. The synchronization signal generation section 33 is composed of, for example, a phase control loop (PLL), and generates a stable first frame reference signal while matching the phase with the synchronization control signal from the phase control section 32. At the same time, the counter forming the PLL outputs count values O to 9 synchronized with the first reference signal.

The second phase information comparing section 34 compares the reproduced phase information from the signal reproducing section 31 and the third count value of the synchronizing signal generating section 33, and only when the values match or are close to each other, for example, the difference between the values is 1, A logical value I Hl is output as a gate control signal of 2. This second gate signal is for validating the reproduced time code data only when there is no contradiction between the reproduced phase information and the frame of the output time code currently being output. The latch control unit 35 receives the second gate control signal “
When the first frame reference signal is input during the H' period, the second latch signal is output. The ninth latch 36 latches the reproduced time code data according to this second latch signal. If the latch signal is not input, that is, if the time code is determined to be invalid, the correct time code can be passed to the tenth latch 37 by holding the time code data of the previous frame as is. 10th
The latch 37 latches the fifth latch time code data output from the ninth latch in accordance with the first frame reference signal and outputs it to the time code generator 38. The time code generator 38 outputs a time code obtained by adding 1 to this time code data.

FIG. 6 is a timing chart for explaining the operation. A is an example of an input time code having the first frame period during recording, and A is an example of the reproduced time code data and reproduction phase information output from the signal reproducing unit during playback when the time code shown in A is recorded. C is the second frame reference signal, 2 is the third count value output from the synchronization signal generator, E is the 5th latch time code data, 3 is the first frame reference signal, G is the 7th latch Time code data, H indicates the output time code.

The point g in the figure indicates an example at a timing where the transition between the first and second frames almost coincides in time. At point g, although the reproduced phase information is O as shown at the top, the third count value of the synchronization signal generator at the falling edge of the second frame reference signal C is 9. , the second gate signal becomes l L +, and no latch signal is output to the ninth latch. Therefore, the fifth latch time code data remains 1, and the tenth latch latches 1 instead of 2 as time code data, as shown in FIG. This data is incremented by 1 and a correct output time code is obtained as shown in FIG. At point h, since the reproduced phase information is O and the count value is also O, a latch signal is output to the ninth latch as shown in E. However, as shown in FIG. 7, the time code data 5 has already been latched in the tenth latch, and the correct output time code is still output.

As described above, according to this embodiment, the time code data is changed based on the difference between the reproduction phase information output from the signal reproduction section and the count value output from the synchronization signal generation section, which is the phase information of the time code being output. By controlling the latch,
Correct timecode can be output by validating only timecode data that has phase information that matches the phase state of the frame being output and preventing inappropriate timecode data from being passed to the timecode generator. .

Note that the configuration of each of the above embodiments may be partially or entirely realized by software using a microprocessor. Further, the first frame-based signal in the first and second embodiments may be configured to be extracted from the input time code by a time code reading section.

Effects of the Invention The present invention provides a method for recording and reproducing a time code having a first frame period in a signal recording and reproducing device having a second frame period, by determining the phase according to the value of the phase information measured by the phase measuring means. By selecting the correct time code that corresponds to the information, errors in the correspondence between time code data and phase information during time code recording and playback can be eliminated, thereby eliminating errors during time code recording and playback. Errors during phase modulation or editing can be reduced by using the time code.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a signal recording device in a first embodiment of the present invention, FIG. 2 is a block diagram of a signal recording device in a second embodiment, and FIG. 3 is a signal reproduction device in an embodiment of the present invention. A block diagram of the device, FIG. 4 is a timing chart showing the operation of the first embodiment, FIG. 5 is a timing chart showing the operation of the second embodiment, and FIG. 6 is a timing chart showing the operation of the signal reproducing device. , FIG. 7 is a block diagram of a conventional signal recording and reproducing device, FIG. 8 is a timing chart showing the operation of the phase measuring section, and FIG. 9 is a timing chart during recording and reproducing in the conventional example. 1.21... Time code reading section, 2... First
latch, 3...first phase counting section, 4...first delay section, 5...second delay section, 6...third
Delay unit, 7... Second latch, 8... Third latch, 9... Fourth latch, 10... Phase information determination unit, 11... Time code selection unit, 1
2...Fifth latch, 13.30...Signal recording section having a second frame period, 22...Fourth delay section, 23...Sixth latch section, 24... 2nd phase counting section, 25...7th latch section, 26... 1st phase information comparison section, 27... 5th delay section,
28... First latch control section, 29... Eighth latch section, 31... Signal reproducing section having a second frame period, 32... Phase control section, 33... Synchronization signal Generation unit, 34... second phase information comparison unit,
35... Second latch control section, 36... Ninth latch, 37...]O latch, 38... Time code generation section. Name of agent: Patent attorney Shigetaka Awano and one other person)
Drop − υ 0 ri ← Ko 〉 ′3

Claims (3)

[Claims] (1) A time code reading means that reads an input time code having a first frame period and outputs read time code data; and a first latched time code that latches the read time code data with a first frame reference signal. a first latch means for outputting data; a first phase counting means for counting the phase with respect to the first frame reference signal and outputting a first count value; and a first latch means for delaying the second frame reference signal. a first delay means for outputting a first delayed frame signal; a second delay means for delaying the first delayed frame signal and outputting a second delayed frame signal; a third delay means for delaying and outputting a third delayed frame signal;
a second latch means for latching first latch time code data using the second frame reference signal and outputting second latch time code data; and a second latch means for latching first latch time code data using the second frame reference signal and outputting second latch time code data; third latch means for latching data and outputting third latched time code data; and latching and recording the first count value output from the first phase counting means with the first delayed frame signal. a fourth latch means for outputting phase information; a phase information determination means for outputting a selection signal according to the value of the recording phase information; and a fourth latch means for selecting the second latch time code data and the third latch time code data. a time code selection means that selects based on a signal and outputs selected time code data; a fifth latch means that latches the selected time code data with the third delayed frame signal and outputs recording time code data; The code data, the recording phase information, and the recording signal are stored in a second
A signal recording device comprising a signal recording means for recording on a recording medium at a frame period of . (2) a time code reading means for reading an input time code having a first frame period and outputting read time code data; and a fourth time code reading means for delaying the first frame reference signal and outputting a fourth delayed frame signal. a delay means; a sixth latch means for latching the read time code data with a fourth delayed frame signal and outputting fourth latched time code data; and counting a phase with respect to the first frame reference signal. a second phase counting means for outputting a second count value; a seventh latch means for latching the second count value with a second frame reference signal and outputting recording phase information; a first phase information comparing means that compares the value with the recording phase information and outputs a first gate signal; and a fifth delay that delays the second frame reference signal and outputs a fifth delayed frame signal. means, first latch control means for opening and closing the fifth delayed frame signal according to the first gate signal and outputting a first latch signal; Eighth latch means for latching by a signal and outputting recording time code data; and signal recording means for recording the recording time code data, the recording phase information, and the recording signal on a recording medium in a second frame period. A signal recording device characterized by: (3) a signal reproducing means for reproducing the reproduced time code data, the reproduced phase information, and the reproduced signal from the signal recording medium in a second frame period; and a second signal output from the signal reproducing means;
phase control means for outputting a synchronization control signal from the reproduced phase information using the frame reference signal as a reference; and synchronization signal generation means for outputting a first frame reference signal and a third count value using the synchronization control signal as a reference. and a second phase information comparing means for comparing the reproduced phase information and the third count value and outputting a second gate signal, and opening and closing a second frame reference signal by the second gate signal. a second latch control means for outputting a second latch signal using the second latch signal; a ninth latch means for latching the reproduced time code data using the second latch signal and outputting fifth latch time code data; The fifth latch time code data is latched by the first frame reference signal, and the sixth latch time code data is latched by the first frame reference signal.
and a time code generating means for generating an output time code synchronized with the first frame reference signal from the sixth latch time code data. Characteristic signal reproducing device.