JPS62139192A - Time code generator - Google Patents

Abstract

PURPOSE:To output time codes corresponding to frame addresses of both video signals in a state that they are coincided with time at the time of a reproduction by controlling the output timing of a time code data outputted from a time code generator with a timing signal. CONSTITUTION:In a digital recording, a phase shift is generated between the reproduction time of a recording video signal and that of the time code data, and the frame number and the time of a reproducing video signal is not coincided with a reproducing picture, therefore, a control command to delay the output phase of the time code data for a prescribed time is inputted from an input device 41 to a CPU 40. A timing signal B at the output out terminal in a programmable counter 30 goes to a signal delaying by a delay time (tau) from the leading edge t0 of a frame pulse A. A time code generator 13 is controlled so as to set the leading edge t1 of the timing signal B as the read start time of the time code data, and a time code data TC is outputted in order at every frame from the time t1. In such a way, the phases of the recording signal and the time code is easily made coincide.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides a time code generator that generates a time code to be recorded on a magnetic tape in order to facilitate editing of a recording magnetic tape in a magnetic recording/reproducing device. It is related to.

[Summary of the invention]

In a magnetic recording and reproducing device configured such that a time code is recorded in the longitudinal direction of a magnetic tape in synchronization with a recording signal when recording a video signal, the start phase of the time code data is variable depending on the recording method. It can be so. Therefore, even when the recording method is, for example, digital recording, it is possible to output a time code that temporally matches the video signal output during playback.

[Conventional technology]

In devices for recording and playing video signals (VTR), for example, in high-end models equipped with editing functions, the time code of the recorded video signal, that is, the video frame number, the recording time of the video frame, etc. It is designed so that it can be recorded on magnetic tape at the same time as the signal.

Such a VTR with a built-in time code generator can identify each video frame by time code when re-editing recorded images, so it is indispensable especially for offline editing, automatic editing, etc. The recording format has also been standardized (SMPTE time code, EBU time code).

[Problem that the invention seeks to solve]

By the way, in the case of analog recording where the recorded video signal is directly supplied to the rotary head of the VTR, the clock of the data generation circuit of the time code generator is formed by a synchronization signal (frame pulse) separated from the video signal during recording. As shown in the recording format of FIG. 3, if the time code data is sequentially recorded in the track B formed in the longitudinal direction of the track zone A of the rotary recording head, the video signal of the recording track can be and the time code match and are read out.

However, a VT system that first converts the recorded video signal into a digital signal and then records the digital signal
In R, for example, as shown in FIG. 4, the signal to be recorded is converted into a digital signal in the A/D converter 1, and written in the timing conversion memory in the digital signal processing circuit 2, and is stored in the horizontal and vertical blanking periods. In addition to forming insertion periods for shift, parity, block synchronization, and block numbers, it also performs signal processing such as converting the signal period to match head scanning and adding parity and synchronization patterns for error detection and correction. It will be done. The data is then recorded on the tape T via the recording amplifier 3 as shown in FIG. Therefore, the recording signal of zone A is at least a recording signal that lags considerably behind the recording track B of time code data, which is operated by the synchronization signal of the recording video signal.

Therefore, when considering signal processing during playback, the digital video signal recorded in zone A of the recording track and the time code recorded in track B have a considerably different phase compared to the case of analog signals. There is a problem in that the reproduced video signal and the time code indicating its frame address do not match in time.

In order to solve this problem, this invention is a time code that delays the recording start time of the time code by a predetermined period of time, especially in the case of a digital recording method, so that the video signal and the time code coincide in time during playback. A generator is provided.

[Means for solving problems]

The time code generator of the present invention is provided with a circuit that shifts the phase of the frame pulse extracted from the recording signal by a desired amount of time in response to a control signal input to the CPU of the VTR. Configure the time code generator to control the data output custard time.

[Effect]

This is because the frame pulse extracted from the recording signal is delayed by a predetermined time to form the readout clock signal of the time code generator, and the recording signal is recorded at a delayed position on the magnetic tape due to digital signal processing, etc. It also becomes possible to supply a time code corresponding to the recording position. Therefore, during playback, the video signal and the time code corresponding to the frame address of the video signal can be output in a temporally matched state, allowing accurate editing work to be performed.

〔Example〕

FIG. 1 shows the main parts of the timing code generation device of the present invention, where 10 is a time code generation circuit formed of an IC circuit, etc., and 20 is a time code generation circuit for forming a timing signal for reading time code data. PLL circuit, 3
0 indicates a programmable counter, which allows a predetermined time delay at the pulse edge, similar to a monostable multivibrator. Reference numeral 40 denotes a control unit (CPU) serving as a system controller of the VTR, which sets various operation modes of the VTR according to operation signals from an input device 41, and in the case of the present invention, inputs the above-mentioned time code phase control command, etc. It is something that can be done.

As shown in the figure, the time code generation circuit 10 has a frame pulse generator 11 to which a recording signal synchronization signal (vertical) VD is input, a frequency dividing circuit (1/320) 12,
and a time code generator 13 from which time code data consisting of a predetermined number of bits is read out by the rising edge of this frequency dividing circuit 12, and as described above, this time code generator 13 generates a time code (recorded in the longitudinal direction of the tape). LTC) and time code as output within the vertical blanking period (V ITC)
etc. can be output in accordance with the NTSC system, PAL system, SECAM system, film frame mode, etc.

The operation of the above-described time code generator will be explained below with reference to the waveform diagram of FIG.

First, when a control command to set the output phase of time code data to O is input from the input device 41, the control data no-D7 of the programmable counter 30 is, for example, O, and the frame pulse generator 11 outputs a synchronizing signal. A frame pulse A is formed by VD and supplied to the programmable counter 30. The programmable counter 30 is counting the clock fcLK, but since the control data from the CPU 40 is O, the timing signal of the output OUT is the rising point t of the frame pulse A.

A signal synchronized with is obtained and input as is to the phase detector 22 of the PLL circuit 20.

Then, the voltage variable oscillator 21 (hereinafter referred to as V
CO) oscillates at 9.8 KHz, for example.
An output that is phase-synchronized with a signal (30 Hz) obtained by multiplying this output signal by 17320 degrees is input to the time code generator 13.

Therefore, the time code data output from the time code generator 13 is output with a phase that matches the synchronization signal VD, and is recorded on the tracks in the longitudinal direction of the tape.

However, in the case of digital recording as described above, when such time code data is output, a phase shift occurs between the playback time of the recorded video signal and the time code data, and the frame number of the playback video signal, The time does not match the playback screen.

Therefore, in such a case, from the input device 41 to the CPU 4
A control command is input to delay the output phase of time code data by a predetermined time with respect to 0.

In this case, since the delay data no-07 is supplied to the programmable counter 30 via the CPU bus, the timing signal at the output terminal of the programmable counter 30 is a frame pulse A as shown in waveform B in FIG.
The rising point t.

The signal will be delayed only by the delay time.

Therefore, the output phase of the VCO 21 also changes, and the frequency-divided output phase supplied from the frequency divider circuit 12 also changes. Then, the time code generator 13 is controlled so that the rising point t1 of the timing signal B is the time code data reading start time, and the time code data TC is sequentially output for each frame from this time t1. .

The setting of the delay time τ can be arbitrarily varied depending on the recording method. For example, if the frequency of the clock fcL is set to fc[=1 frame (30Hz) x 216=i=
When set to 2 MHz, it can be set by τ = 1/fCLK can be set.

The SMPTE standard time code consists of 80 bits, as shown in TC in Figure 2, and consists of frame codes XI,
XIO, time code S, l03 (seconds) M, MIO (minutes)
, H, l0H (time) and user code Ul, U2
．． U3. . . . , etc. are provided, and in the user code, the month/day 1 program code, reel number 2 quality control data, etc. can be entered for signal management.

Therefore, time code delay information can also be input into this user code.

〔Effect of the invention〕

As explained above, the time code generation device of the present invention is configured such that a PLL circuit, a programmable counter, etc. are added to the conventional time code generation circuit, and the phase of the frame pulse is controlled by the CPU. Therefore, it is possible to easily match the phases of the recording signal and the time code. Furthermore, since the amount of time code delay can be finely controlled by CPU control instructions, there is an advantage that it can be easily applied to various types of digital VTRs.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an outline of the time code generating device of the present invention, and FIG. 2 shows the amount of delay and time code. FIG. 4 shows an explanatory diagram of digital recording. In the figure, IO is a time code generation circuit, 11 is a frame pulse generator, 12 is a frequency dividing circuit, 13 is a time code generator, 2o is a PLL circuit, 30 is a programmable counter, and 4o is a CPU (control unit). Digida l's head's house's kidnapping II picture 4

Claims (1)

[Claims] In a magnetic recording/reproducing device that is capable of recording a time code corresponding to each frame of the video signal in the longitudinal direction of the tape when recording a video signal, frame pulses are extracted from the video signal to which the time code is added. After phase-controlling the frame pulse by a CPU, the frame pulse is input as phase information to a clock signal generation circuit that forms a timing signal, and the output timing of time code data output from a time code generator is controlled by the timing signal. A time code generator characterized by: