JP3446259B2 - Reference timing signal generation circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a rotary head type recording device such as a digital video tape recorder (hereinafter referred to as a digital VTR), and more particularly to a circuit for generating a reference timing signal which defines an after-recording area and the like.

[0002]

2. Description of the Related Art A digital VTR has been proposed which records digital video signals, digital audio signals and subcodes on a helical track of a magnetic tape in a time division manner. When post-recording a digital video signal, digital audio signal or sub-code recorded in this way, the post-recording area, that is, the area to be rewritten, must correspond exactly to the area already recorded on the tape, that is, the post-recording area is defined. It is necessary to.

In order to define the post-recording area, it has been considered to use a tracking pilot signal recorded at the head entrance side of the track. That is, since the recording position of the pilot signal is fixed, the recording area of the digital audio signal, for example, can be discriminated by measuring the timing based on the reproduced pilot signal, and a new digital audio signal can be recorded here. it can. It is also possible to define the post-recording area by measuring the timing based on the switching pulse of the rotary head.

[0004]

However, the conventional post-recording area defining method using the pilot signal has a problem that the accuracy of defining the post-recording area is low because the frequency of the pilot signal is as low as several hundred kHz. It was Further, the method of defining the after-recording area using the switching pulse of the rotary head has a problem that the prescribed after-recording area also shifts when the timing of the switching pulse shifts due to the jitter.

The present invention has been made to solve such a problem, and an object of the present invention is to provide a circuit for generating a reference timing signal capable of highly accurately defining a post-recording area and the like.

Another object of the present invention is to provide a circuit which can generate a reference timing signal even if there is an error in reproduced data.

[0007]

In order to solve the above-mentioned problems, the invention according to claim 1 is recorded at a predetermined position of a recording track, and each block has a synchronization pattern and a plurality of identical bits. In a circuit that generates a reference timing signal from data for timing definition, which is composed of a predetermined number of blocks each having a block number,
The first circuit for detecting the synchronization pattern, the second circuit for detecting the coincidence of a plurality of the same bits in the block number, the first circuit and the second circuit are n (where n is 2
And a third circuit for generating a first reference timing signal indicating the timing of a predetermined block when the detection signal is output consecutively (the above integer) times.

According to a second aspect of the present invention, in the first aspect of the invention, the timing of a predetermined block is calculated based on the detection signals of the first circuit and the second circuit, whereby the predetermined block is calculated. Is further provided with a fourth circuit for generating a second reference timing signal indicating the timing of.

The invention according to claim 3 provides the invention according to claim 1.
Or the invention according to 2, wherein a counter for counting the timing of the switching signal of the head for reproducing the recording track is used as a reference, and the count value of the counter counts the previous first reference timing signal or the second reference timing signal. It is further characterized by further comprising a fifth circuit for generating the third reference timing signal when the value reaches the above value.

[0010]

According to the first aspect of the invention, when the first circuit and the second circuit output the detection signal n times (where n is an integer of 2 or more) consecutively, the first reference timing is obtained. A signal is generated.

According to the invention of claim 2, the first aspect is further provided.
A second reference timing signal is generated based on the detection signals of the circuit and the second circuit. The second reference timing signal is generated when the first circuit and the second circuit output the detection signal even once.

According to the third aspect of the invention, the third reference timing signal is further generated based on the output of the counter which counts with reference to the timing of the switching signal of the head for reproducing the recording track. The third reference timing signal is generated if the first or second reference timing signal was generated last time even if the first circuit and the second circuit did not output the detection signal even once.

[0013]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 7 is a block diagram showing the configuration of a rotary head type recording apparatus to which the present invention is applied. This rotary head type recording apparatus can record a digital video signal, a digital audio signal and a subcode in a predetermined track format on a magnetic tape. On the magnetic tape, a digital video signal for one frame is recorded as a plurality of (for example, 10 in the NTSC system) diagonal tracks together with a digital audio signal and a subcode.

In FIG. 7, the recording processing circuit 31 is supplied with digital video signals, digital audio signals and sub-codes from input terminals 32, 33 and 34, respectively. The digital video signal is compressed by DCT (discrete cosine transform) and variable length coding, and is further error correction coded. The digital audio signal and the subcode are error correction coded.

The recording processing circuit 31 generates data in which the above-mentioned digital data is arranged in one track according to a format to be described later, and the channel encoder 35 converts the data into recording code, and then the multiplexer 3
9 is supplied. A signal from the ITI generating circuit 36 is also supplied to the multiplexer 39. The recording processing circuit 31 and the multiplexer 39 are controlled by the control signal from the control signal generation circuit 37, and the arrangement of data and ITI on the track is controlled. The control signal generating circuit 37 is supplied with data from the system controller 38.

The output data of the multiplexer 39 is passed through the recording amplifiers 40A and 40B and the recording / reproducing changeover switch 4 is used.
It is supplied to the recording side terminals r of 1A and 41B. The recording / reproducing changeover switches 41A and 41B have a rotary head H.
A and HB are respectively connected, and the outputs of the recording amplifiers 40A and 40B are recorded as diagonal tracks on a magnetic tape (not shown) by this rotary head. A pair of rotary heads HA and HB having different azimuths are used. Specifically, it is two heads arranged on a rotary drum at intervals of 180 °, or a double azimuth head in which gaps having different azimuths are provided close to each other.

The reproduction signals from the rotary heads HA and HB are reproduced side terminals p of the recording / reproduction changeover switches 41A and 41B.
And to the channel decoder 43 via the reproduction amplifiers 42A and 42B. The recording code is decoded by the channel decoder 43, and its output is supplied to the TBC 44. The TBC 44 removes the fluctuation of the reproduction data on the time axis, and the output thereof is supplied to the reproduction processing circuit 45 and the ITI detection circuit 46.

The reproduction processing circuit 45 performs error correction of the digital video signal, decoding of compression coding, and error correction of the digital audio signal and subcode. Playback digital video signals, playback digital audio signals, and playback subcodes are obtained at the output terminals 48, 49, and 50 of the playback processing circuit 45, respectively.

The ITI detection circuit 46 detects the ITI in the reproduced signal.
To generate a reference timing signal for defining the positions of various data recorded on the tape. IT
The output signal of the I detection circuit 46 is supplied to the control signal generation circuit 37. A control signal for post-recording is generated from the control signal generation circuit 37 to the recording processing circuit 31 and the multiplexer 39. As a result, post-recording is performed on the predetermined recording area.

FIG. 8 is a format diagram showing an array of data recorded on one track of the rotary head type recording apparatus shown in FIG. In this figure, the left end of the track is the head entrance (rush) side, and the right side is the head exit (separation) side. Further, no data is recorded in the margin and IBG (inter block gap). In the amble areas (preamble or postamble) added to both ends of the data recording area, for example, a pulse signal having a frequency equal to the bit frequency of the data is recorded, and a PLL for bit clock extraction provided on the reproduction side is provided. Used for locking.

Amble-SSA at the left end of the track
An ITI area composed of TIA-amble is provided. A recording area for digital audio signals, a recording area for digital video signals, and a recording area for subcodes are provided in order from the ITI area in the head scanning direction. The number indicating the length of each area means the number of bits. The contents of these data recording areas can be rewritten by post-recording. The margin provided at the right end of the track is for dealing with jitter.

FIG. 9 shows the ITI format. Figure 9
As shown in (a), the ITI area is 1400.
Bit preamble, 1830 bit SSA (St
Art-Sync Block Area), 90-bit TIA (Track ID Area) and 280
It consists of a bit postamble.

Then, as shown in FIG. 9 (b), SSA and TIA have 3 bits each having 10 bits.
It is composed of block data in word units. Then, the first 10 bits of each block data have a predetermined synchronization pattern (ITI-SYNC), the next 10 bits have an upper ID (ID-U), and the last 10 bits have a lower ID (ID).
-L). This upper ID is composed of an 8-bit upper ID word (ID-WORD-U) and 2-bit upper dummy data (Dummy-U), and a lower ID is an 8-bit lower ID word (ID-WORD-U).
L) and 2-bit lower dummy data (Dummy-L)
It consists of

The contents of the high-order ID word and the low-order ID word differ between SSA and TIA. In SSA, as shown in FIG. 9C, the adjustment bit 2 bit and sync block number (0 to 60) are set. have. The adjustment bit is a bit for giving a tracking pilot signal component of a predetermined frequency to the recorded data. Also, the sync block number is composed of 6 bits, and for example, bits 5 to 3 are each twice in the upper ID word, and lower I
Bit 2 to bit 0 are recorded twice in the D word. The upper and lower dummy bits give the tracking pilot signal component to the recorded data, like the adjustment bits.

As shown in FIG. 9D, the upper ID and the lower ID in the TIA identify the adjustment bit 2 bits and the use of the recording device (eg, used as a digital VTR, used as a streamer, etc.). The application ID is 3 bits, the recording mode (SP / LP) is 1 bit, the pilot frame is 1 bit indicating the reference frame of the servo system, and the reserve is 1 bit. The adjustment bit has the same role as the adjustment bit in SSA. The 6-bit array excluding the adjustment bits is not limited to the array of FIG.
It is sufficient that the same bit is recorded twice each for the total of the upper ID word and the lower ID word.

As described above, since each sync block in the ITI area is recorded at a fixed position on the magnetic tape, the position where the 61st sync pattern of SSA, for example, is detected from the reproduced data is recorded on the track. By using it as a reference for defining the position, the position to be rewritten at the time of dubbing can be defined with high accuracy, and good dubbing can be performed.

FIG. 1 is a block diagram showing the configuration of a reference timing signal generation circuit according to the embodiment of the present invention, which corresponds to a part of the ITI detection circuit 46 in FIG. 2 to 4 are operation timing charts of the reference timing signal generation circuit according to the embodiment of the present invention. Below,
The configuration and operation of this embodiment will be described with reference to FIG.

After detecting the SSA synchronization pattern from the reproduced data, the sync block number detection circuit 1 performs an error check for each same bit of the sync block number recorded in the upper ID word and the lower ID word by 2 bits. Then, if the synchronization pattern and the sync block number are continuously detected by a predetermined number or more (details will be described later),
When the sync block number = 60 is detected, the reference timing pulse TP1 is generated. FIG. 2A shows that the sync block number is continuously detected from 0 to 60, and FIG. 2B shows the operation of generating the first reference timing pulse TP1 when the sync block number = 60 is detected. Is shown. The reference timing pulse TP1 is
The switch SW1 and the switch SW that are switched so as to select the output of the sync block number detection circuit 1.
Output through switch SW2 which is switched to select the output of 1. Thus, normally, the first reference timing pulse TP1 generated by the sync block number detection circuit 1 is output through the switches SW1 and SW2.

However, there are cases where the sync block number detection circuit 1 cannot generate the reference timing pulse TP1. Therefore, in this embodiment, the first interpolation circuit 2 is provided. Then, the sync block number detection circuit 1
When the sync pattern and sync block number are detected even once, the sync pattern detection pulse and sync block number are output to the first interpolation circuit 2. The first interpolation circuit 2 operates, for example, an internal flywheel counter based on the detected pulse and the sync block number,
The second reference timing pulse TP2 is generated at the time when the timing corresponding to the sync block number = 60 is counted. This reference timing pulse TP2 is generated by the sync block number detection circuit 1 as the reference timing pulse TP1.
, Is output through the switch SW1 that is switched to select the output of the first interpolation circuit 2 and the switch SW2 that is switched to select the output of the switch SW1. For example, as shown in FIG. 3A, when the sync block number is continuously detected from 0 to 56, but is not detected after 57, the sync block number detection circuit 1 is The reference timing pulse TP1 is not generated. At this time,
As shown in (b), the sync block number detection circuit 1 detects the first sync block number,
The flywheel counter is operated to generate the second reference timing pulse TP2 shown in FIG. Thus, if the sync block number detection circuit 1 detects the sync pattern and sync block number even once, the second reference timing pulse TP2 is generated.

However, when the sync block number detection circuit 1 cannot detect the sync pattern and sync block number even once, the reference timing pulse TP2
Is not generated. Therefore, in this embodiment, the second interpolation circuit 3 is further provided. The output of the switch SW1 is input to the second interpolation circuit 3. The second interpolation circuit 3 has a counter for counting the reference clock inside. Then, this counter is reset by the head switching pulse SWP to start counting, and is reset again by the next head switching pulse SWP to repeat the operation of starting counting. And switch S
The third reference timing is used when the count value at the time when the output of W1 is input to the second interpolation circuit 3 is latched and the count value that started counting from the next switching pulse SWP matches the previously latched count value. Pulse TP
3 is generated. This reference timing pulse TP3 is the second reference timing pulse TP3 when the first interpolation circuit 2 does not generate the second reference timing pulse TP2 (of course, the sync block number detection circuit 1 does not generate the first reference timing pulse TP1). The output of the interpolation circuit 3 is output through the switch SW2 that is switched to select the output. Figure 4 (a)
Indicates that the reference timing pulse TP1 or TP2 is generated after a predetermined time has elapsed from the head switching pulse SWP. Further, in FIG. 4B, the counter is reset by the head switching pulse SWP, the count value n at the timing of the reference timing pulse TP1 or TP2 is latched, and further reset by the next head switching pulse SWP. It shows how to start counting up. Then, FIG. 4C shows how the reference timing pulse TP3 is generated when the count value reaches the value n latched last time.

As described above, in the present embodiment, the sync block number detection circuit 1 generates the first reference timing pulse TP1 if the sync pattern and the sync block number are continuously detected for a predetermined number or more, and the sync block number detection circuit 1 continues for a predetermined number or more. However, if the synchronization pattern and the sync block number cannot be detected once, but the synchronization pattern and the sync block number can be detected once, the first interpolation circuit 2 outputs the second reference timing pulse T.
When P2 is generated and the sync pattern and the sync block number cannot be detected even once, the second interpolation circuit 3 generates the third reference timing pulse TP3.

Next, the detailed configuration and operation of the sync block number detection circuit will be described with reference to the block diagram shown in FIG. The input data is converted into parallel data in units of words (10 bits) by the serial / parallel conversion circuit 11, and the D-flip-flop circuit 1
Input to 2. Further, the parallel data in word units is input to the synchronization pattern detection circuit 14, and ITI-SYNC shown in FIG. 9B is detected. When the synchronization pattern detection circuit 14 detects the synchronization pattern, it outputs a detection signal to the bit-flywheel circuit 15. Bit-
The flywheel circuit 15 changes the cut-out phase of the parallel data input to the D-flip-flop circuit 12 in bit units when the state machine 22 is in the search mode, and a sync block that outputs a signal indicating that the sync pattern has been detected. Number check circuit 13, delay circuit 2
5 and the ITI flywheel circuit 26. Each state of the state machine 22 will be described later.

The sync block number check circuit 13
An error is detected by performing EX-OR for each identical bit recorded in the upper ID and the lower ID of FIG. 9B by 2 bits each. Then, a signal indicating the presence or absence of an error is output to the multiplexer 21. Further, the sync block number check circuit 13 outputs the input parallel data in word units to the adder circuit 16, the first comparison circuit 17, and the application ID check circuit 18.

When the state machine 22 is in the search mode, the adder circuit 16 adds 1 to the input parallel data and latches it in the sync block number latch circuit 19. When the state machine 12 is in a state other than the search mode, the adder circuit 6 adds 1 to the output of the sync block number latch circuit 19 every 3 words and latches it in the sync block number latch circuit 19. Therefore,
When in a state other than the search mode, the content of the sync block number latch circuit 19 is incremented by 1 every 3 words.

The first comparison circuit 17 compares the sync block number output from the sync block number check circuit 13 with the sync block number latched in the sync block number latch circuit 19 and multiplexes a signal indicating a match or a mismatch. It outputs to 21.

The output of the sync block number latch circuit 19 is output to the second comparison circuit 20 and the third comparison circuit 24. The second comparison circuit 20 determines whether or not the sync block number read from the sync block number latch circuit 19 is larger than 60, and outputs a signal corresponding to the result to the multiplexer 21.

The multiplexer 21 includes the second comparison circuit 2
0 detects that the sync block number is 60 or less, the sync block number check circuit 13 detects that there is no error, and the first comparison circuit 1
7 detects a match, the second comparison circuit 20 detects that the sync block number is 61 or more, and the sync block number check circuit 13 detects that there is no error. Sometimes the state machine 22
Outputs a high-level (= 1) signal to.

The output of the ITI flywheel circuit 26 and the output of the first counter 27 are also input to the state machine 22. The ITI flywheel circuit 26 is reset by the sync pattern detection signal output from the bit flywheel circuit 15 only when the state machine 22 is in the search mode, and thereafter outputs a pulse every three words.
The first counter 27 counts up the output pulse of the ITI flywheel circuit 26 when the state machine 22 is in the caution mode and outputs a high level (= 1) signal to the state machine 22 when the count pulse exceeds the predetermined value. To do.

The second counter 23 is the state machine 22.
Is in hold mode, ITI flywheel circuit 26
Output pulse is counted up, and when it exceeds a predetermined value, a control signal is output to the third comparison circuit 24.
The third comparison circuit 24 is a sync block number latch circuit 1
The sync block number read from 9 is 60,
A pulse (reference timing pulse TP1) is generated only when the control signal is output from the second counter 23.

The delay circuit 25 adjusts the timing of the sync pattern detection signal and outputs a pulse indicating the position of the sync pattern to the state machine 22. Further, the switching control signals of the switches SW1 and SW2 in FIG. 1 are created based on the outputs of the second counter 23, the sync number check circuit 13 and the like, for example.

As shown in FIG. 9, in the TIA sync block, since the same bit such as the application ID is recorded twice in the upper ID word and the lower ID word, the sync block number check circuit 13
Takes an EX-OR for each bit recorded by 2 bits, detects an error, and then the application ID check circuit 18 causes a 3-bit application ID.
Check. Here, the application ID is 0
Is set to 00 or 111, and application I
The D-check circuit 18 detects the application ID by the majority logic and determines the number of coincidences of the majority logic (2 or 3).
Is being output.

The state machine 22 has four states of search mode, verify mode, hold mode and caution mode. Basically, the search mode is set when the ITI portion is not reproduced, and the verify mode is entered when the sync pattern and sync block number are detected. Further, when continuity of the sync pattern and sync block number is detected, the mode shifts to the hold mode. When the reproduction of the ITI portion is completed and no sync pattern is detected, the caution mode is set, and when no sync pattern is detected, the search mode is set. When an error occurs in the hold mode, the transition to the caution mode occurs, but only when the error occurs several times in succession, the transition to the search mode occurs. The operation of the state machine 22 will be described below with reference to the flowchart of FIG.

First, the search mode is initially set.
In this search mode, if the sync pattern is detected by the sync pattern detection circuit 14 and the output level of the multiplexer 21 is 1, the verify mode is entered,
Otherwise, stay in search mode. As described above, the output level of the multiplexer 21 becomes 1 when the SSA data is input because the sync block number check circuit 13 has detected that there is no error and the first comparison circuit 17 Is detecting a match,
That is, this is a case where there is no error in the sync block numbers recorded in 2 bits each in the upper ID and the lower ID of the SSA, and a sync block number consecutive to the sync block number of the immediately preceding sync block is detected.

Also in the verify mode, if the same condition is satisfied, the mode transits to the hold mode, and if not satisfied, the verify mode remains. As described above, in order to transit to the halt mode, the sync block number must be error-free for two consecutive times and must be continuous with the previous sync block number. Then, in the hold mode, if the above conditions are satisfied, the hold mode remains,
If not satisfied, transition to caution mode. Therefore, the hold mode is the most stable state among the four modes.

In the caution mode, if the above condition is satisfied, transition to the hold mode is made. If not, the first mode is set.
See the output of counter 27 of. When the output level of the first counter 27 is 1, the search mode is entered,
Otherwise stay in caution mode.

Although the reference timing pulse is generated in the 60th sync block in the above embodiment, the reference timing pulse may be generated in sync blocks of other numbers.

[0047]

As described above in detail, the first aspect of the present invention is as follows.
According to the present invention, the reference tamming pulse is generated only when the synchronization pattern is detected n times in a row and there is no error in the block number. Therefore, the reference tamming pulse with high accuracy and reliability can be generated.

Further, according to the second aspect of the present invention, since the reference timing signal is generated even if the synchronization pattern is detected even once and there is no error in the block number, even if there is an error in the data, it is highly accurate. Of the reference timing pulse can be generated.

According to the third aspect of the invention, even if the synchronization pattern is not detected even once, the reference tamming signal is generated based on the previous reference timing pulse. Therefore, the data cannot be detected this time. Can also generate a reference timing pulse.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a reference timing signal generation circuit according to an embodiment of the present invention.

FIG. 2 is an operation timing chart of the sync block number detection circuit in FIG.

FIG. 3 is an operation timing chart of the first interpolation circuit in FIG.

FIG. 4 is an operation timing chart of the first interpolation circuit in FIG.

5 is a block diagram showing an example of a specific configuration of the sync block number detection circuit of FIG.

6 is an operation flowchart of the state machine in FIG.

FIG. 7 is a block diagram showing a configuration of a rotary head type recording apparatus to which the present invention is applied.

FIG. 8 is a rotary head type recording apparatus 1 shown in FIG.
It is a format diagram which shows the arrangement | sequence of the data recorded on a track.

FIG. 9 is a format diagram of ITI.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Sync block number detection circuit, 2 ... 1st interpolation circuit, 3 ... 2nd interpolation circuit, 14 ... Sync pattern detection circuit, 13 ... Sync block number check circuit, 24 ... 3rd comparison circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11B 20/10-20/16 351 G11B 27/00-27/34

Claims (3)

(57) [Claims] 1. A timing stipulating data which is recorded at a predetermined position of a recording track, and each block is composed of a predetermined number of blocks having a sync pattern and a block number having a plurality of the same bits. A circuit for generating a reference timing signal; (a) a first circuit for detecting the synchronization pattern; (b) a second circuit for detecting a match between a plurality of identical bits in the block number; ) The first circuit and the second circuit are n (where n
Is an integer of 2 or more), when the detection signal is output continuously,
A third circuit that generates a first reference timing signal indicating the timing of a predetermined block, the reference timing signal generation circuit. 2. A fourth reference timing signal which indicates the timing of a predetermined block by calculating the timing of the predetermined block based on the detection signals of the first circuit and the second circuit. The reference timing signal generation circuit according to claim 1, further comprising a circuit. 3. A counter for counting the timing of a switching signal of a head for reproducing a recording track as a reference, and the count value of the counter is a value obtained by counting the previous first reference timing signal or second reference timing signal. 5. A fifth circuit is further provided for generating a third reference timing signal when
Alternatively, the reference timing signal generation circuit described in 2.