JPH02158153A - Dielectric insulator isolation type semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To avoid the drop of the breakdown voltage of a high breakdown strength semiconductor element and the deterioration of the semiconductor element by disposing the high potential wirings of the high breakdown strength semiconductor element on a region except an isolated island formed with other high breakdown strength semiconductor element. CONSTITUTION:A dielectric insulator isolating island 5 is provided on a dielectric insulator isolating board 1, and P-N-P-N type thyristors 2a, 2n of high breakdown strength semiconductor elements as well as N-P-N type transistor 3 and P-N-P type transistor 4, etc., of low breakdown strength semiconductor element are formed on the insulator isolating island 5. The anode electrode 6a, cathode electrode 7a and gate electrode 8a of the thyristor 2a are connected to lead wirings 10c, 11c, etc. These lead wirings are not formed on the region of the insulator isolating island 5 formed with other thyristor, but formed on the region of the insulator isolating island 5 formed with the low breakdown strength semiconductor element. Reverse high voltages of negative voltage to anode side and positive voltage to cathode side are applied to the thyristor 2b, and a forward high voltage is applied to the thyristor 2a. Since the potential of the wirings 11c of the thyristor 2c is not applied on the region of the insulator isolating island 5, it does not affect the characteristics of the thyristor 2b.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dielectric isolation type semiconductor integrated circuit having a low breakdown voltage semiconductor element and a high breakdown voltage semiconductor element.

[Prior Art] FIG. 3 is a plan view showing an example of a conventional dielectric isolation type semiconductor integrated circuit, and FIG. 4 is a sectional view taken along the line IV--IV in FIG. 3.

A plurality of dielectric isolation islands 5 are partitioned on the dielectric isolation isolation substrate 1 by dielectric isolation isolation films 9 . This insulating isolation island 5 is provided with a PN, which is a high voltage semiconductor element.
PN type thyristors 2a and 2b, an NPN transistor 3 and a PNP) range metal 4, which are low voltage semiconductor elements, are formed.

In the thyristor 2b region, the region surrounded by the dielectric isolation film 9 is an N-semiconductor region, and on the surface of this N-semiconductor region, a pair of P- impurity diffusion regions 24 are separated from each other by an appropriate distance. They are selectively formed separately. In this one P- impurity diffusion region 24, there is an N+ impurity diffusion region 2.
Also, in the NPN) range meta 3 region, the inside of the dielectric insulating isolation film 9 is occupied by the N− semiconductor region, and the surface thereof has an N“ impurity diffusion region 26 and a P1 impurity diffusion region. A region 25 is selectively formed.In this P+ impurity diffusion region 25, an N+ impurity diffusion region 2 is formed.
6 is formed.

A surface insulating film 23 is formed on the substrate 1, and holes for contacts 27 are selectively formed on each impurity diffusion region 24, 25, 26 of the surface insulating film 23. The contact holes are filled with aluminum or the like, and are filled with anode electrodes 6a, 6b, cathode electrodes 7a, 7b, gate electrodes 8a, 8b, base electrode 13,
16, emitter electrode 14.17 and collector electrode 15,
It consists of 18.

A first layer wiring 19 is formed on the surface insulating film 23 in a predetermined pattern. The first layer wiring 19 includes an anode lead wiring 10b, a cathode lead wiring 11b, and the like. An interlayer insulating film 21 is formed on the first layer wiring 19 and the surface insulating film 23, and a second N wiring 20 is formed in a predetermined pattern on the glabella insulating film 21. As this second layer wiring 20, anode lead wiring 1
A final protective film 22 is formed on the second layer wiring 20 and the interlayer insulating film 21.

As mentioned above, the electrodes drawn out from each semiconductor element are connected to the first and second layer wiring 19 formed by a two-layer wiring process.
．． 20 is connected. And in this example,
Anode electrode 6a and cathode electrode 7 of thyristor 2a
The anode lead wire 10a and the cathode lead wire 11a, which are the wires a, are also formed above the dielectric isolation island 5 of the thyristor 2b.

In general, in conventional dielectric isolation type semiconductor integrated circuits, the wiring length is shortened to reduce wiring capacitance, and when the chip size is reduced, in order to avoid close contact with adjacent wiring, this example is used. Thus, wiring from a high voltage semiconductor element to another semiconductor element is also formed on another high voltage semiconductor element region.

[Problems to be Solved by the Invention] However, for example, the anode electrodes 6a, 6b and the cathode electrode 7a of the cyrisks 2a, 2b.

7b becomes a high potential state depending on the operating state of the element.

Therefore, in the conventional dielectric isolation type semiconductor integrated circuit described above, the dielectric isolation island 5 on which the high voltage semiconductor element is formed is affected by the potential of external elements other than the high voltage semiconductor element. This has the disadvantage that the breakdown voltage of this high voltage semiconductor element is reduced. Furthermore, since charge is accumulated at the boundary between the wiring and the dielectric isolation island, which is in a high potential state in the high-voltage semiconductor element, there is also the problem that the characteristics of the semiconductor element deteriorate due to the influence of this charge.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a dielectric isolation type semiconductor integrated circuit having excellent breakdown voltage characteristics and reliability by avoiding breakdown voltage of a high voltage semiconductor element and deterioration of characteristics of the semiconductor element.

[Means for Solving the Problems] A dielectric isolation isolation type semiconductor integrated circuit according to the present invention includes a plurality of dielectric isolation isolation islands formed on a dielectric isolation isolation substrate, and a plurality of dielectric isolation isolation islands formed within the dielectric isolation isolation islands. In a dielectric isolation type semiconductor integrated circuit having high-voltage and low-voltage semiconductor elements formed, the high-potential wiring of the high-voltage semiconductor element is placed in an area other than the isolated island where other high-voltage semiconductor elements are formed. It is characterized by being located.

[Function] In the present invention, the high-potential wiring of the high-voltage semiconductor element is arranged in a region excluding the isolation island where other high-voltage semiconductor elements are formed. As a result, no wiring with a high potential is formed on the high-voltage semiconductor element, so this high-voltage semiconductor element is not affected by the potential of the wiring of other high-voltage semiconductor elements, and the original electrical Characteristics can be maintained. Furthermore, it is possible to prevent charges accumulated in the wiring from affecting the semiconductor element.

[Example] Next, an example of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a plan view showing an embodiment of the present invention, and FIG. 2 is a sectional view taken along line 1--2 in FIG.

This embodiment differs from the conventional dielectric isolation type semiconductor integrated circuit in that the wiring structure of the high-voltage semiconductor element is different, and the other structures are basically the same as the conventional one. Components in FIG. 2 that are the same as those in FIGS. 3 and 4 are designated by the same reference numerals, and detailed explanation thereof will be omitted.

The dielectric isolation isolation substrate 1 is provided with a plurality of dielectric isolation islands 5 separated by a dielectric isolation isolation film 9, and each isolation island 5 has a PNPN which is a high voltage semiconductor element.
type thyristors 2a and 2b, and an NPN type transistor 3 and a PNP type transistor 4, which are low voltage semiconductor elements.
etc. are formed.

The first layer wiring 19 made of aluminum formed on the substrate 1 includes lead wirings 10b and l from the anode electrode 6b, cathode electrode 7b, and gate electrode 8b of the thyristor 2b.
There are lb, 12b, etc. In addition, the anode electrode 6a, cathode electrode fi7a, and gate electrode 8a of the thyristor 2a
are formed simultaneously with the first layer wiring 19. These electrodes 6a7a, 8a are connected to the anode lead wiring 10c and cathode lead wiring 11c, which are the second layer wiring 20c made of aluminum, through through-hole contacts (not shown) provided in the glabella insulating film 21. has been done. These lead wires 10c and 11C are not formed on the area of the isolation island 5 where other thyristors are formed, and are not formed on the isolation island 5 where the low breakdown voltage semiconductor element is formed.
It is formed on the area of

In the dielectric isolation type semiconductor integrated circuit of this embodiment having the above-described structure, a high voltage in the opposite direction is applied to the thyristor 2b with the anode side set to a negative potential and the cathode side set to a positive potential, and a high voltage is applied to the thyristor 2a. applies a high voltage in the forward direction. Even in this operating state, thyristor 2
The potentials of the anode lead wiring 10c and the cathode lead wiring 11c of a do not affect the characteristics of the thyristor 2b because these wirings lQc and llc are not on the insulation isolation island 5 region of the thyristor 2b.

Therefore, the breakdown voltage of the thyristor 2b is not affected by the operation of other semiconductor elements, and operates at the original breakdown voltage.

[Effects of the Invention] As explained above, according to the present invention, the high potential wiring of a high voltage semiconductor element is formed in a region excluding the area of other high voltage semiconductor elements, thereby preventing breakdown of the high voltage semiconductor element. It is possible to avoid deterioration of the characteristics of the semiconductor element due to voltage drop and the influence of charges accumulated in the high potential wiring. Thereby, it is possible to obtain a dielectric isolation type semiconductor integrated circuit with high reliability and high withstand voltage performance.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an embodiment of the present invention, FIG. 2 is a sectional view taken along the line ■-■ in FIG. 1, and FIG. 3 is a plan view showing an example of a conventional dielectric isolation type semiconductor integrated circuit. , Figure 4 is the third
It is a sectional view taken along the line IV-IV in the figure. 1; Dielectric insulation isolation substrate, 2a, 2b; Thyristor, 3
;NPN transistor, 4;PNP transistor, 5;
Dielectric insulation isolation island, 6a, 6b; anode electrode, 7a,
7b; cathode electrode, 8a.

Claims (1)

[Claims] (1) A dielectric isolation type semiconductor having a plurality of dielectric isolation islands formed on a dielectric isolation isolation substrate, and high and low breakdown voltage semiconductor elements formed in the dielectric isolation islands, respectively. 1. A dielectric isolation isolated semiconductor integrated circuit, characterized in that a high potential wiring of a high voltage semiconductor element is arranged in an area excluding an isolated island on which other high voltage semiconductor elements are formed.