JPH02158135A - Semiconductor element - Google Patents

Abstract

PURPOSE:To form a semiconductor element which has a buried epitaxial layer without crystal defect as an active layer, by making an insulator film be of a multilayer structure, and as for opening part, making the opening dimensions of an insulator film, the lowermost layer in contact with a semiconductor substrate, larger than those of the insulator film right above. CONSTITUTION:This has a semiconductor epitaxial layer 5, which is buried in an opening part 11 provided in an insulator film on an N-type silicon substrate 1 where an N-type buried layer 4 is formed, as an active layer. In such a semiconductor element, the insulator film constitutes double-layers structure which has a silicon thermal oxide layer 2 as a lower layer and a silicon nitride film 3 as an upper layer, and at the opening part 11 the silicon thermal oxide film 2 has a larger opening dimension by the amount of its film thickness then that of the silicon nitride film. For this reason, the crystal defect part 5a of a the epitaxial layer 5 is limited to the end of the enlarged opening part of the silicon thermal oxide film 2, and does not reach the vicinity of the opening part of the silicon nitride film 3. Accordingly, the actual active region of an element can be set avoiding this crystal defect part 5a, and the property of the element can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is utilized for producing buried crystals in openings of insulating films in semiconductor devices.

The present invention relates to a semiconductor device having an epitaxial layer selectively grown in an opening of an insulator layer as an active layer of the device.

〔overview〕

The present invention provides a semiconductor element having as an active layer a semiconductor epitaxial layer embedded in an opening provided in an insulator film on a semiconductor substrate, wherein the insulator film has a multilayer structure in which different insulator films are laminated. The opening is such that a lowermost insulating film in contact with the semiconductor substrate has a larger opening than at least an immediately above insulating film, thereby reducing crystal defects occurring in the semiconductor epitaxial layer;
This improves the characteristics of the element.

[Conventional technology]

Semiconductor devices using silicon crystals are required to be smaller and functional devices with higher processing speeds, as exemplified by the trend towards higher integration of memory devices. To this end, the elements required for semiconductor crystals are:
Not only must the crystal be of high quality with no crystal defects, but it must also satisfy the degree of freedom in functional design of various devices. For example, it is necessary to create a degree of freedom in design by achieving a wide range of physical property values such as resistivity and impurity concentration.

Moreover, the high integration of devices requires achieving this degree of freedom within a single area called a "chip," and simply using a single semiconductor crystal substrate material poses technical difficulties. be.

Epitaxial growth technology, in which a semiconductor crystal layer is further grown on a semiconductor crystal substrate, is used as a solution to this problem in terms of semiconductor device manufacturing technology. Furthermore, in order to integrate more independent unit functional elements in a smaller area, selective growth techniques are being considered in which crystals are grown to fill the openings of an insulator film on a semiconductor crystal substrate. This is dichlorosilane (S
iH2Cl2), hydrogen (H2) and hydrochloric acid (I(C1)
This method takes advantage of the fact that crystal growth occurs selectively only on the surface of a semiconductor crystal due to the nature of a gas phase chemical reaction using a mixed gas.

The details of this selective growth technique are disclosed by Borland et al. in a well-known document, Japanese Edition Solid State Technology, October 1985 issue, page 43.

[Problem that the invention seeks to solve]

However, in the conventional selective growth method described above, a single insulating film structure such as a thermal oxide film is used, so crystals tend to form at the initial stage of growth at the contact area between the semiconductor substrate surface and the insulating film. It had a tendency to induce defects and propagate throughout.

The situation will be explained using FIGS. 6(a) and 6(a).

FIG. 6(a) (right door) is a schematic cross-sectional view showing a conventional epitaxial layer forming process. The contact area between the insulating film and the surface of the semiconductor substrate has a unique shape in which different materials come into contact, so it tends to become a nucleus during crystal growth, as shown in Figure 6 (a). Thus, at the initial stage of crystal growth, separate crystal regions are formed at the opening end A of the silicon thermal oxide film 2 and the epitaxial layer 5 on the silicon substrate 1. This region contains significant crystal defects as shown in FIG. 6b), and as the epitaxial layer 5 grows, it extends to the surface to form crystal defects 5a.

Further, from the viewpoint of processing accuracy of the end portion of the insulating film, the roundness of the corner portion B as shown in FIG. 7 has a significant influence on crystal growth. This is because the growth rate of crystal growth differs depending on the crystal orientation, so the shape of the opening in the insulator film is also processed along the lower crystal orientation of the crystal structure of silicon, that is, almost at right angles. This is because it is necessary. As described in the above-mentioned literature, it has been shown that oriented the sidewall of the opening in the (100) direction is effective in controlling crystal defects. If the angle is arbitrary, crystal growth regions along some low-order crystal orientations such as (311) are generated and collide, resulting in crystal defects.

By the way, when a semiconductor device is actually manufactured within the limits of such crystal orientation, it is extremely difficult to control the processing accuracy of the opening shape of the insulating film. Although it is easy to match the orientation of the aperture to the pattern design, the current microfabrication dimensions of the actual aperture in semiconductor devices, such as in dynamic RAM, have already achieved a processing dimension of around 1 micron. However, regarding the local shape, for example, in the corner portion of a rectangle, it is not necessarily possible to reproduce the right angle exactly as in the mask original, and the mask has some kind of curvature. This phenomenon is limited not only by the performance of the exposure apparatus used, but also by the principle of diffraction caused by the use of a visible light wavelength region that is on the same level as the dimensions.

Another practical limitation is that, even if minute fluctuations and defects in patterns that occur accidentally are not at a fatal level in the conventional semiconductor device manufacturing process, in the selective growth process, crystals in the initial stage of growth are It has the aspect that it becomes the core of defects and causes the defect region to grow.

Furthermore, when using a silicon thermal oxide film as a single-layer insulator film, for example, the film is formed by high-temperature treatment at around 1000°C, then openings are processed around room temperature, and crystal growth is performed again at around 100°C. There is a problem caused by the material itself that large residual stress is generated between the grown epitaxial layer and the silicon thermal oxide film.

The purpose of the present invention is to solve the above-mentioned problems.
An object of the present invention is to provide a semiconductor device having a buried epitaxial layer free of crystal defects as an active layer.

[Means for solving problems]

The present invention provides a semiconductor element having as an active layer a semiconductor epitaxial layer embedded in an opening provided in an insulator film on a semiconductor substrate, wherein the insulator film has a multilayer structure in which different insulator films are laminated. , the opening is characterized in that the lowermost insulating film in contact with the semiconductor substrate has a larger opening size than at least the immediately above insulating film.

Further, in the insulating film having the multilayer structure, the present invention provides a method in which a dimensional difference between an opening dimension of the lowermost insulating film in contact with the semiconductor substrate and an opening dimension of the upper insulating film is smaller than that of the lowermost insulating film. It is preferable that the thickness be equal to or larger than the thickness of the insulating film.

Further, the present invention uses a thermal oxide film as the lowermost insulating film, uses a nitride film formed by a vapor phase chemical reaction method as the upper insulating film, and adjusts the film thickness ratio of the thermal oxide film to the nitride film. It is preferable to set the ratio in a range of 10:1 to 4:1.

[Effect]

In the present invention, an insulating film having a multilayer structure is used, and the opening dimensions of the upper layer and the lower layer are set to be different.

In other words, by setting the aperture size of the insulator film in the lowest layer at least larger than that of the insulator film immediately above, crystal defects will occur at the edges of the opening in the initial stage of crystal growth, but At the stage where the crystal has grown to the thickness of the film, in order to set the opening size as the region where the crystal should grow by reducing it by, for example, the thickness of the lowest layer insulator film, the edge of the opening containing the crystal defects is It is possible to confine the peripheral region within the upper layer insulator film region corresponding to the difference in opening size.

Furthermore, residual stress can be reduced by combining different materials for the multilayered insulator. For this purpose, a plurality of materials having different Young's modulus between the epitaxial layer and the Young's modulus of the epitaxial layer are combined, for example, a silicon thermal oxide film is used as the lower layer and a silicon nitride film is used as the upper layer, with a thickness ratio of 10:'. By setting the ratio in the range of 1 to 4:1, the Young's modulus can be approximated to that of the epitaxial layer, and the occurrence of crystal defects can be suppressed.

Therefore, by suppressing the occurrence of crystal defects in the epitaxial layer and setting the active region of the device in the region above the opening where crystal defects do not occur, it is possible to improve the characteristics of the device.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic vertical sectional view showing a first embodiment of the present invention.

The present embodiment is a semiconductor having as an active layer a semiconductor epitaxial layer 5 embedded in an opening 11 provided in an insulating film on an N-type silicon substrate 1 on which an N-type buried layer 4 is formed. In the device, the insulator film has a two-layer structure with a silicon thermal oxide film 2 as a lower layer and a silicon nitride film 3 as an upper layer.
has an opening size larger than that of the silicon nitride film by the thickness of the silicon nitride film.

Here, the thickness of the silicon thermal oxide film 2 and the silicon nitride film is, for example, the film thickness of the silicon thermal oxide film 2 d. , when the thickness of the silicon nitride film is d8, do = 1.5
um, dN = 0.2μ11, i.e. do : dN
=7.5:1, do:d, I=10:1 to 4:1.

Hey, in Figure 1, 6 is the base P-type head area, 7
is the N-type region which becomes the emitter, and 8.9 and 10
are electrodes made of aluminum that serve as an emitter electrode, a base electrode, and a collector electrode, respectively, and this semiconductor element constitutes a transistor. Moreover, 5a is a crystal defect portion generated at the end of the opening.

The feature of the present invention is that, in FIG. 1, silicon thermal oxide film 2 and silicon nitride film 3 having the above-mentioned dimensional relationship are provided.

According to this embodiment, the crystal defect portion 5 of the epitaxial layer 5
a is limited to the end of the enlarged opening of the silicon thermal oxide film 20 and does not extend to the vicinity of the opening of the silicon nitride film 3. Therefore, the actual active region of the device can be set so as to avoid this crystal defect portion 5a, and the characteristics of the device can be improved.

Next, the manufacturing method of this example will be explained.

FIGS. 2(a), 2(a) and 2(c) are schematic longitudinal cross-sectional views of the main manufacturing steps of this example.

As shown in FIG. 2(a), the entire surface of a (100)-oriented silicon substrate 1 having a highly concentrated N-type buried layer 4 is treated at 1000° C. in an oxidizing atmosphere containing water vapor.
A silicon thermal oxide film 2 with a thickness of 1.5 μm is formed. next,
A silicon nitride film 3 having a thickness of 0.2μ0 is formed using a chemical vapor deposition (CVD) method.

After that, as shown in FIG. 2 (5), an open pattern is formed by mask exposure using a photoresist (not shown),
Openings are formed in silicon nitride film 3 and silicon thermal oxide film 2 at the same time by dry etching. At this stage,
No difference in aperture size is required for the present invention. Further, when a diluted hydrofluoric acid aqueous solution is used, the silicon thermal oxide film 2 is almost selectively etched to the sides due to the difference in etching speed between the two films. This additional etching forms openings 11 with a difference in opening size of 1.5 μm. In this case, good controllability can be obtained by selecting the dilution concentration so that the etching rate is several hundred angstroms per minute.

Thereafter, as shown in FIG. 2(C), the N-type epitaxial layer 5 was heated with dichlorosilane (SiH2C1,), hydrochloric acid (HCI), and hydrogen (H2) gas at a flow rate of 0.5.
J/min, 21/min, 801/min, and phosphine (PH3) diluted with hydrogen (H2) as doping gas 0
．． It is formed by chemically reacting a 2 ppma concentration gas at a flow rate of 0.11/min at a temperature of 1000°C and a vacuum level of 50 Torr.

At this time, a crystal defect portion 5a is generated at the end of the opening, which is the contact portion between the silicon thermal oxide film 2 and the silicon substrate 1.
In the range of this crystal defect portion 5a, the crystal defect is (113)
4 due to the property that it tends to grow in low-order plane orientations such as orientation.
The difference falls within an angular direction larger than 5°, that is, within a range of an opening size difference equal to the thickness of the silicon thermal oxide film 2.

After the above N-type epitaxial layer 5 is formed, a P-type head region 6 is formed as a base region by boron (B) ion implantation, and then arsenic (A) is formed as an emitter region by ion implantation, and finally, , electrodes 8 of the semiconductor element which serve as an emitter electrode, a base electrode, and a collector electrode, respectively.
．． By opening holes 9 and 10 at predetermined positions using PR technology and dry etching technology, and forming aluminum by sputter deposition, the semiconductor element of this embodiment shown in FIG. 1 is obtained.

Regarding the electrical characteristics of the finally obtained semiconductor device,
When a reverse bias of 10 to 15 V is applied between the N-type epitaxial layer 5 and the P-type head region 6 of a semiconductor device formed using the conventional technology, the junction leakage current is approximately 10-'A/C (I+''). On the other hand, in this example, it was 10-8
It showed an extremely small value of ~10-'A/cm''. This means that in the conventional example, the crystal defects reached the PN junction near the surface, whereas in this example, the crystal defects reached the PN junction near the surface. It seems that containment is working.

Furthermore, it was measured by Raman spectroscopy that the residual stress value of the N-type epitaxial layer 5 changes when the film thickness ratio of the silicon nitride film 3 and the silicon thermal oxide film 2 is changed. The results are shown in FIG. In FIG. 3, the horizontal axis represents the film thickness ratio of the nitride film to the oxide film, and the vertical axis represents the compressive stress. For a rectangular epitaxial layer with device dimensions of 20 x 40 μm and a thermal oxide single layer of 1.7 μm thick, 4 x
Since a compressive stress of lQ-"dyn/cm2 is generated after the device is formed, dislocations occur from the edge of the opening. However, if the two-layer structure with the silicon nitride film 3 is used and the film thickness ratio is increased, the compressive stress will be reduced. It was found that it decreased significantly.

However, if the thickness of the silicon nitride film 3 is made too large, tensile stress will result, which is not effective, and there is an appropriate range. Based on the experimental results, the range was selected such that the film thickness ratio of the nitride film/thermal oxide film was 1/10 to 1/4.

The reason why the above relationship is established is that when a single layer of a silicon thermal oxide film or a silicon nitride film is formed on a silicon substrate, the direction of warpage is different between the two. It is thought that there is a series of Young's modulus. Therefore, by combining the two, they can be canceled out, which is why the effects of the second embodiment were obtained. Also,
Similar results were obtained regardless of the difference in aperture size.

FIG. 4 is a longitudinal sectional view showing the main parts of a second embodiment of the present invention.

The second embodiment has a three-layer structure in which a polycrystalline silicon layer is sandwiched between the silicon thermal oxide film 2 and the silicon nitride film 3 of the insulating film in the first embodiment shown in FIG. The opening size is the same as in the first embodiment, in which the opening size of the silicon thermal oxide film 2 is increased by the thickness of the silicon thermal oxide film 2. In FIG. 4, 13 and 14 are silicon thermal oxide films, and the other reference numbers are the same as in FIG. 1.

A feature of the present invention is that, in FIG. 4, an insulating film 3 is composed of a silicon thermal oxide film 2, a polycrystalline silicon layer 12, and a silicon nitride film 3 having the dimensions shown in the figure.
The reason is that it has a layered structure.

In the second embodiment, since the polycrystalline silicon layer 12 is not easily dissolved in the hydrofluoric acid aqueous solution, it is possible to form different opening sizes in the same manner as in the first embodiment.

Next, the manufacturing method of the second embodiment will be explained. Fifth
Figures (a), (a) and (c) are schematic longitudinal sectional views taken through the main manufacturing steps of the second embodiment.

As shown in FIG. 5(a), an N-type epitaxial layer 5 is formed in the opening 11 in the same manner as in the first embodiment except that the polycrystalline silicon layer 12 is deposited by the CVD method.
Embed and form.

Thereafter, as shown in FIG. 5(b), boron is ion-implanted into the N-type epitaxial layer 5 to form a P-type head region 6, and arsenic is further ion-implanted to form an N-type region 7.
form. Furthermore, an opening for a collector electrode passing through the polycrystalline silicon layer 12 and reaching the N-type epitaxial layer 5 is formed at a predetermined position in the silicon nitride film 3.

Thereafter, as shown in FIG. 5C, high temperature treatment is performed in an oxidizing atmosphere to form silicon thermal oxide films 13 and 14.

Finally, after forming an open pattern using a photoresist (not shown), openings are formed in the silicon nitride film 3 and silicon thermal oxide film 14 by dry etching, and the bottom portion of the silicon thermal oxide film 13 is removed. By forming electrodes 10.9 and 8 for the active layer, ie the N-type epitaxial layer 5, the P-type head region 6 and the N-type region 7, a second embodiment shown in FIG. 4 is obtained.

In removing the bottom portion of the silicon thermal oxide film 13, it is important to use a highly anisotropic dry etching method to suppress damage to the side oxide film.

The NPN transistor formed by the above manufacturing method also exhibited good reverse bias breakdown voltage characteristics as in the first example.

In the above embodiments, a transistor is used as a semiconductor element, but the present invention is similarly applied to other semiconductor elements such as a diode and a silice.

〔Effect of the invention〕

As explained above, the present invention confines crystal defects that occur at the ends of an epitaxial layer formed by selective epitaxial growth using a multilayer structure insulating film having different opening dimensions, and This makes it possible to prevent the leakage current from propagating, thereby reducing the leakage current that becomes particularly noticeable when the semiconductor element is reverse biased, and having the effect of obtaining good electrical characteristics.

Further, by forming a multilayer structure such as a nitride film or an oxide film, residual stress generated in the epitaxial layer can be controlled, crystal defects generated after epitaxial growth can be prevented, and good electrical characteristics can be ensured.

[Brief explanation of the drawing]

FIG. 1 is a schematic vertical sectional view showing a first embodiment of the present invention. FIGS. 2(a), 2(c), and 2(c) are schematic vertical cross-sectional views of the main manufacturing steps of the first embodiment. FIG. 3 is a characteristic diagram showing residual stress in the first example. FIG. 4 is a schematic vertical sectional view showing a second embodiment of the present invention. FIGS. 5(a), 5(a) and 5(c) are schematic longitudinal cross-sectional views of the main manufacturing steps of the second embodiment. FIGS. 6(a) and 6(b) are schematic vertical cross-sectional views showing the epitaxial layer forming process in a conventional example. FIG. 7 is a schematic cutaway perspective view showing the main parts of a conventional example. DESCRIPTION OF SYMBOLS 1... N-type silicon substrate, 2.13.14... Silicon thermal oxide film, 3... Silicon nitride film, 4... N-type buried layer, 5... N-type epitaxial layer, 5a.・・・
Crystal defect portion, 6... P type region, 7... N type region, 8
．． 9.10... Electrode, 11... Opening, 12...
Polycrystalline silicon layer. N-type silicon substrate 6 Silicon thermal rtL4 film 7 Zinocon nitride film 8,9.1O N-type buried sublayer 11 N-type epitaxial crystal defect akore: P-type arrester: N-type nitriding bag : Opening irises fan - Fukori・1 to 3 times Atsushi - example of writing (1 time 1 time)'! f: J 2 Figure 1: N-type silicon Jk 2: Silicon thermal oxide film 3: Silicon nitride layer 4: N-type bitaximal heat sa: t'6 crystal x IvI part 1+: ff mouth part 1: N-type silicon substrate 2, 13.14: Silicon black modified layer 3; Silicon nitride leg 4: N-type buried Δ1 5: N-type epitaxial layer 50: Tsume & rug area 6: To PJgi area 7: N To the mold 11: Opening 12 Rainbow Viscous Silicon I (Plant drawing) 5 Figure 1: N'ln Sofun Base 2: Silicon! ! A@4LifX 5: N type Evita no Shall layer 5a: 1f5. j% defective part 1: N-type Si 0-in Grave treatment 2: Silicon thermal @ oxide film 5: N-type Ehi 1 layer #East 4IA (English revised plan), Yl 6 Mouth (Shiba Nagata example) (-Diagram of encouragement) 'W: Diagram J-7

Claims (1)

[Scope of Claims] 1. A semiconductor element having as an active layer a semiconductor epitaxial layer embedded in an opening provided in an insulator film on a semiconductor substrate, wherein the insulator film is a stack of different insulator films. 1. A semiconductor element having a multilayer structure, wherein the opening has a lowermost insulating film in contact with the semiconductor substrate having a larger opening size than at least an immediately above insulating film.