JPH02155674A - Image data processor - Google Patents

Abstract

PURPOSE:To prevent gradation properties or resolution from being lowered at the time of conversion of image data and obtain image data with high quality by subjecting binary data to pulse width modulation according to the density of multi-valued image data. CONSTITUTION:Upper order two bits (VD7, VD6) of a multi-valued image signal inputted to a demultiplexer 12 are used as a selection signal 24 for the demultiplexer 12. That is, density data for 256 gradations is divided into 4 hierarchical levels each of which corresponds to 6 bits (64 gradations), before being inputted to dither processing circuits 15-18. In each of the circuits 15-18, 6-bit density data is compared with a 8X8 dither matrix, and 1-bit signals D1-D4 are outputted respectively from the dither processing circuits. The signals D1-D4 are outputted after being converted into pulse signals which are obtained by multiplying by different integral numbers a pulse width modulation (PWM) clock signal 26 (PCLK) obtained by halving the frequency of a master clock signal CLK. An output from a logical circuit 23 is used as a driving signal 27 (LD) for actually driving a laser.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image information processing device that converts a multivalued image signal into a binary image signal.

[Prior Art] Conventionally, methods of reproducing halftone images using a dither method or a density pattern method are known. These compare multi-valued image data with a threshold matrix and convert it into an on/off signal (2 positive signals) for a laser light source such as a laser beam printer. However, no matter which of the above-mentioned methods is used, sufficient gradation cannot be obtained by using a small-sized threshold matrix. Further, when a large-sized threshold matrix is used, the gradation is improved to some extent, but there is a problem in that the resolution of the image is extremely reduced.

On the other hand, apart from the above-mentioned method, a method has been proposed that can express gradation while maintaining high resolution with a relatively simple circuit configuration. The method is to convert digital multilevel image signals into two
When forming an image with a laser beam printer etc.,
In order to obtain halftone gradation, the input digital multivalued image signal is first converted to an analog signal, and this converted analog signal is compared with a periodic pattern signal such as a triangular wave to generate a pulse. This generates a binarized signal that is width modulated.

FIG. 8 is a block diagram showing an example of a circuit configuration for realizing this method.

In FIG. 8, an input digital multi-level image signal is latched by a latch circuit 101 in synchronization with a video clock 111. This video clock 111 is a clock obtained by dividing the frequency of the mask clock 112 into J- by two using the flip-flop 104. It is assumed that the master clock 112 is synchronized with the horizontal synchronization signal 113 in advance.

The digital image signal of the latch circuit 101 is sent to the D/A converter 1
02 is converted into an analog signal 115, and the comparator 1
It is input to the analog input terminal of 03.

On the other hand, the master clock 112 is frequency-divided into a predetermined period by a frequency divider 105 and a period switching signal, and further divided by two by a J- flip-flop 108, with a duty ratio of 50.
% clock signal 114. This clock signal 11
4 and the period of the video clock 111 is determined by the frequency divider 10.
This corresponds to a frequency division ratio of 5. Further, the frequency divider 105 is loaded with a frequency division ratio by the logical sum signal of the horizontal synchronization signal 113 described above and the ripple carry signal (RC○) of the frequency divider 105, so that the analog image signal 115 and the clock signal 114, each line is completely synchronized.

The clock signal 114 is input to the pulse pattern generator 110 through the buffer 109, where it is converted into a triangular wave pattern signal 116 and an analog image signal 115.
The dynamic range and matching are taken. The triangular wave pattern signal 116 output from the pulse pattern generator 110 is input to the other input terminal of the comparator 103, and the analog image signal 115 is input to the other input terminal of the comparator 103.
[Problems to be Solved by the Invention] However, in such a pulse width modulation method,
Due to factors such as the responsiveness of the laser driver and the particle size of the developer, there is a limit to the ability to separate one recorded dot into gradations.For example, it is difficult to record by inputting an 8-bit multilevel image signal. It could not be said that sufficient gradation was obtained.

The present invention has been made in view of the above-mentioned conventional example, and it converts multivalued image information into binary information, and also prevents the deterioration of gradation and resolution that accompanies the conversion of this image information. The present invention also aims to provide an image information processing device that can obtain high-quality image information.

[Means for Solving the Problems] In order to achieve the above object, an image information processing apparatus of the present invention has the following configuration. That is, a binarization means for binarizing multivalued image information, and a pulse width modulation means for pulse width modulating the information binarized by the binarization means in accordance with the density of the multivalued image information. and has.

According to another claim, the binarization means includes a dividing means for dividing the multivalued image information into a plurality of layers corresponding to the density of the image information, and a plurality of layers divided by the dividing means. [Operation] In the above configuration, multi-valued image information is input and binarized, It operates to pulse width modulate the binarized information in accordance with the density of the input multivalued image information.

Further, the multivalued image information is divided into a plurality of layers corresponding to the image density, and dither processing or error diffusion processing is performed for each layer to binarize the multivalued image information.

[Embodiments] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[Description of the image data conversion circuit (Fig. 1)] Fig. 1 is a block diagram showing the configuration of the image data conversion circuit of the embodiment.
This circuit shows the configuration of an image data conversion circuit provided in a laser beam printer.

In the figure, VDO to VD7 are 8-bit multivalued image signals input from an external device such as a host computer or an image scanner. This multi-value image signal is latched by the latch circuit 11 in synchronization with the image clock signal 25 (VCLK), and the image clock signal 25 and the multi-value image signal are synchronized. This image clock signal 25VCLK is
It is obtained by frequency-dividing the master clock signal CLK by 1/8 using the phase-locked 1/8 frequency divider circuit 13. This phase synchronization 1/8 frequency divider circuit divides the mask clock CLK by 1/8 in synchronization with the rising edge of the horizontal synchronization signal H3YNC sent from a controller (not shown) or a beam detector of a laser beam printer. There is.

12 is a demultiplexer that receives a 6-bit input signal (VD
O to VD5), and the 2-bit select signal 24 (VD
6. VDT) to one of the data buses DB1 to DB4, and outputs "0" to all output ports not selected by the select signal 24. Dither processing circuit 1
5 to 18 are each input data bus DBI to
Dither processing is performed based on the 6-bit image signal from the DB 4, and 1-bit output signals D1 to D4 are output, respectively. The pulse generation circuits 19 to 22 input the output signals (DI to D4) from the corresponding dither processing circuits, and generate pulse signals PWI to PW4 of a predetermined length through the signal windows, respectively.
Output. These pulse signals PW1 to PW4 are input to an OR circuit 23, and the OR output thereof is output as a laser drive signal 27 (LD) to turn on the laser of the image recording section.

Next, the operation of the circuit having the above configuration will be explained.

The 8-bit multilevel image signals VDO to VDT are synchronized with the image clock signal 25 (VCLK) by a latch circuit 11 and then input to a demultiplexer 12. The upper two bits (VDT, VD6) of this multivalued image signal are used as a select signal 24 of the demultiplexer 12. That is, ■D7. When VD6 is "1.1", the lower six bits (VDO to VD5) of the multivalued image signal are input to the dither processing circuit 15 via the data bus DBI.

Similarly, when VDT and VD6 are "1.0", the lower 6 bits (VDO-VD5) are sent to the dither processing circuit 16 via the data bus DB2, and when VD7 and VD6 are "0.1", (
7) When VDO-VD5 is input to the dither processing circuit 17 via the data bus DB3, when VDT and VD6 are "0.0", VDO to VD5 are input to the dither processing circuit 18 via the data bus DB4. .

In this way, for example, an 8-bit, 256-gradation multi-value image signal (density information) can be converted into a 6-bit (64-gradation) multi-value image signal (density information).
Each level is divided into four hierarchies, and input to dither processing circuits 15 to 18 in descending order of density. Each of the dither processing circuits 15 to 18 processes 6
A comparison is made between the bit density data and the 8x8 dither matrix. As a result, each signal D1~
D4 is output from each dither processing circuit.

Each of these 1-bit signals D1 to D4 is input to a corresponding pulse generation circuit. Pulse generation circuit 19
~22 is a pulse width modulated PWM) clock signal 26 (PC
LK) are converted into pulse signals of different integer multiple widths and output.

That is, for example, when the pulse generation circuit 19 receives Dl at a high level, it outputs a pulse signal PWI having a pulse width four times the period of PCLK. Similarly, when the pulse generation circuit 20 inputs D2 at a high level, it generates a signal PW2 having a pulse width three times the period of PCLK, and when the pulse generation circuit 21 inputs D3 at a high level, it generates a signal PW2 having a pulse width three times the period of PCLK.
When the pulse generating circuit 22 inputs the signal PW3 having a pulse width twice the period of PCLK and D4 at a high level, the pulse generating circuit 22 generates a signal PW4 having a pulse width equal to the period of PCLK.
are output to the OR circuit 23, respectively. The output of this OR circuit 23 becomes a drive signal 27 (LD) that actually drives the laser.

[Description of dither processing circuit (FIG. 2)] FIG. 2 is a block diagram showing the configuration of one of the dither processing circuits 15 to 18 of the embodiment, and the configurations of the other dither processing circuits are similar.

In FIG. 2, 31 is a ROM that stores dither matrices, etc., and the address input (AO-A
5) contains the lower 6 bits (VDO to VD5) of the multivalued image signal.
) is input through the data bus (DBn+n=1 to 4). 32 is a 3-bit up counter that is counted up by the image clock signal 25 (VCLK), and the counted value is sent to the address input (A6 to A6) of the ROM 31.
8) is entered. This counter 32 counts pixel positions in the main scanning direction, and is composed of 3 bits corresponding to an 8.times.8 dither matrix. 33 is also a 3-bit up counter, and horizontal synchronization signal H3Y
The count is counted up by the NC, counted in the sub-scanning direction, and the counted value is manually stored in the addresses A9 to A of the ROM 31.
I am inputting it to ll.

As a result, information obtained when the multilevel image signal input to address AONA5 is compared with the threshold values of the 8×8 dither matrix designated by addresses A6 to All is stored at that address. 36 is the result, ROM3
This shows 1 byte data output from 1, and the least significant bit of this 1 byte data contains laser on/off information (
Dn: n=1 to 4) is written.

Therefore, as described above, since this output 36 is the same value as the result of comparing the threshold value of the 8×8 dither matrix and the 6-bit multi-value image signal (density data), the 1 output from each dither processing circuit is Each of the bit data D1 to D4 is a binary signal obtained by dithering a 6-bit multivalued image signal.

Next, the pulse generation circuits 19 to 22 that generate laser drive signals based on dither-converted signals will be described.

[Description of Pulse Generating Circuit (FIG. 3)] FIG. 3 is a block diagram showing the configuration of the pulse generating circuit of the embodiment, and the other pulse generating circuits have almost the same configuration.

41 is a D type flip-flop, and when the 1 bit data Dn from the dither processing circuit is at a high level, VCL
In synchronization with the rise of K, the Q output 45 is set to high level. 43 is a 2-bit presetable up counter, which sets the 2-bit value set in the initial value setting section 42 by PCLK when the Q output 45 is at a low level, and counts up by PCLK 26 while the Q output is at a high level. ing. When the ripple carry (RC) output 44 of the counter 43 is output, the flip-flop 41 and the counter 43 are reset.

This 2-bit counter 42 is preloaded with 2-bit data from the initial value setting section 42 using PCLK when the Q output 45 is at a low level. Therefore, this initial value determines the time until the counter 42 resets the flip-flop 41, and thereby the Q output 45
The pulse width of (PWn) will be determined. As a result, as described above, for example, the value set in the initial value setting section 42 of the pulse generation circuit 19 is set to "O", the initial value set in the pulse generation circuit 20 is set to "1", and the value set in the pulse generation circuit 21 is set to "O". If the initial value set to the pulse generating circuit 22 is set to "2" and the initial value set to the pulse generating circuit 22 is set to "3", the PWI becomes P
PW2 is 4 times the width of the CLK period, PW2 is 3 times the width of the PCLK period, PW3 is 2 times the width of the PCLK period, PW4 is I P
The pulse width is the same as the CLK cycle.

As described above, the PWM clock signal 26 (PCLK), which is the counting clock of the counter 43, converts the master clock signal CLK into the phase interval wIl/in FIG.
This is a signal whose frequency is divided by 1/2 by the frequency divider circuit 14 in synchronization with the rising edge of the horizontal synchronizing signal H5YNC.

Therefore, this clock signal 26 (PCLK) is
Synchronized with image clock signal 25 (VCLK), VCL
This is a clock signal having a frequency four times that of K.

[Explanation of signal timing (Figures 1 to 5)]] 4th
is a diagram showing the pulse widths of PW1 to PW4 output from each pulse generation circuit, and as mentioned above, each PWI
is 4 times PW4, PW2 is 3 times PW4, PW3 is PW
It is twice as many as 4.

FIG. 5 is a diagram showing an example of an operation timing diagram of the image data conversion circuit of FIG. 1.

As shown in the figure, when the output D4 of the dither processing circuit 18 rises at timing T1 in synchronization with VCLK25, the next VC
Pulse generation circuit 2 at the rising edge of LK (timing T2)
PW4 is output from 2. As described above, this PW4 has a pulse width equivalent to one cycle of PCLK, and thereby the laser drive signal 27 (LD) is created to turn on the laser.

Similarly, when D2 rises at timing T2, the next VC
At the rising edge of LK, PW2 is output from the pulse generation circuit 20.
It is output with a pulse width three times the period of CLK.

Here, a high-speed ROM is used as the ROM 31, and the VCLK signal input to the pulse generation circuits 19 to 22 is set to be higher than the VCLK signal input to the dither processing circuits 15 to 18.
For example, by delaying several hundred seconds, the P W n signal for driving the laser can be output at almost the same timing as the Dn signal (n=1 to 4).

As explained above, according to this embodiment, high gradation can be obtained without increasing the size of the dither matrix, so a high-quality image with good gradation can be obtained without loss of resolution.

In the above embodiment, the PW flaw signal pulse width outputted by the pulse generation circuit is set to the period of PCLK or an integral multiple thereof, but it is not limited to this, and the pulse width may be given a γ characteristic. , it may be possible to output with various pulse widths so that the recording density becomes linear.

In addition, in the above-mentioned embodiment, in the case of dither processing in which 4-step pulse width modulation is performed on the upper 2 bits of an 8-bit multivalued image signal, and the lower 6 bits are binarized using an 8 x 8 dither matrix. However, it is not limited to this, for example, various combinations of pulse width modulation gradation selection and dither matrix selection are possible, and furthermore, these combinations can be made using dip switches or commands. It would be good if it could be switched.

[Other Embodiments (Fig. 6)] In the embodiments described above, the demultiplexer, dither processing circuit, and pulse generation circuit were each configured as separate circuits, but these functions can be implemented in one ROM. It is possible to realize this with FIG. 6 shows this.

FIG. 6 is a block diagram showing the configuration of an image data conversion circuit according to another embodiment, and parts common to those in FIG. 1 are designated by the same numbers. This circuit configuration is the dither processing circuit 15~
18 is that a PWM clock signal 26 (P
CLK), and the counter 72 is a 5-bit counter that is reset every 32 seconds. Next, the operation will be explained.

The latch circuit 11 causes the image clock signal 25 (VCL
8-bit image signal VDONvD synchronized with
7 is input to the ROM 71 (7) 7FL/S input AO-A7. Furthermore, the count value of the 5-bit counter 72 that counts in the main scanning direction using the PWM clock PCLK is transferred to the address buses A8 to A12 of the ROM 71, and the count value of the 3-bit counter 73 that counts in the sub-scanning direction based on the horizontal synchronization signal HSYNC. is ROM71
is input to address inputs A13 to A15.

In this way, laser on/off information is written in the least significant bit of the 1-byte data file 4 stored at the address specified by the 16-bit address (AONA15). Here, since the clock PCLK has a frequency four times that of VCLK, the upper 3 bits of the main scanning counter 72 and the full output of the sub-scanning counter 73 of VDO-VD 5.5 bits, which are the lower 6 bits of the image data. An 8×8 dither matrix is formed from the relationship between the three bits. In this way, the pixel determines whether the laser is turned on or off.

In this embodiment, data is written in each address of the ROM 71 so that the pulse width for turning on the laser can be determined based on the upper two bits of the multivalued image data.

FIG. 7 shows the upper two bits VD7. of the multivalued image data output from the latch circuit 11. VD6 and 5-bit counter 72
FIG. 2 is a diagram showing an example of ROM data showing the relationship between the lower two bits (QA, Q,) of the signal and the modulated 1-bit signal (D).

According to this, VD6. When both VD7 are “1”,
Since D=1 when QA and Q are between "Oo" and "11", D is output at a high level during four clock cycles of PCLK. Further, when VD6 and VD7 are "0.1", D becomes high level for three cycles of PCLK. Similarly, when VD6 and VD7 are “1.0”, D is PC
2 cycles of LK, VD6. When VDT is "0.0" (7), D is at a high level for one cycle of PCLK.

In this way, similarly to the embodiment described above, laser driving can be performed with four types of pulse widths depending on the value of the upper two bits of the image signal. Note that the table shown in FIG. 8 is just an example, and it goes without saying that the table is not limited to this.

Note that in the two embodiments described above, an example was explained in which the dither method was applied as a means of binarizing multivalued data, but the method is not limited to this, and an error diffusion method or a density pattern method may also be used. In this case, in the error diffusion method, the laser may be turned on at a plurality of layers at the same time among the layers divided into a plurality of layers based on density data within the same dot. In this case, for example, if a signal that lights up with pulse width 1 (PW4) and a signal that lights up with pulse width 3 (PW2) are on, drive with pulse width 4 (PWI), which is the logical sum of these signals. The signal may be used to drive the laser.

As explained above, according to the present embodiment, there is provided a binarization circuit that binarizes a multi-value image signal using a dither method, etc., and a pulse width of the binarized signal based on the density of the multi-value image signal. By performing recording based on the converted image signal in combination with a pulse width modulation circuit for conversion, it is possible to obtain a high-quality image with good gradation and resolution.

[Effects of the Invention] As explained above, according to the present invention, multilevel image information can be
In addition to converting the image information into value information, it is possible to prevent the gradation and resolution from decreasing due to the conversion of the image information, thereby obtaining good and high-quality image information.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the schematic configuration of the image data conversion circuit of the first embodiment, FIG. 2 is a block diagram showing the configuration of the dither processing circuit of the embodiment, and FIG. 3 is a block diagram of the pulse generation circuit of the embodiment. A block diagram showing the configuration, FIG. 4 is a diagram showing an example of a pulse width modulated signal, FIG. 5 is a diagram showing the operation timing of the image data conversion circuit of FIG. 1, and FIG. 6 is a diagram showing image data of another embodiment. FIG. 7 is a block diagram showing the configuration of a conversion circuit, FIG. 7 is a diagram showing an example of ROM data, and FIG. 8 is a block diagram showing the configuration of a conventional pulse width modulation circuit. In the figure, 11... Latch circuit, 12... Demultiplexer, 13... 1/8 frequency divider circuit, 14... 1/2 frequency divider circuit, 15-18... Dither processing circuit, 19 ~22
...Pulse generation circuit, 23...OR circuit, 24.
...Select signal, 25...VCLK, 26...P
WM clock PCLK, 27...Laser drive signal, 3
1...ROM, 32.33...Counter, 41...
・Flip-flop, 42...Initial value setting section, 43・
...Counter, 1 ...ROM. 72°73... It is a counter. Figure 7

Claims (2)

[Claims] (1) Binarization means for binarizing multivalued image information;
An image information processing apparatus comprising: pulse width modulation means for pulse width modulating the information binarized by the value conversion means in accordance with the density of the multivalued image information. (2) The binarizing means includes a dividing means for dividing the multivalued image information into a plurality of layers corresponding to the density of the image information, and a dithering process or an error for each of the layers divided by the dividing means. Diffusion processing is performed, and 2
2. The image information processing apparatus according to claim 1, further comprising a binarization conversion means for obtaining a digitized signal.