JPH02151175A - Picture signal thinning-out circuit for facsimile equipment - Google Patents

Abstract

PURPOSE:To apply the reduction processing of an original size immediately without the need for the processing by a software by counting a picture clock signal repetitively, generating an interleave signal at a prescribed count so as to apply interleaving, using the result as a clock signal and repeating the latch of a serial picture signal. CONSTITUTION:A binary counter(CUT) 1 counts a clock signal(VCLK) b, interleave signal generating circuits(TOS) 5-7 generate an interleave signal every time a count output (e) reaches a prescribed level decided for each output. Then the TOS 5 is used to reduce an original size B4 to A4, a TOS 6 is used to reduce the A3 size into A4 size and a TOS 7 is used to reduce the size A3 into the size B4 similarly seductively. Moreover, the clock VCLKa is inverted by an inverter 8 as an inverse of VCLKc to be given to a clock terminal CK of a D flip-flop(FFC) 9, a carry output (a) of the CUT 1 is given to a data terminal D of the FFC 9, and the CUT 1 counts the clock VCLKb in a range of '5'-'F' repetitively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit for thinning out images 1N when reducing the document size in a facsimile machine.

[Conventional technology]

In facsimile machines, when reducing the document size, serial image signals from an image sensor are thinned out. Conventionally, software is used to operate a processor to count image clock signals and It is common practice to thin out image signals based on .

[Problem to be solved by the invention]

However, with conventional methods, everything depends on software, resulting in an increased number of program steps, extended processing time, and a lack of responsiveness.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention is configured by the following means.

That is, in the facsimile device described above, there is a counter that repeatedly counts the image clock signal, a thinning signal generation circuit that generates a thinning signal when the count output of this counter is in a predetermined order, and a thinning signal generating circuit that generates a thinning signal when the count output of this counter is in a predetermined order, and a thinning signal generating circuit that generates a thinning signal when the count output of this counter is in a predetermined order. It is equipped with a gate circuit that performs thinning, and a latch circuit that repeatedly holds a serial image signal using the output of this gate circuit as a clock signal.

[Effect]

Therefore, the output of the gate circuit is a thinned-out image clock signal for each predetermined order, and the latch circuit repeatedly holds the image signal based on the thinned-out clock signal. An image signal thinned out at predetermined intervals is obtained.

〔Example〕

Hereinafter, the present invention will be explained in detail with reference to figures showing examples.

FIG. 1 is a block diagram, and FIGS. 2 (,) to (,) are timing charts showing waveforms of each part in FIG.
In Figure 1, a binary counter (hereinafter referred to as CUT) 1
counts the image signal (hereinafter referred to as VCLK) (b) and sends out a count output (,) of the output terminal QA"QoYoshi2 evolution, and this count output (,) is output from the inverter 2. , exclusive OR (hereinafter referred to as EXOR) gate 3
, and a decimation signal generating circuit (hereinafter referred to as rO8) 5 consisting of an AND gate 4, and a similar r
The signal is also given to the TOs 086 and 07, and each TO 85 to T generates a thinning signal every time the count output (,) reaches a predetermined rank determined for each one.

In addition, rO85 converts the original size 84 version to A4 version, rO8
6 is similarly selected and used when reducing the A3 version to the A4 version, and rO87 is similarly used when reducing the A3 version to the 84 version.

In addition, VCLK (a) is inverted by an inverter 8 and applied as an inverted V CL K (c) to the clock terminal CK of a D-type 7-lip-flop circuit (hereinafter referred to as FFC) 9, and the carry output (&) of CUT 1 is It is fed to the data terminal of FFC9, and its inverted output (d) is fed to the CU
Since it is applied to the load terminal LOAD of Tl, when the count output (,) becomes rFJ in binary, r is sent to CUTl.
4J is 0-coded, and CUTl sets VCLK(b) to “5”.
”~rFJ is to be counted repeatedly.

On the other hand, the output of TO85 to γ is output from the selector (hereinafter referred to as 5EL).
)10 input terminal Do-D! According to the 3-bit reduced size designation signal (hereinafter referred to as REDS), 5EL10 selects and sends out one of the outputs of TO85 to TO7, so for example, RE
When DS is rO,0,OJ, 5EL10 is rO85
output (f) is selected and sent as a thinning signal (g).

Then, the output (f) is generated every predetermined order "8" of the count output (@) and rFJ, and this is the inverted VCL.
According to K(c), each output (h
) and (1), and both outputs (h)
, (1), the pulse width is expanded and becomes the output (h), which is given to the NOR gate 14 as the final thinning signal, and the inverted CLK (e). is also applied to the same gate 14, and as its output (k)/(e), a clock signal thinned out at a predetermined interval is obtained.

This output (k)/) is an FF used as a latch circuit.
' is applied to the clock terminal CK of C15, and the FF
The data terminal of Cl3 is given an image signal (hereinafter referred to as vos) (z) from the image sensor, and FFCl
3 uses the output (k)/←) as a clock signal and outputs VDS(t
) is repeated for each pixel, its output (n)
becomes an image signal thinned out at a predetermined interval, and this is sent to the output OUT.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the image clock signal is repeatedly counted, and when the count output reaches a predetermined value, a thinning signal is generated, thereby thinning out the image clock signal. By using this as a clock signal to repeatedly hold the serial image signal, software processing is no longer required, and document size reduction processing can be performed on the fly. Remarkable effects can be obtained.

[Brief explanation of the drawing]

The figures show embodiments of the present invention, with Figure 1 being a block diagram and Figure 2 being a block diagram.
The figure is a timing chart showing waveforms of various parts in FIG. 1. 1...Fist counter, 5-T...Thinning signal generation circuit, 14...ΦNOR gate, 15...Flip-flop circuit.

Claims (1)

[Claims] A facsimile machine that thins out serial image signals from an image sensor at predetermined intervals to reduce the document size includes a counter that repeatedly counts an image clock signal and a thinning signal when the count output of the counter is in a predetermined order. a gate circuit that thins out the image clock signal in accordance with the thinning signal; and a latch circuit that repeatedly holds the serial image signal using an output of the gate circuit as a clock signal. An image signal thinning circuit for a facsimile machine, characterized by: