JPH01140859A - Picture signal correcting device - Google Patents

Abstract

PURPOSE:To facilitate to settle the pulse width correction of a picture signal at a requested value by selecting an output for obtaining prescribed recording picture element width from the outputs of plural delay circuits with prescribed delaying characteristics. CONSTITUTION:A picture signal is inputted to a selection circuit 12 directly and through an inversion circuit 11, and the output of it is inputted to the delay circuit 1A with the delaying characteristic of t time corresponding to a requested minimum correction picture element width and the plural delay circuit 2A-nA with the delaying characteristics different by every t time. One of the outputs of these delay circuits 1A-nA is selected and outputted by the selection circuit 13 according to a correction picture element width designate signal. In a logical integrated circuit 14, a corrected picture signal is outputted from the output signal of the selection circuits 12, 13, and an output picture signal is outputted through the inversion circuit 15 and the selection circuit 16.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a single-picture signal correction device, and more particularly, to a single-picture signal correction device for modifying the pixel width of a 9i-element in the main scanning direction by modifying the pixel signal pulse width of a recording device such as a 7-axis recording device. This relates to the image signal correction circuit to be set.

BACKGROUND OF THE INVENTION Conventionally, this type of image signal correction circuit has had to use a clock several times higher in frequency than the recording pixel clock in order to obtain an image signal pulse corresponding to the minimum corrected pixel width.
For example, if the minimum correction pixel width is '/', then 1
A clock of t times the pixel clock is used to delay the human image signal by a shift register or the like, and the pulse width of the image signal is corrected by calculating the logical product of the delayed sub-signal and the input image signal. was.

However, the above-mentioned conventional image signal correction circuit cannot be solved by increasing the recording speed of the recording device and increasing the density of recording pixels. 7 The IE recording pixel clock itself has a very high frequency, and the clock used to perform F[ij times signal pulse width correction requires an even higher frequency, so it is necessary to set the minimum correction pixel width sufficiently small. This method is difficult and has the disadvantage that the pixel width that can be corrected becomes discrete.

The present invention has been made in view of the above-mentioned conventional situation,
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a novel image signal correction device that makes it possible to eliminate the above-mentioned drawbacks inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above objects, the two-signal correction device according to the present invention includes a seventh method for selecting either an input image signal or an image signal whose polarity is inverted from the input image signal. a selection circuit, n sets of delay circuits having delay times different by Δt time with respect to the input image signal, and a delay circuit output corresponding to a designated recording pixel correction amount from the n sets of delay circuit outputs. No. 1 selection circuit.

a pixel correction circuit that obtains an output by ANDing the human image signal and the output of the selection circuit of the editor; an inversion circuit that inverts the polarity of the output of the pixel correction circuit; The third one selects one of the outputs of the inverting circuit.
and a selection circuit.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

Referring to FIG. 1, the image signal a input to the terminal 10/
The polarity is inverted by the inverting circuit //, and in the 1 selection circuit /-, the pixel correction document signal J input from the terminal io
Accordingly, either the input image signal a or the polarity-inverted image signal S is selected. The output C of the selection circuit/co is Δt
It is input to a delay circuit /A having a delay characteristic of time, a delay circuit /A having a delay characteristic of Δt time, and a delay circuit jA -nA having a delay customization that similarly differs by Δt time, and is delayed according to each delay customization. image signal d
1 to dn are obtained.

Selection circuit/JVc'J? , one-pixel signals d1 to dn are generated according to the corrected pixel width designation signal 1 input to terminals io and y.
Choose one or seven! selected and output. AND circuit/
In Hiroshi, output signal C of 1 selection circuit 1 and selection circuit 1
A corrected image signal is output by logical product with the output signal e of 3. The inversion circuit is inverts the polarity of the corrected image signal f and outputs an inverted corrected image signal g. In the selection circuit /AVch, either the corrected image signal or the inverted corrected image signal g is selected according to the pixel correction type signal jK inputted from the terminal 101d, and output as the output image signal to the terminal io-.

With the above configuration. The operation of the circuit according to the tree embodiment will be explained with reference to the signal waveform diagram shown in FIG.

In FIG. 2, each symbol represents an electrical signal waveform at a point shown in FIG. The polarity of the round surface signal a inputted to the input terminal 10/1 is inverted by the 1-inverting circuit/l to become an inverted image signal A.

Next, as the output C of the selection circuit /Q, whichever of the input image signal a and the inverted image signal S is output according to the pixel correction type signal J input from the terminal /Qlt. Here, an embodiment is shown in which an input image signal a is output. The output signal C of the selection circuit /A becomes the image signal d1 delayed by the time Δt by the delay circuit /A.
Both signals d2 are delayed by a time, and one signal dn is similarly delayed by a time nXΔt by the delay circuit nA. Next, in the selection circuit /3, the image signals d1 to d are inputted from the terminal 103, and according to the correction pixel I/designation signal 1,
One is selected from n. Here, an embodiment is shown in which the image signal d2 is selected, and the same waveform as the image signal d2 is output as the output signal e of the 1 selection circuit 13. AND circuit/I
The output of I is the output signal C of 1 selection circuit/co and selection circuit/3
The corrected image signal is obtained by logical product with the output signal e. The inversion circuit 15 inverts the polarity of the corrected image signal and outputs an inverted corrected image signal g. In the selection circuit /6, either the corrected image signal f or the inverted corrected image signal g is connected to the terminal 1o.
The 1IIIi elementary correction image signal data inputted to tI is selected accordingly, and the image signal is outputted to the terminal 102. Here, an embodiment is shown in which the corrected image signal f is selected, and a four-waveform is shown as the corrected image signal as the output image signal.

Note that both the first selection circuit 7.2 and the selection circuit /6 select input signals based on the pixel capture signal jK, but the inverted image signal of the liI signal a input to the terminal 10/ is sent to the selection circuit 12. If the selection circuit 16 selects the inverted corrected image signal g, the circuit is configured to select the inverted corrected image signal g.
This defines the polarity of the pixel correction signal j to select whether the image signal pulse width is to be corrected by addition or subtraction, and the operation of the selection circuits /JP and /6 is determined by the polarity.

As described in detail, according to the present invention, as a means for correcting the pulse width of a single pixel signal, a delay circuit having a delay characteristic of Δt time corresponding to the required minimum correction pixel width and a delay circuit having a delay characteristic of Δt time that is different for each Δt time is used. From the outputs of multiple delay circuits having delay characteristics, in order to obtain a predetermined recording pixel width tl-, the output of the delay circuit corresponding to the corrected pixel width is selected. This provides the effect that the pulse width correction of the one-picture signal can be easily set to a required value without supplying a clock.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an image signal correction circuit according to the present invention, and FIG. 1 is an operation time chart of the image signal correction circuit shown in FIG. /A, CoA,...nA...Delay circuit, l/, B;-
...81 inverting circuits, /,7. /4... Selection circuit, /q... AND circuit Patent applicant NEC Corporation

Claims (1)

[Claims] In a recording device such as a facsimile that sets the recording pixel width according to the image signal pulse width in the main scanning direction, the first selection is to select between an input image signal and an image signal with the polarity of the input image signal reversed. a circuit, n sets of delay circuits having delay times different by Δt time with respect to the input image signal, and a delay circuit output corresponding to a designated recording pixel correction amount from the outputs of the n sets of delay circuits. a pixel correction circuit that obtains an output by ANDing the input image signal and the output of the second selection circuit; an inversion circuit that inverts the polarity of the output of the pixel correction circuit; and the pixel correction circuit. and a third selection circuit for selecting either the output of the inversion circuit or the output of the inversion circuit.