JPS61232776A - Encoding circuit - Google Patents

Abstract

PURPOSE:To make possible a high speed encoding by providing a change point detecting means, a mode forming means, a vertical mode counter, an adding means and a synthesizing circuit in an encoding circuit encoding a binary picture signal by a two-dimensional encoding system. CONSTITUTION:A reading circuit 1 scans an original picture, successively samples the obtained signals to convert into a binary signal and output a serial picture signal and a picture signal buffer memory 2 stores it as the encoding line information. A change point detecting circuit 3 reads a reference line picture signal and an encoding line picture signal and detects a change point changing the color of the picture element in both the lines. A runlength count circuit 5 carries out a count of the runlength during a horizontal mode. A mode forming circuit 6 carries out a mode formation from the change point information of the encoding line and the reference line. A vertical mode counter 7 counts the value of N and an adding circuit 8 corrects an output of the vertical mode counter 7. An encoding ROM table 10 receives the output of the runlength count circuit 5 and an output of a synthesizing circuit 9 and transmits the formed MR code.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an image signal encoding circuit capable of encoding image signals of facsimile machines, electronic files, etc. at high speed.

(Prior art) Conventionally, for the purpose of speeding up facsimile communication or efficiently storing data in electronic files, images and character information obtained by scanning a document are compressed by encoding and then transmitted or stored. things are being done. For encoding such image signals,1 there is an MR (Modified Read) method as specified in Recommendation T4 regarding the encoding of CCITT Group 3 facsimile machines. Dimensional codes are often used.

FIG. 6 shows a block diagram of a configuration example of a conventional apparatus for performing such software two-dimensional encoding. As shown in the figure, this software two-dimensional encoding apparatus includes a reading circuit 21. Change point detection circuit 22, change point position Karafu 2
31 picture signal buffer memory 24, microprocessor (
MPU ) 25, encoding RO table 26, encoding buffer memory 27 and P/S (parallel/serial)
It is composed of a conversion circuit 28. Regarding the operation,
The signals obtained by sequentially scanning the original image are sent to the reading circuit 21.
The signal is sequentially sampled and converted into a black and white binary signal, which is then supplied to the change point detection circuit 22 as a serial image signal. The change point detection circuit 22 detects a change point from a white pixel to a black pixel or from a black pixel to a white pixel, while the change point position counter 2
3 counts the absolute value of the position of the change point, and the count value is stored in the image signal buffer memory 24 as an absolute address. A microprocessor (HPU) 25 reads information on the current encoded line and the previous reference line from the image signal buffer memory 24, performs arithmetic processing on the encoded line based on the reference line, and encodes the processing result. The MR code is obtained by giving it as the address of the encoded PON table 26. The obtained MR code is converted from parallel data to serial data by the P/S circuit 28 via the code buffer memory 27, and then sent to the receiving side.

(Problems to be Solved by the Invention) However, in the conventional device with the above configuration, since arithmetic processing is performed by a microprocessor, encoding takes time, and it cannot be applied to CCIT↑ Group 4 facsimile devices, which require higher speed. The problem was that it was difficult.

Therefore, the present invention solves the problem of the conventional technology that encoding takes time, and provides an image signal encoding circuit that can perform high-speed encoding and is suitably applicable to CGITT Group 4 facsimile machines. The purpose is to

(Means for Solving the Problems) The present invention relates to an encoding circuit that encodes a binary image signal using a two-dimensional encoding method. The present invention includes a means for creating a mode, a vertical mode counter, an adding means, and a synthesizing circuit.

The change point detection means detects the position where the pixel value changes on the encoded line and on the reference line which is the line immediately before the encoded line. The mode creation means creates various modes including a pass mode, a horizontal mode, and a vertical mode based on the output from the change point detection means. In vertical mode, the vertical mode counter counts the first change pixel on the encoded line to the right of the origin change pixel, and the first change pixel on the reference line that is to the right of the origin change pixel and has a different value from the origin change pixel. The relative distance from the changed pixel (in the example, the relative distance It between a and bl) is counted in pixel units. The addition means is connected to the output of the vertical mode counter, and the 0 synthesis circuit that adds the correction value to the count value of the vertical mode counter and outputs the result during encoding processing at the end of the l line adds the correction value to the output of the mode creation means. The outputs of the means are combined and output.

(Operation) The change point detection means detects the change point between the encoded line and the reference line (in the embodiment, aa m81 * al e bl
*G) is detected. Based on this information, the mode creation means includes path mode, horizontal mode, and vertical mode (V-, VA).
.

Create a mode such as V (0) ). When the mode is vertical mode, the vertical mode count is reset, and the distance (N) from a specific pixel (al) on the encoded line to a specific pixel (bl) on the reference line is counted. The addition means calculates the count value of the vertical mode counter and the actual distance (
Correct the count value if N) no longer match.
Then, the synthesis means outputs the outputs (VL, V
A) and the output (N) from the adding means are combined and the combined value (VL(N), 1Ja(N)-V(0)) is output. When the mode is other than the vertical mode, the vertical mode counter is not reset, nor is the output from the adding means, and the combining means outputs the modes such as pass mode and horizontal mode from the mode generating means as they are. Therefore, according to the present invention, encoding can be performed at high speed, and the problems of the prior art described above are solved.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of the present invention. The encoding circuit of this embodiment includes a reading circuit 1, an image signal buffer memory 2, a change check circuit 3, a control circuit 4, a run length counting circuit 5, a mode creation circuit 6. It is composed of a vertical mode counter 7, an adder circuit 8, a synthesis circuit 9, and an encoding ROM table IO. Regarding the connection relationship between each circuit, the output of the reading circuit l is output from the image signal buffer memory 2.
The output of the image signal buffer memory 2 is connected to a change point detection circuit 3, and the output of the change point detection circuit 3 is connected to a control circuit 4. The output of the control circuit 4 is sent to a run length counting circuit 5. It is connected to a mode creation circuit 6, a vertical mode counter 7, and an addition circuit 8, respectively. The output of the vertical mode counter 7 is connected to an adder circuit 8, and the output of the adder circuit 8 and the output of the mode creation circuit 6 are connected to a synthesis circuit 9.

The output of the adder circuit 8 is also connected to the control circuit 4. The output of the run length counting circuit 5 and the output of the combining circuit 9 are encoded R
Connected to the OM table 10.

The reading circuit 1 sequentially samples signals obtained by scanning an original image, converts them into binary signals, and outputs serial image signals.
The image signal buffer memory 2 stores the serial image signal from the reading circuit 1 as encoded line information. The change point detection circuit 3 reads the reference line image signal and the encoded line image signal from the image signal buffer memory 2, and detects change points a, , a, Ia where the color (value) of the pixel changes in both lines.
! Detect A *bx. Here aoIa4, a>
, bl, b are defined as follows.

a,: Starting point change pixel a,: a on the encoding line. The first changed pixel on the right side al: a on the encoding line, the first changed pixel on the right side: a, the first changed pixel on the reference line with the opposite color to ao on the right side: reference Also the first change pixel to the right of bl on the line. Here, three modes, path mode, vertical mode, and horizontal mode, are defined as follows.

(i) When path mode = b is located to the left of a (ji) When vertical mode l''*bvl≦3, al
When is to the left of bl, VL(N).

When al is to the right of bl is Vu(N), a4 and b1 toca same When it is in the column, press the beam (0) and , N is the relative position of a4ba It is a place.

('+ii) Horizontal mode: When la, b il≧4 The control circuit 4 uses the run length counting circuit 5, mode creation circuit 6, vertical mode counter 7, and addition circuit 8 based on the output of the change point detection circuit 3. controls the operation of each circuit,
The run length counting circuit 5 counts the run length in the horizontal mode, and the mode creation circuit 6 creates a mode from the change point information of the encoded line and the reference line, that is, horizontal mode, vertical mode VL (N), Vu.
(N) −V (of.

A vertical mode counter 7, which creates modes such as pass mode, EOL, and RTC, counts the value of N in the vertical mode. The adder circuit 8 corrects the output of the vertical mode counter 7 based on the correction information from the control circuit 4 when performing the termination process of the l line.

A synthesis circuit 9 synthesizes the output of the mode creation circuit 6 and the output of the addition circuit 8 and outputs the result. The encoding ROM table IO receives the output of the run length counting circuit 5 and the output of the combining circuit 9, and transmits the created MR code to the receiving side via a latch circuit and a P/S circuit (not shown).

Next, the operation will be explained. First, the serial image signal from the reading circuit 1 is directly input to the image signal buffer memory 2, and the reference line image signal and the encoded line image signal read out simultaneously from the 0 image signal buffer memory 2 are stored as encoded lines. .

At the same time, each change point a is input to the change point detection circuit 3.
. , a, , ai, bl are detected as follows. here,
For example, if the image signal shown in FIG. 2 is input to the change point detection circuit 3, the output a1 of the change point detection circuit 3 will change from 0 to 1 at the point where the image signal of the encoded line changes from white to black. , the output ayu changes from 0 to l at the point where it changes from black to white. Similarly, the output b1 changes from 0 to l at the point where the image signal of the reference line changes from white to black.

The control circuit 4 detects that the output aI of the change point detection circuit 3 changes from 0 to 1, resets the vertical mode counter 7, and starts counting the value of N in the vertical mode. (Counting the distance of a, crow) First, the address of the image signal buffer memory 2 is +IL, and the vertical mode counter 7 is +1. At this time, the value remains 0. Similarly, the address of the image signal buffer memory 2 is set to +IL and the vertical mode is set to address +IL. At this time, bl remains at 0. Furthermore, the address of image signal buffer memory 2 is +1.
Then, the vertical mode counter 7 is incremented by 1.

At this time, S, a, and L are all 1, and VL(
3) is encoded as That is, the control circuit 4 detects a, b, and notifies the mode creation circuit 6 of the vertical mode V+-. Since the vertical mode counter 7 is set to 3 as described above, 3 is input to the input A of the adder circuit 8, and 0 is input to the output of the control circuit 4, that is, the input B of the adder circuit 8. Therefore, the output of the adder circuit 8 is 3, so by inputting v5 and 3 to the 1 synthesis circuit 9, the output of the synthesis circuit 9 becomes VL(3), which is output as 0 as the address of the encoding ROM table IO. With the above steps, the encoding from a to al in FIG. 2 is completed.

In the next encoding, as shown in FIG.
becomes a, therefore, the address of the image signal buffer memory 2 must be returned to point a in FIG. 3, and the vertical mode counter is at point a in FIG.

Since it is counted from bl to bl, by decrementing the address of the image signal buffer memory 2 until it becomes 0, the address is as shown in FIG.

Return to the point of 0 or more, and after the mode encoding is completed, the vertical mode counter 7 sets a for the next encoding.
, it becomes possible to find.

However, when bl is a virtual change point as shown in FIG. 4, the address of the image signal buffer memory 2 is one address before bl, that is, on the end pixel.

Therefore, the vertical mode counter 7 is 2.

However, since the encoded code should be VL(3), the output of the control circuit 4, that is, the input B of the adder circuit 8, is set to 1.
VL(3) is finally output as the address of the encoded ROM table IO.

In preparation for the next encoding, the vertical mode counter 7 is decremented until the output (=2) becomes 0, and at the same time,
By decrementing the address of the image signal buffer memory 2, the address becomes a as shown in FIG. By using the vertical mode counter 7 and the addition circuit 8, it becomes possible to replace the change point a1, which has been encoded, with ao to be encoded next, as in the case of 0 or more returning to the pixel of .

(Effects of the Invention) As described above in detail, according to the present invention, since vertical mode encoding can be performed at high speed, there is an advantage that the time required for encoding can be significantly shortened. Therefore, the present invention can be suitably applied to COI TT Group 4 facsimile machines that require high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an encoding circuit according to an embodiment of the present invention, FIGS. 2 to 5 are diagrams used to explain the above embodiment, and FIG. 6 is a block diagram of a conventional encoding circuit. It is. l...Reading circuit 2...Image buffer memory 3...Changing point detection circuit 4...Control circuit 5...Run length counting circuit 6...Mode creation circuit 7...Vertical mode counter 8 ...Addition circuit 9...Composition circuit 10...Second diagram of encoding ROM table. Figure 3

Claims (1)

[Scope of Claims] In an encoding circuit that encodes a binary image signal using a two-dimensional encoding method, a change point detection means for detecting a position where a pixel value changes on an encoding line and a reference line immediately before the encoding line. and mode creation means for creating various modes including a pass mode, horizontal mode, and vertical mode based on the output of the change point detection means, and a mode creation means connected to the output of the change point detection means and configured to generate an encoded line when in the vertical mode. Count the relative distance in pixels between the first changed pixel to the right of the origin changed pixel and the first changed pixel on the reference line that is to the right of the origin changed pixel and has a different value from the origin changed pixel. a vertical mode counter; connected to the output of the vertical mode counter;
Adding means for adding a correction value to the count value of the vertical mode counter and outputting the result during encoding processing at the end of a line; and a combining circuit for combining and outputting the output of the mode creating means and the output of the adding means. An encoding circuit comprising: and.