JPH02150146A - Instrument and method for testing communication equipment - Google Patents

Abstract

PURPOSE:To test critical ability concerning the reception of a communication controller to be tested and a terminal controller and to facilitate the verification of a product quality by deleting or inserting a synchronous flag, and arbitrarily making variable a telegram interval. CONSTITUTION:The communication data of the telegram are accumulated in a memory 9, the writing and reading of the memory 9 is independently controlled, the synchronous flag is deleted or inserted at the designated arbitrary data interval between the communication data, the telegram is changed so as to have various lengths, and resent. Thus, in the communication equipment in a network system, the critical ability of the communication equipment can be tested through a communication line 4 on-line, further, by inserting the test device to the communication line 4 between the plural pieces of the communication equipment in the network system and testing the communication equipment, the performance of the communication equipment can be checked on-line.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a testing device and a testing method for a communication device that transmits and receives messages having a plurality of synchronization flags at the beginning of communication data over a communication line, and particularly relates to The present invention relates to a test device and a test method that arbitrarily vary the length of the synchronization flag of a message sent to a communication device, perform a variable data interval test, and test the limit capability of a communication device.

[Conventional technology]

For example, in a network system in which a plurality of computer systems 11 are connected through communication lines to form a system, a communication device connects each system through communication lines. Such communication devices communicate via communication lines between each communication device according to a predetermined transmission procedure. In communication using communication lines performed by communication devices, a common transmission procedure is used as a transmission procedure when performing communication so that communication is possible between any communication devices. As a transmission procedure in such communication, for example, there is an HD LC transmission procedure. This HDLC transmission procedure eliminates the shortcomings of the basic mode control procedure and provides efficient transmission and scalability.

This procedure was developed to improve reliability.

The information to be transmitted is accommodated in a prescribed frame called a frame, and is uniformly transmitted regardless of the type of information.

Enables full-duplex communication for efficient transmission and performs continuous frame transmission. It also enables conversational operation and simultaneous transmission with multiple secondary stations, increasing transmission efficiency. Transmission is performed using frames to maintain scalability.
Code-independent transparent transmission. To further improve reliability, error control is performed by adding equivalent check information to all frames.

[Problem to be solved by the invention]

By the way, in this way, HD for efficient transmission
In the LC transmission procedure, the synchronization flag between consecutive messages may be at least one character. Therefore, a communication device that performs communication using the HDLC transmission procedure has the ability to perform normal communication operations even for high-load messages where the synchronization flag between consecutive messages is one character. must be maintained.

However, conventional test equipment for communication equipment is not capable of testing high-load messages such as one-character synchronization flag between consecutive messages, and it is not possible to test the performance of communication equipment sufficiently. The problem was that it could not be done. In addition, the exam is also conducted offline,
The exam was not conducted online. For this reason,
Since transmission quality conditions such as noise characteristics and electrical characteristics vary depending on the communication line used by the communication device, test equipment for this type of communication device conducts online tests during actual operation. It is desirable to have a test function that can confirm the limit of communication performance.

If the limit capability test for high-load messages has not been sufficiently tested online for the communication device, messages with a synchronization flag of 1 character will be continuously received when the communication device is operated in a network system. There is a problem in receiving such high-load messages that there is a risk of an accident.

The present invention has been made to solve the above problems.

SUMMARY OF THE INVENTION An object of the present invention is to provide a communication device testing device and a testing method that can perform a limit capability test for high-load message reception on a communication device that communicates via a communication line.

Another object of the present invention is to arbitrarily vary the interval between input messages for messages transmitted via a communication line in order to test a communication device that communicates via a communication line. The object of the present invention is to provide a test device that enables variable data interval testing.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

In order to achieve the above object, the present invention provides a test device for a communication device that transmits and receives a message having a plurality of synchronization flags at the beginning of communication data via a communication line, including a comparator that detects a synchronization flag of a received message; A memory that stores communication data, a memory control circuit that independently controls writing and reading data to the memory, reads the communication data stored in the memory, inserts synchronization flags at specified intervals, and generates a message. and a test control circuit that reconfigures and transmits.

Further, in a test method for a communication device that transmits and receives a message having a plurality of synchronization flags at the beginning of the communication data over a communication line, the synchronization flag of the received message is detected and write control is performed to store communication data in a memory, Interpolation is performed using a test device that independently controls data readout from the memory, reads communication data stored in the memory, and interpolates synchronization flags at specified arbitrary intervals to reconstruct and transmit the message. The feature is that a limit performance test is performed by changing the interval specification of the synchronization flag.

In addition, this test device is inserted between communication lines between communication devices in a network system in which communication devices are interconnected via communication lines to test communication devices and check communication devices online. It is characterized by

[Effect]

According to the above means, there is provided a testing device for a communication device.

It includes a comparator that detects a synchronization flag, a memory that stores communication data, a memory control circuit, and a performance test control circuit. The comparator inputs the message being communicated over one communication line and detects the synchronization flag added to the beginning of the communication data. In other words, the comparator determines whether the message input from the communication line is a synchronization flag pattern at the 4th place among the characters, or
A check is made to see if it is any other pattern, and if it is other than the synchronization flag pattern, it is communication data, and the characters are sequentially stored in the memory. At this time, a synchronization flag is sent to the output communication line. When using a synchronous flag pattern,
An arbitrarily determined number of flags is stored in the memory, but if this number is exceeded, a synchronization flag is directly sent to the output communication line. Communication data stored in memory is
After an arbitrary predetermined time has elapsed, the data is read from the memory and sent to the output communication line. In other words, the comparator detects the synchronization flag of the input message, stores it in the memory, deletes or inserts the synchronization flag in the message according to the specified contents, changes the message interval, and outputs the communication. sent to the line. In this case, the message interval can be changed by inserting or deleting the synchronization flag, but
The data inside the message is stored in the memory, read out as is, and output without change, so there is no possibility of malfunction.

In this way, the communication data of the message is stored in the memory, writing and reading of the memory are controlled independently, and synchronization flags are deleted or inserted at specified data intervals between the communication data, and various The message is changed to a message with a length of , and then resent. Thereby, in the communication device of the network system, the limit capability of the communication device can be tested online via the communication line.

Further, by inserting this test device between communication lines between communication devices of a network system and testing the communication devices, it is possible to check the performance of the communication devices online.

〔Example〕

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

FIG. 1 is a system diagram showing the position of a test device according to an embodiment of the present invention in a network system. In FIG. 1, 1 is a communication control device, 2 is a communication line test device,
3 is a terminal control device, and 4 is a line interface (communication line). As line interface 4, HD
V24 interface, X21 interface supporting LC transmission procedure or SYN synchronous transmission procedure,
There are high-speed digital line interfaces, etc. Below 1
The line interface 4 will be explained using a communication line that supports the I-(DCL transmission procedure) as an example.

The message from the communication control device 1 has a format in which a plurality of synchronization flags are provided at the beginning, followed by a data section, and a synchronization flag is provided at the end. The message reaches the communication line testing device 2 via the line interface 4. The communication line testing device 2 acts on the synchronization flag in the message, does not affect the data in the data section, and resends the message to the terminal control device 3 via the line interface 4. From terminal control device 3 to communication control device 1
The message to is also transferred via the communication line testing device 2 in the same way.

FIG. 2 is a block diagram showing the flow of messages in one direction in the communication line testing device. The block diagram in FIG. 2 shows, for example, the flow of messages from the communication control device 1 to the terminal control device 3 in the communication line testing device 2. In FIG. 2, 5 is a receiver, 6 is a comparator, 7 is a memory control circuit, 8 is a write register, 9 is a memory, 10 is a read register, and 11 is an I-transmitter. Also,
12 is a selector, and 13 is a shift register that generates a synchronization flag or test data. Further, 14 is a control circuit that outputs a control signal according to the content to be tested based on an instruction given from the outside. The flow of data from the shift register 13 to the transmitter 11 via the selector 12 is the flow when inserting a synchronization flag or test data, and when the transmitter 11 is configured to insert test data and synchronization flags. , and independently controls data reading from the memory 9,
When interpolating or deleting the synchronization flag, the configuration of the selector 12 and shift register 13 is not required.

When the data of the message is being communicated via the communication line, a synchronization signal is detected in the flow of the receiver 5, the comparator 6, and the memory control circuit 7, and the data is sent to the receiver 5, the write register 8,
A data message flows in the order of memory 9, read register 10, and transmitter 11. The memory 9 repeats a write operation and a read operation in order.

The memory write start address (initial value) and the memory read start address are the same. The memory write address and memory read address are updated by the memory control circuit 7.

When a message having a plurality of synchronization flags at the beginning of the data successively reaches the comparator 6 via the receiver 5 of the communication line testing device 2, a series of messages that essentially change the message length by a control signal from the control circuit 14 are transmitted. A sequence of operations begins.

Hereinafter, for ease of understanding, the operation will be described for the case where two consecutive messages are received. First, when the first character of the first message is input, the comparator 6 compares each character to see if the character is a synchronization flag pattern or something else. In the case of a synchronous flag pattern, the write address and read address of the memory 9 are not updated, the synchronous flag pattern is written to the address, and then the data at the address is read and sent to the line interface via the read register 10 and transmitter 11. Send to 4. This operation is performed sequentially character by character. When a character other than the synchronization flag pattern is input, the comparator 6 instructs the memory control circuit 7 to write the memory 9 write address +1, updates the write address sequentially, and inputs a character other than the synchronization flag pattern. written to memory sequentially. Since the read address 1 (response) is not updated, the synchronization flag pattern of the initial 1 address is sent to the line interface 4 via the read register 10 and transmitter 11 while data is being written to the memory 9.

This operation is executed sequentially for each input character, and the data part of the first message is stored in the memory 9, and the time period during which it is stored is transferred to the line interface 4 by the memory read operation as described above. The synchronization flag pattern is sent.

Next, processing for the synchronization flag pattern sandwiched between the first data part and the second data part of two consecutive messages will be described. An arbitrarily designated number of synchronization flag patterns during this period are stored in the memory 9 under the control of the comparator 6. During this stored time zone, a synchronization flag pattern is sent to the transmitter 11 by the above-mentioned memory read operation. For synchronization flags that follow the specified number of synchronization flags, the memory control circuit does not update the write address, and the synchronization flag pattern is overwritten at the same address. During this time, the read address of memory 9 is not updated, so memory 9 of the initial value address
The synchronization flag pattern is read out from the read register 10. It is sent to the line interface 4 via the transmitter 11.

If the synchronization flag ends within the arbitrarily determined time in the comparator 6 and the beginning of the second data is input (a character other than the synchronization flag pattern is input), the comparator 6 The memory control circuit 7 is instructed to write the memory 9 write address +1, and the write address is sequentially updated to continue storing in the memory 9. On the other hand, at this timing, the read address of the memory 9 is sequentially updated (+1) L
While doing so, start reading. The read character is
It is sent from the read register 10 to the line interface 4 via the transmitter 11.

This operation is continued until the sending of the second message is completed.

] If the synchronization flag between the first and second messages is
If it does not end within an arbitrarily determined time, the read address of the memory 9 is updated sequentially as a timeout (
+1) Start reading while at L. The read character is transferred from the read register 10 to the transmitter 11.
is sent to line interface 4 via.

If reading is started as a timeout and the beginning of the second data is input during reading, the write address of memory 9 is sequentially updated (+1) in parallel with the read operation of memory 9, and the data is transferred to memory 9. is stored.

Regarding the synchronization flag after the second data, the memory control circuit 7 does not update the write address for the synchronization flag following the specified number of synchronization flags. Reading from the memory 9 is performed sequentially from the start address at the time of writing, and once the read operation is started, it is continued until it matches the current value of the write address. After the addresses match, both the write address and read address are returned to their initial values, and the above-described operation is repeated. With the above operation, when two consecutive messages are input, the number of synchronization flags sandwiched between the two data is compressed to an arbitrary number and output.

FIG. 3 is a diagram illustrating the relationship between the input message and the output message. As shown in Fig. 3, input message data a,
The synchronization flag sandwiched between data b is compressed and output as an output message.

Additionally, a message is output in which the length of the synchronization flag is set to an arbitrary length.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As explained above, according to the present invention, the message interval can be arbitrarily varied by deleting or inserting the synchronization flag.
The reception-related limit capability of the communication control device or terminal control device under test can be tested, and the quality of the product can be easily verified. Further, by inserting this test device between communication lines between communication devices of a network system and testing the communication devices, it is possible to check the communication devices online.

[Brief Description of the Drawings] Fig. 1 is a system diagram showing the position of a communication line testing device according to an embodiment of the present invention in a network system, and Fig. 2 shows the flow of messages in one direction in the communication line testing device. FIG. 3 is a diagram illustrating the states of the input message and the output message. In the figure, 1... Communication control device, 2... Communication line testing device, 3... Terminal control device, 4... Line interface (communication line), 5... Receiver, 6...
Comparator, 7...Memory control circuit, 8...Write register, 9...Memory, 10...Read register, 11
...Transmitter, 12...Selector, 13...
- Shift register, 14... control circuit.

Claims (1)

[Scope of Claims] 1. A test device for a communication device that transmits and receives a message having a plurality of synchronization flags at the beginning of the communication data via a communication line, comprising a comparator that detects the synchronization flag of the received message and a comparator that stores the communication data. a memory that independently controls data writing and data reading to the memory, a memory control circuit that reads the communication data stored in the memory, and reconstructs the message by inserting synchronization flags at specified arbitrary intervals. 1. A test device for a communication device, comprising a test control circuit for transmitting data. 2. In a test method for a communication device that transmits and receives a message having a plurality of synchronization flags at the beginning of the communication data via a communication line, detecting the synchronization flag of the received message and performing write control to store communication data in a memory, Interpolation is performed using a test device that independently controls data readout from the memory, reads communication data stored in the memory, and interpolates synchronization flags at specified arbitrary intervals to reconstruct and transmit the message. A communication device testing method characterized by performing a limit performance test by changing the interval specification of synchronization flags. 3. Testing a communication device by inserting the communication device testing device according to claim 1 between communication lines between communication devices of a network system in which communication devices are interconnected via communication lines; A method for testing a communication device, characterized by checking the communication device online.