JPH04344736A - Line test system - Google Patents

Abstract

PURPOSE:To realize the technology in which the line test with simple constitution is attained in a packet exchange network and various kinds of statistic information are easily obtained. CONSTITUTION:A line terminal device 6 is interposed between a 1st packet terminal equipment 1 and a 2nd packet terminal equipment 2, the line test device 6 is provided with a discrimination means 4 recognizing a specific bit pattern and provided with a pattern registration means 5 in which a test pattern is registered in advance. The discrimination means 4 monitors a bit pattern of a data sent from the 1st packet terminal equipment 1 and reads the test pattern from a pattern registration means 5 when the bit pattern corresponds to a specific bit pattern to replace the test pattern with the bit pattern and outputs it to a 2nd packet terminal equipment 2.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique that is effective when applied to line testing between terminals in a packet communication network.

0002

[Prior Art] In this type of packet switching network, X in the CCITT recommendation is used as a link level protocol.
．． When the 25 level 2 mode is adopted, various statistical information due to link disturbance can be obtained.

[0003] An overview of such a test method in the prior art will be explained using FIG. 4. As shown in the figure, a first packet terminal 1 and a second packet terminal 2 face each other and are connected to a line 3, and both terminals have X. The device is equipped with an interface section 7 based on the X.25 protocol.

[0004] In the interface section 7, "T"
"" means a transmitted signal, "R" means a received signal, "C" means a control signal, "I" means an instruction signal, and "S" means a signal element timing signal.

[0005] In the figure, the transmission and reception of each signal is conceptually shown, but in reality, the transmission and reception between the two terminals is carried out through a two-wire line according to CCITT Recommendation V11.

[0006] When performing a line test in a link disturbance state using the method shown in the figure, RR (Receive
Ready) transmissions and RR receptions can be counted, but it is not possible to obtain more detailed line information, such as FCS errors, invalid frames, fractional bits, A (address) field end definition, and retransmission count. could not.

[0007] Therefore, in order to obtain the above-mentioned error information, it was necessary to connect a protocol testing device in place of the second packet terminal 2, for example.

[0008]

However, since the protocol test device generates various signals by assuming in advance various errors caused by link disturbances, the device configuration becomes complicated, and the device cost and scale increase. I had no choice but to grow up.

The present invention has been made in view of the above-mentioned problems, and its purpose is to provide a technique that enables line testing with a simple configuration and easily obtains various statistical information.

0010

[Means for Solving the Problems] The present invention provides a circuit testing device 6 interposed between a first packet terminal 1 and a second packet terminal 2, and a specific bit pattern is applied to the circuit testing device 6. In addition to providing a determining means 4 for recognizing, a pattern registering means 5 for registering test patterns in advance is provided, and the determining means 4 monitors the bit pattern of the data sent from the first packet terminal 1. If this corresponds to a specific bit pattern, the pattern registration means 5
A test pattern is read out from the data center, replaced with the data, and outputted to the second packet terminal 2.

[0011]

[Operation] In the present invention, as shown in FIG. 1 which is a diagram of the principle,
The determining means 4 in the line testing device 6 constantly monitors whether the data from the first packet terminal 1 corresponds to a specific bit pattern (step 101). If this does not correspond to a specific bit pattern, the packet is directly output to the second packet terminal 2.

On the other hand, if the pattern corresponds to a specific bit pattern, the test pattern is read out from the pattern registration means 5 (102), the data is rewritten (103),
The data rewritten into the test pattern is output to the second packet terminal 2.

As described above, in the present invention, the line testing device 6 is interposed between the packet terminals 1 and 2, and outputs data through-output in the normal state, and outputs a test pattern only when data of a specific bit pattern is recognized. do. Therefore, by simply changing the transmission data format at the sending terminal (first packet terminal 1), it is possible to send out various test patterns, easily generate a pseudo disturbance state, and use a simple configuration to It becomes possible to conduct the test.

[0014]

Embodiment FIG. 2 is a block diagram showing the overall configuration of the information transmission system of the present invention.

In the figure, the first packet terminal 1 (DTE1
) and the second packet terminal 2 (DTE2) are line termination devices (DCE1, DCE2) placed on each terminal side.
2), a packet multiplexer (PKT1, PKT2), a transmission multiplexer (MUX1, MUX2), and a transmission path 8.

FIG. 3 is a conceptual diagram showing the transmission signals between the packet terminal (DTE) and the circuit terminating equipment (DCE), and the contents of each signal are explained in FIG. 4 in the prior art. Since it is the same as that described above, the explanation will be omitted.

The packet terminal (DTE) is connected to, for example, a central control unit (CC) and controlled by a control system.

The packet terminal (DTE) is also equipped with an interface unit 7, and this interface unit 7 supports, for example, X. Performs communication control specified in the 25 protocol.

FIG. 6 shows the structure of a data frame in this embodiment. The data frame is equipped with an 8-bit flag field (F) before and after it, and is “01111
110'' bit strings indicate the start and end of the data frame.

[0020] Following the flag field (F), there is provided an address field (A) also having an 8-bit configuration, and normally, the address of the secondary station is written in this field.

[0021] The control field (C) is also composed of 8 bits, and the type of operation to be performed on the communication partner receiving the frame is registered as a command.

[0022] The information field (I) has an arbitrary bit length and contains necessary control information other than frame transmission control.
Alternatively, record an actual information message, etc.

[0023] The frame check sequence (FCS) is an error control field for checking whether the contents of the entire frame have been accurately transferred, and error checking is performed based on the CRC method.

[0024] Such data frames can be roughly divided into information transfer frames (I frames), monitoring frames (S frames), and unnumbered frames (U frames).
The control fields (C) have different configurations as shown in FIG.

In FIG. 7, N(S) indicates a transmitting sequence number on the transmitting side, and N(R) indicates a receiving sequence number on the transmitting side. Further, P/F indicates a poll bit (P) when the frame data is sent as a command, and functions as a final bit (F) when it is sent as a response. In the figure, S is a monitoring function bit, and M is a modification function bit.

In this embodiment, the first packet terminal 1 (
A line testing device 6 is connected between the DTE 1) and the second packet terminal 2 (DTE 2).

FIG. 5 conceptually shows this connection state.
It is. In the figure, the line testing device is configured such that the first packet terminal 1 (DTE1) and the second packet terminal 2 (DTE2) face each other and receive the transmission T from the first packet terminal 1 (DTE1) at the signal element timing S. 6 is connected.

FIG. 8 shows the circuit configuration of the line testing device 6 of this embodiment. The line testing device 6 includes shift registers 120 to 126 each having an 8-bit configuration and connected in seven stages, PROMs 110 to 115 each having an 8-bit configuration, an AND gate as the determining means 4, and a latch FF 130. There is.

Test patterns are registered in the PROMs 110-115, and these test patterns are loaded into shift registers 120-126 by means described later.

In the circuit shown in the figure, when a specific bit pattern is received and synchronization is established, PROMs 110 to 1
Shift the test pattern from 15 to registers 120 to 126
This generates pseudo data as if the data on line 3 had changed due to disturbance. The details will be explained below.

First, the first packet terminal 1 (PKT1) receives two information data, "43h" and "33h".
Assume that a byte of data has been sent.

[0032] As a result, the address field (A) following the flag field (F) of the data frame contains the partner station address "01h", and the control field (C) contains N.
From (S)=000h, P=0, N(R)=000, “0
0h” is inserted, and “43h” is inserted in the information field (I).
" and "33h" are respectively inserted, and "73h" and "8Fh" are respectively inserted into the frame check sequence (FCS).

Here, "43h" inserted into the upper two bytes of the information field (I) is defined as a command that pseudo-generates an undefined address field.

[0034] Also, in the address field (A), from the perspective of the first packet terminal 1 (PKT1), the own station address is "03h" and the other station address is "01h".
shall be. Therefore, the second packet terminal 2 (PKT2)
When viewed from the station, the address of the own station is "01h" and the address of the other station is "03h".

[0035] Such a data frame is further input to a latch FF via shift registers 120-126. Here, the transmission T is input to the shift registers 120 to 126 as the signal SDI, but the signal element timing signal S is input to the inverter circuits 150 and 151 as an inverted signal of the signal ST1, as shown in FIG. A clock consisting of the positive and negative signals of ST1 is generated. This relationship is shown in the timing chart of FIG.

The SDI inputs of the shift registers 120 to 126 are shifted in by an inverted signal of the clock ST1. At this time, the inverted signal of ST1 is inputted as a clock to all shift registers 120-126.

When the data frame start flag is set in the shift register 126, the shift register 1
25 has address "01h", shift register 124 has control code "00h", shift register 123 has information data "43h", shift register 122 has information data "33h", shift registers 121 and 122 have frame check The sequence (FCS) code is “7”.
3h" and "8Fh" are respectively set.

The shift registers 120 to 126 output the output from the flag (shift register 126) and the seventh bit (") of the shift register 125 that determines the address.
0"), the first bit ("0") of the control field (C) that determines the information transfer frame, and the first bit ("1") of the information field (I) that determines that a line test will be performed.
) respectively. Note that an inverter 11 is connected to each input of the AND gate 10 that corresponds to the output of "0" in this setting, and the AND condition is established in the setting, and "1" is output from the AND gate 10 as the output signal S0. It is now sent out.

The output signal S0 is sent to the shift register 12.
It is input as S0 of No. 3, 124, and is also input to other shift registers 120, 121, 122, 125, 126.

Address input A of PROM110-115
The first bit to the eighth bit (43h) of the shift register 123 are input to 0 to A7. PROM110-1
In this address No. 15, a test pattern shown in FIG. 8 for obtaining statistical information with an undefined address field is registered. That is, the PROM 115 has an address of 07h, the PROM 114 has a control code of 00h,
In the PROMs 113 and 114, 43h and 33h are registered as information data, and in the PROMs 111 and 110, for example, E9h and C4h are registered as corrected FCS.

The output signal S0 of the AND gate 10 is "
1'', the output of the PROM group described above is loaded into the shift registers 120 to 125. This timing is the portion indicated by ``ROM OUT'' in FIG.

In FIG. 20, SFR indicates the output of the shift register, and the output of the shift register 126 at the final stage is input to the latch FF130, and the output from the shift register 126 at the final stage is input to the latch FF130,
Latched by signal. As a result, latch FF13
An output signal SD0 that is in phase with that of 0 can be obtained. In addition,
The shift register shown in FIGS. 8 and 9 is S0=0, S
When 1=1, it is shifted to the left.

As described above, in this embodiment, a case has been described in which a test pattern with an undefined address field is generated, but it is also possible to generate other pseudo error patterns. For example, in the case of an FCS error, when 11h is inserted in the information field, the test pattern that causes the FCS error is loaded from the PROM address 11h into the shift register.

At this time, the data of the PROM 113 is not loaded into the first bit of the shift register 123, and the original information frame is sent to the packet terminal (PKT2).
Send to.

In this manner, by selectively loading the test pattern on the PROM side into the shift register side, a data frame having a pseudo FCS error can be sent to the second packet terminal 2 (PKT2).

[0046] In the above explanation, the information transfer frame (
Although the explanation has been given regarding the I frame), the supervisory frame (S frame) and the unnumbered frame (U frame) are also transmitted through the line testing device 6.

Although the present invention has been described above based on examples, the present invention is not limited to the above-mentioned examples.

For example, in the embodiment, the information data field (I) has a 16-bit structure, but it may have an 8-bit structure or a structure of 32 bits or more.

[0049] Also, as the pattern registration means 5, PROM
However, other registration means such as EPROM or EEPROM may be used.

[0050]

According to the present invention, a pseudo error pattern can be generated with a simple configuration, and various statistical information can be easily obtained, so that line tests can be easily and appropriately performed.

[Brief explanation of drawings]

[Figure 1] Principle diagram of the present invention

[Fig. 2] A block diagram showing the overall configuration of an information transmission system that is an embodiment of the present invention.

FIG. 3: In an embodiment of the present invention, a packet terminal (DT
Conceptual diagram showing the connection status between E) and the line terminating equipment (DCE)

[Fig. 4] Explanatory diagram for explaining the test method between terminals in the conventional technology

[Fig. 5] Conceptual diagram showing the connection state between packet terminals in the embodiment

[Fig. 6] Block diagram showing the structure of a data frame used in the embodiment

FIG. 7 is an explanatory diagram showing an example of the configuration of a control field in the embodiment.

FIG. 8 is an explanatory diagram showing the configuration of a shift register and a gate (judgment means) in a line testing device in an embodiment.

[
FIG. 9 is an explanatory diagram showing the element configuration for realizing the circuit shown in FIG. 8 in the example.

FIG. 10 is a timing chart diagram showing the operation timing of the line test equipment in the example.

FIG. 11 is a circuit diagram showing a clock generation circuit in an embodiment.

[Explanation of symbols]

1...1st packet terminal 2...Second packet terminal 3...Line 4. Judgment means 5. Pattern registration means 6...Line testing equipment 7. Interface section 8...Transmission line 9...Line termination device 10...AND gate 11...Inverter 110-115...PROM 120-126...Shift register 130...Latch FF 150, 151... Inverter circuit

Claims (3)

[Claims] Claim 1: In an information transmission device in which at least a first packet terminal (1) and a second packet terminal (2) are connected via a line (3), a specific bit pattern is interposed on the line (3). The line testing device (6) includes a determining means (4) for recognizing a test pattern, and a pattern registering means (5) for registering a test pattern. is the first packet terminal (1
), when it is determined that the bit pattern of the data sent from the second packet terminal (2) is a specific bit pattern, a test pattern is read from the pattern registration means (5), the data is replaced with the test pattern, and the second packet terminal (2)
A line test method characterized by output. 2. In the line testing device (6), the ROM serving as the pattern registration means (5) and the transmission data (T) from the first packet terminal 1 are transmitted at a signal instruction timing (S).
), and a gate circuit as a determination means (4) that outputs an output when an AND condition of specific bits of the shift register is satisfied, and outputs the output signal from the gate circuit to the ROM. As the address, RO
2. The line test method according to claim 1, further comprising reading a test pattern from M and transferring it to said shift register. 3. The line test method according to claim 2, wherein the test pattern is selectively transferred from the ROM to the shift register.