JPH02149973A - Address reproduction device - Google Patents

Abstract

PURPOSE:To attain appropriate address reproduction in which a reproduction course is considered and to perform the accurate reproduction of address data by providing an address data supervisory circuit. CONSTITUTION:Reproduction address data is supervised from sink data showing a synchronous position included in digital data and address data showing an address. When a difference between address data detected from digital data to which sink data showing the synchronous position and address data showing the address are added in terms of blocks and the discrete value of an address counter 5 which jogs whenever sink data is detected from digital data is less than a prescribed threshold value, it is set to be reproduction address data, and when it exceeds the threshold value, the address data supervisory circuit 6 which performs substitution is provided if it exceeds the previously decided number of blocks and it continues. Thus, address data of highest reality appropriateness can be reproduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address reproducing device used for reproducing address data in a digital VTR or the like.

[Prior Art] Digital VTRs that convert video signals into digital data and record it on magnetic tape via a rotating magnetic head use the TDM method, which compresses the color signal in the time axis and inserts it into the horizontal retrace period of the luminance signal. A method is often used in which the recording band is compressed by combining the DPCM method, which quantizes and encodes a difference signal between a predicted value and a human input value, and then transmits the signal. In the DPCM method, 1
After dividing the field image into, for example, 2550 partial areas, and dividing each divided area into 64 sample pixels in a matrix, the video data for each pixel is divided into 2 to 5 sample pixels depending on the specified mode. Sample using the number of quantization bits. The sampled video data and the mode data indicating the quantization mode are both made up of 8 bits as one symbol, and are arranged in the second row and below on the m-by-n memory map according to a certain arrangement rule. The arranged data is given an error correction code according to the matrix of the map, and then sync data indicating the synchronization position and address data indicating the address are prefixed to the 0th and 1st rows, respectively, and the data in the same column is displayed as a whole in batting order. The information is recorded on a magnetic tape while being read out in column sequence.

That is, the digital data recorded on one track of the magnetic tape is grouped into one block for each column of the memory map, and the first block is prefixed with sync data and address data A0, and the data of the subsequent first block is prefixed with sync data and address data A0. , the sync data and address data A+ are prefixed, and so on up to the nth block of data An, with the sync data and address data at the beginning, respectively, and are recorded in alignment in the scanning direction of the rotating magnetic head. On the other hand, in a playback system that plays back digital data, it is important to accurately play back each block of data. The effects on playback quality cannot be overlooked, such as vibration and distortion of the playback waveform due to jitter. In addition, if a reading error occurs not only for sync data but also for address data, it becomes impossible to identify the code sequence of the error correction code that should be decoded according to the same code sequence as when recording, and the correction capacity used in the recording system becomes impossible. There is a risk that an error correction code with a high error correction code will become useless, so a sync data reproducing device and an address reproducing device that determine the origin of data reproduction are required to have sufficient reproduction accuracy.

[Problems to be Solved by the Invention] A conventional address reproducing device is configured to generate an address clock based on sync data included in reproduced digital data and detect address data according to the generated address clock. Since the address data that was created is used as the reproduced address data,
Problems may occur where the detected address data deviates significantly from the count value of the sync data due to reading errors, etc., and it is difficult to decode error correction codes that identify code sequences based on reproduced address data with a certain level of accuracy. The problem was that there were cases where the guarantee could no longer be guaranteed.

[Means for Solving the Problems] The present invention solves the above problems, and provides an address for detecting address data from digital data to which sync data indicating a synchronization position and address data indicating an address are attached in blocks. a data detection circuit; an address counter that detects sync data from the digital data and increments a count value each time; The counted value of the address counter is replaced with the detected address data as the reproduced address data, and if the difference exceeds the threshold, the replacement is interrupted and the counted value of the address counter is adopted as the reproduced address data, but the number of times this adoption is The present invention is characterized by comprising an address data monitoring circuit that executes the replacement when a predetermined number of blocks are consecutively exceeded.

[Operation] This invention provides address data that is detected from digital data to which sync data indicating a synchronization position and address data indicating an address are attached in block units, and an address that is incremented each time sync data is detected from the digital data. If the difference with the count value of the counter is less than a predetermined threshold,
The counted value of the address counter is replaced with the detected address data as the reproduced address data, and if the difference exceeds the threshold, the replacement is interrupted and the counted value of the address counter is adopted as the reproduced address data. If the number of consecutive blocks exceeds the predetermined number, replacement is performed to reproduce the most realistic address data based on the detected sync data and address data.

[Example] Hereinafter, an example of the present invention will be described with reference to FIGS. 1 to 3. Figures 1 and 2 are circuit diagrams and signal waveform diagrams of various parts of the circuit, respectively, showing an embodiment of the address reproducing device of the present invention, and Figure 3 explains the operation of the address data monitoring circuit shown in Figure 1. This is a flowchart for

In FIG. 1, the address reproducing device 1 reproduces address data from digital data to which sync data indicating a synchronization position and address data indicating an address are attached in blocks, in accordance with the conditions shown below. The reproduction operation timing is based on the clock generated by the clock generation circuit 2.
controlled by Based on the sync data separated by the synchronization separation circuit 3, the clock generation circuit 2 generates first and second address clocks CKI and CK2 that time-divide the address data period shown in FIG. , a field clock CK3 is generated at the field period.

4 is an address data detection circuit that detects address data from digital data, and is composed of a D flip-flop circuit that latches digital data in response to a first address clock CKI.

Reference numeral 5 denotes an address counter, which is supplied with the second address clock GK2 from the clock generation circuit 2, increments the count value each time, and is cleared by the field clock CK3. Moreover, this address counter 5 is
When receiving a low level load input from an address data monitoring circuit 6, which will be described later, the detected address data supplied to the data input terminal is loaded.

The address data monitoring circuit 6 includes a subtraction circuit 7 that calculates the difference between the count value of the address counter 5 and the detected address data;
It has an absolute value circuit 8 which takes the absolute value of the subtraction output of the subtraction circuit 7 and outputs data indicating that this absolute value is less than or equal to a predetermined threshold value N or data indicating that the absolute value exceeds the threshold value N.

A counter 9 counts data indicating that the absolute value exceeds N, and outputs data indicating this when the counted value exceeds N. The output of the counter 9 and the data indicating that the absolute value is less than or equal to N are:
It is sent to the latch circuit 11 and address counter 5 via the NOR gate circuit IO. The latch circuit 11 is composed of a D flip-flop circuit that latches the output of the NOR gate circuit 10 using the second address clock, and supplies the latch output to the clear input terminal of the counter 9.

The address counter 5 is loaded with the detected address data supplied to the data input terminal when the load input terminal receives a low level load input, thereby replacing the counted value with the detected address data. The detection-address data used for this replacement is the address data latched by the address data detection circuit 4 by the first address clock CKI immediately before the replacement, and at the same time as the replacement, the address counter 5 receives the second address clock CK2. Therefore, the replaced address data immediately increases the count value by I.

By the way, when the difference between the count value of the address counter 5 and the detected address data is equal to or less than N, the NOR gate circuit 10 in the address data monitoring circuit 6 becomes at a high level when only one of the two manual inputs is input.

Therefore, the low level output of the NOR gate circuit 10 is supplied to the load input terminal of the address counter 5. As a result, the address counter 5 replaces the previous count value with the address data sent from the address data detection circuit 4, and the new count value obtained by adding 1 to this address data becomes the reproduced address data. It is said that In addition,
The operations up to this point correspond to step 4 from step (101) to step (104) in FIG.

On the other hand, if the difference between the count value of the address counter 5 and the detected address data exceeds N, the NOR gate circuit 10
Since both human power is low level, it is a Noah gate circuit!
A high level output of 0 is sent to the load input terminal of the address counter 5. Therefore, in this case, the address counter 5 interrupts the replacement and starts the second address clock CK.
2 and increments the count value. Up to this point, the operations are shown in steps (105) to (107), but since the latch circuit 11 latches high-level data, the counted value of the counter 9 is not cleared, and the number of times the difference exceeds N. Enter the count.

When the count value of the counter 9 reaches or exceeds , the output of the counter 9 becomes high level, as shown in step (108) following step (105), and the low level output of the NOR gate circuit 10 is addressed as a load input. It is supplied to the counter 5. As a result, address protection by the above-mentioned substitution is performed. That is, here, the detected address data that should originally be the reproduced address data is adopted, assuming that the temporary data jump that occurred in the detected address data has left its tail. In addition, the latch circuit!
When the counter 9 receives the low level output of l, its count value is cleared.

In this way, the address reproducing device I monitors the reproduced address data from the sync data indicating the synchronization position included in the digital data and the address data indicating the address, and is capable of reproducing address data with the highest practical validity. This is particularly effective for address reproduction in digital reproduction equipment, where accurate reproduction of address data is essential for specifying an error correction code sequence.

[Effects of the Invention] As explained above, the present invention monitors playback address data from sync data indicating a synchronization position and address data indicating an address included in digital data, and calculates the detected address data and the address counter. If the numerical values are accompanied by a distance less than a predetermined threshold, the detected address data is trusted and adopted, and if the detected address data is too far from the count value of the address counter,
By using the count value of the address counter, detection errors can be avoided, and if the above number of times of use continues beyond the predetermined number of blocks, a temporary data jump that occurred in the detected address data can be detected. Gaoori 1
However, by adopting detected address data that should originally be reproduced address data, it is possible to perform appropriate address reproduction from a realistic perspective that takes into account the reproduction progress, and this will prevent accurate reproduction of address data from being erroneous. It has excellent effects such as being particularly effective for address reproduction in digital reproduction equipment, etc., which is indispensable for specifying correction code sequences.

[Brief explanation of the drawing]

Figures 1.2 and 3 are a circuit diagram and signal waveform diagrams of various parts of the circuit, respectively, showing one embodiment of the address reproducing device of the present invention.
FIG. 1 is a flowchart for explaining the operation of the address data monitoring circuit shown in FIG. ! 19. Address reproducing device, 4. ．． ．． Address data detection circuit, 5. ,,Address counter, 6° address data monitoring circuit. Figure 3

Claims (1)

[Claims] An address data detection circuit detects address data from digital data to which sync data indicating a synchronized position and address data indicating an address are attached in blocks, and detects sync data from the digital data and increments a count value each time. If the difference between the count value of this address counter and the detected address data is less than a predetermined threshold, the count value of the address counter is replaced with the detected address data as reproduced address data, and the difference exceeds the threshold. If the number of blocks exceeds the predetermined number of blocks, the address data monitoring circuit interrupts the replacement and adopts the counted value of the address counter as the reproduced address data. An address reproducing device comprising: