JPH02149012A - Schmitt trigger circuit - Google Patents

Abstract

PURPOSE:To generate a Schmitt trigger at the output terminal of a latch circuit so as to facilitate the design of a circuit by inputting the outputs of two pieces of the buffers or the inverters of different switching levels to a NAND gate and an OR gate respectively, and inputting the outputs of those to the latch circuit. CONSTITUTION:When input voltage is increased gradually, since the outputs of the respective buffers 1, 2 are Low at the voltage below the switching level VT- of the buffer 2, the output of the NAND gate 3 becomes High, the output of the OR gate becomes Low, and the output of the latch circuit becomes High. The input voltage is increased further, and in the range of VT-<VIN<VT+, since the output of the buffer 2 is High, and output Vout of this circuit is left as it is High. When the input voltage is increased further, and it becomes over VT+, since both the outputs of the buffers 1, 2 become High, the output Vout of this circuit is turned into Low. As stated above, the switching levels VT+, VT- and the Schmitt width DELTAVT of the whole Schmitt circuit are determined by only the switching levels of the buffer or the inverter.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a Schmitt trigger circuit whose switching level can be easily set.

Conventional technology A Schmitt trigger circuit is a circuit in which when the input voltage is changed, the output voltage does not change above a certain voltage, but when that voltage (hereinafter referred to as the switching level) is exceeded, the output voltage changes. Since the switching level has different hysteresis characteristics when the input voltage is increased and decreased, it has the advantage of being resistant to input signal noise.

FIG. 3 shows a Schmitt trigger circuit conventionally used to generate such a Schmitt trigger.

In FIG. 3, a Schmitt trigger is obtained by connecting inverters 1, 2, and 3 in series and applying feedback from the output side of inverter 2 to the input side via inverter 4.

The operation of the conventional Schmitt trigger circuit configured as described above will be explained below.

FIG. 4 shows the logic circuit of FIG. 3 rewritten as a transistor circuit. In FIG. 4, when the input voltage is increased, the output voltage changes at a voltage (VT+) higher than the switching level (VT) when only one stage of inverter is used. The switching level (VT+) at this time depends on the transistor sizes of the P-channel transistors la and 4a and the N-channel transistor 1b. Conversely, when the input voltage is decreased, the output voltage changes at a voltage (Vy-) lower than vr due to the action of the N-channel transistors lb and 4b and the P-channel transistor 1a. The waveform of the output voltage with respect to the input voltage at this time is shown in FIG.

Problems to be Solved by the Invention However, since the conventional configuration described above includes a feedback system, the switching level cannot be easily designed, and is generally designed using a circuit simulator. In other words, it has the disadvantage that a complicated design process is required in which circuit simulation is performed when determining the transistor size so that the switching level is at the designed value.

The present invention solves the above conventional problems and aims to provide a Schmitt trigger circuit whose switching level can be easily designed.

Means for Solving the Problems To achieve this object, the Schmitt trigger circuit of the present invention inputs the outputs of two buffers or inverters with different switching levels to a NAND gate and an OR gate, It has a configuration in which a Schmitt trigger is generated at the output terminal of the latch circuit by inputting it into the latch circuit.

Operation: With this configuration, it is possible to generate a Schmitt trigger that changes with hysteresis characteristics at the switching level of the buffer or inverter.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. In this embodiment, the input section will be explained using a buffer, but similar effects can be achieved even when an inverter is used.

FIG. 1 shows a logic circuit diagram of a Schmitt trigger circuit in one embodiment of the present invention. 1 is the switching level v
T+ buffer, 2 is a switching level vT- buffer. NAND the outputs of these buffers 1.2
Connect gate 3 and OR gate 6 and NAND the output
A latch circuit consisting of gates 4 and 5 is input.

The operation of the Schmitt trigger circuit configured as above will be explained below.

In FIG. 1, when the input voltage is increased and the voltage is below the switching level of buffer 2, the output of each buffer 1.2 is Lo-, so the NAND gate 3
The output of the OR gate becomes Low, and the output of the latch circuit becomes lligh. When the input voltage further increases and in the range VT-<VIN<T+, the output of the buffer 1 is Low, and the output of the buffer 2 is the old GH, so the output Vout of this circuit remains tlight.

When the input voltage is further increased to VT10 or more, the outputs of buffers 1 and 2 both become High, so the output Vout of this circuit changes to Low. The same applies to the case where the input voltage is decreased. The waveform of the output voltage with respect to the input voltage at this time is shown in FIG.

As described above, according to this embodiment, the switching levels V7+, V7- and the Schmitt width ΔVT of the entire Schmitt circuit are determined only by the switching level of the buffer or inverter, so the Schmitt circuit can be designed very easily. . Furthermore, even when VDD is changed, the switching level and Schmitt width can be easily calculated.

Effects of the Invention As described above, the present invention allows the switching levels ■T+ and vT- of the entire circuit to be determined only by the input switching level of the buffer or inverter, and furthermore, the Schmitt width can be easily calculated by V7+-Vy-=ΔvT. This provides a Schmitt trigger circuit that can be easily designed, and is much easier to design than conventional designs using circuit simulators. Furthermore, even when VOO is changed, the switching level and Schmitt width can be easily calculated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a Schmitt trigger circuit according to an embodiment of the present invention, FIG. 2 is an input terminal versus output voltage waveform diagram of the same embodiment, and FIG. 3 is a block diagram of a conventional Schmitt trigger circuit. FIG. 4 is a circuit diagram representing FIG. 3 at a transistor level, and FIG. 5 is a waveform diagram of input voltage versus output voltage in a conventional example. 1.2...Buffer, 3...NAND
Gate, 4.5... NA forming the latch circuit
ND gate, 6...OR gate. 61-O scale gate I~4-11 inverter

Claims (1)

[Claims] By inputting the outputs of two buffers or inverters with different switching levels to each input terminal of a NAND gate and an OR gate, and inputting the outputs of the NAND gate and OR gate to a latch circuit, the output terminal of the latch circuit is A Schmitt trigger circuit is characterized in that it generates a Schmitt trigger.