JPH03198160A - Logical simulator and logical simulation method - Google Patents

Abstract

PURPOSE:To perform the timing check for precharging of a dynamic circuit by providing an action model of the logical simulation corresponding to the dynamic circuit. CONSTITUTION:When a precharge signal is kept turned on, the values of input signals A and B are stored in the storage parts 5A and 5B respectively. Then the comparison parts 6A and 6B compare the values of signals A and B obtained with the signal kept turned off with the values of signals A and B stored in the parts 5A and 5B. When the coincidence is obtained between both values, these coincident values are outputted to a logical arithmetic part 4 from the parts 6A and 6B. Meanwhile an unfixed signal is outputted to the part 4 if no coincidence is obtained through the preceding comparison. The part 4 performs an operation equivalent to a static 2-input NAND circuit when both input signals I1 and I2 are equal to 0 or 1. Furthermore the part 4 has a function to output an unfixed arithmetic result if at least one of both signals I1 and I2 is equal to an unfixed signal. Thus the timing check is attained for precharging.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a logic simulator and a logic simulation method for functionally verifying a logic circuit, and particularly to a logic simulator and a logic simulation method for verifying the timing of a logic circuit having a dynamic circuit. Regarding.

[Conventional technology]

Conventional logic simulators of this type do not have a logic simulation behavior model compatible with dynamic circuits. Therefore, when performing a logic simulation of a logic circuit composed of dynamic circuits, the following two methods can be considered.

The first method is to describe the connection information of a dynamic circuit at the level of transistors such as transfer gates, and the second method is to describe the dynamic circuit using a static equivalent model.

Figure 5 shows a dynamic NA to explain a conventional example.
FIG. 2 is a circuit diagram in which an ND circuit is implemented using MOSFETs.

As shown in FIG. 5, this dynamic circuit 8 consists of a P-channel MO whose gate is driven by a precharge signal φ.
SFET9 and N-channel MO8FETIOC and N-channel MO3F whose gates are driven by input signals A and B
ETIOA and 10B are connected in series between power supply 11 and ground, and output signal O is taken out from the connection point of P-channel MOSFET 9 and N-channel MO3FETIOA.

The logical operation of the dynamic circuit 8 having such a configuration is as follows:
As shown in the table.

In the logic operation described above, the signals A and B are assumed to have a value of 1°0, but the output value of the logic simulation may be undefined (X). In Table 1, dc represents DON'T CARE, that is, a state in which the corresponding signal has no effect on the output result, regardless of whether it has a value of 0 or 1.

Next, the operation of the dynamic circuit 8 shown in FIG. 5 will be explained in detail.

First, when the precharge signal φ is 0, the input signals A and B
Regardless of the value of , 1 is always output to the output terminal O. Further, when the precharge signal φ is 1, the result of performing a NAND operation on the values of A and B is output to the terminal O.

On the other hand, if Tr is the delay time when the signal value changes from 0 to 1, and Tf is the delay time when the signal value changes from 1 to 0, then in general, Tr>Tf. Are known. Such a dynamic circuit reduces the delay time of the entire circuit by setting the output signal to 1 (precharging) until the values of input signals A and B are determined.
It has the advantage of being able to be pressed down with a 3D speed, which is convenient for speeding up the circuit. However, it must be guaranteed that the values of input signals A and B are fixed while the precharge signal φ is 0 (setup time) and that the values of A and B do not change while φ is 1 (hold time). Otherwise, it may cause the circuit to malfunction.

Next, the number of simulations performed in such a logic simulator will be explained.

Assuming that n dynamic NAND circuits with the same precharge signal are used in a certain circuit, and the total number of input bins of the NAND circuit is m, such a logic simulator uses (3n+m) elements. need to be simulated. In other words, the precharge MOSFET is 2n in total for P channel and N channel.
m N-channel MOSFETs receiving input signals,
Furthermore, P channel MOSFET and N channel MOSFET
Since both outputs collide at the contact point (DC separation point) where T is connected, n contact elements are required.

For example, when a three-man power, four-output decoder circuit is configured with four dynamic NAND circuits, and the total number of input pins of the NAND circuits is nine, it is necessary to simulate a total of 21 elements.

[Problem to be solved by the invention]

The conventional logic simulators and logic simulation methods described above either describe the connection information of the dynamic circuit at the transistor (transfer gate, etc.) level or describe the dynamic circuit using a static equivalent model in order to perform the logic simulation of the dynamic circuit. Either method is adopted.

The former method has the disadvantage that the load on the simulator increases because the number of elements increases.

Furthermore, in the latter method, a dynamic NAND gate is described as a static NAND gate. At this time, since there is no precharge signal φ in the static NAND gate, it is necessary to check whether the values of the input signals A and H, which were determined when φ-0, have changed after reaching φ-1. The disadvantage is that it is virtually impossible to check.

It is an object of the present invention to provide a logic simulator and a logic simulation method that reduce the increase in the burden of simulation and also enable verification of whether the input signal value determined at the setup time is maintained during the hold time. Our goal is to provide the following.

[Means to solve the problem]

The logic simulator of the present invention compares the value of the input signal and the value of the storage unit with a plurality of storage units that store the value of each input signal and output the stored value when the precharge signal is on. The input signal checking section includes a plurality of comparison sections, and an arithmetic processing section that performs arithmetic processing on each comparison section output of the input signal checking section.

Further, the logic simulation method of the present invention has a logic simulation operation model compatible with a dynamic type circuit, stores the value of the input signal when the precharge signal is on, and stores the value of the input signal when the precharge signal is off. It has a function to compare the value of the input signal when the precharge signal is on with the previously stored value of the input signal when the precharge signal is on, and the value of the input signal when the precharge signal is on. The device is configured to output the result of performing a specific operation on the value when the precharge signal is off.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a logic simulator circuit for explaining one embodiment of the present invention.

As shown in FIG. 1, the logic simulator of this embodiment is
It has an operational model of a logic simulator for dynamic circuits and checks precharge timing. The operational model for such logic simulation is the input signal A.

A dynamic type NA consisting of an input signal check section for checking B using a precharge signal φ, and a logic operation section for calculating the output of this input signal check section.
Realized by ND circuit 1, this dynamic NAN
The output of the D circuit 1 is inverted by the inverter circuit 2 and output from the output terminal ○.

FIG. 2 is a block diagram of the dynamic NAND circuit shown in FIG. 1.

As shown in FIG. 2, the input signal check section 3 constituting the dynamic NAND circuit 1 checks the input signals A and B.
A storage unit 5A that temporarily stores.

5B, and the output and input signal A of the storage units 5A and 5B.
, B, and comparing units 6A and 6B. First, the values of the input signals A and B when the precharge signal φ is ON are stored in the storage sections 5A and 5B. Next, the values of the input signals A and B when the precharge signal φ is OFF. and the precharge signal φ previously stored in the storage units 5A and 5B.
The comparison unit 6A compares the values of the input signals A and B when is ON.

Compare with 6B. If both values match, the value is output from the comparison units 6A and 6B to the logic operation unit 4. Also,
If they do not match, an undefined (X) signal is output to the logic operation section 4.

The operation of the storage unit (5A) described above is as shown in the logical operation section of Table 2. That is, when the precharge signal φ is O, the output Q becomes QN-1 in the state, and the signal φ
When is 1, the value of A is output to the output Q. Note that the operation of the storage section (5B) is also similar to the operation of the storage section (5A) described above.

Further, the operation of the comparison section (6A) is as shown in the logical operation section of Table 3. That is, if the values of the comparator forces A and Q match, that value is output as Il, and if they differ, undefined (X) is outputted as Il. Note that the operation of the comparison section (6B) is also similar to that of the comparison section (6A).

Table 3 On the other hand, the logic operation unit 4 performs a specific logic operation on the signal output from the input signal check unit 3. As shown in the logic operation section in Table 4, this logic operation unit 4 performs an operation equivalent to a static type two-man NAND circuit when the values of the input signals 11 and I2 are O or 1.
At least one of input signals 11 and I2 is undefined (X)
If it is a signal, it has the function of outputting an undefined value as a calculation result. The result of the operation in the logic operation section 4 becomes the output of the operation model 0.

Furthermore, the operation of the above-mentioned logic simulator will be specifically explained.

When the precharge signal φ is 0, the input signal A.

Assume that the value of B is determined and then the precharge signal φ changes to 1. When the values of A and H are inverted while φ is 1, the comparison unit 6
The output values of A and 6B are undefined (X), resulting in the output O
The value of (the result of the logic operation unit 4) is also undefined (X). Conversely, if the values of A and B are not inverted while φ is 1, the comparison unit 6
Since the values of A and 6B are output as they are of the input signals A and B, the simulation is executed correctly.

That is, when performing a logic simulation of a circuit constituted by a dynamic circuit by using the operational model of this embodiment, the values of input signals A and B when the precharge signal φ is ON are used as the precharge signal φ. is OFF
Verification as to whether or not the data is retained even after the change is made possible can be determined based on whether or not the simulation result becomes indeterminate (X).

In addition, the above-mentioned input signal checking unit 3 specifically includes:
Two inverter circuits provided for each input and a MOS transistor that forms a transfer gate connected between the two inverter circuits form a storage section, and a comparison section is formed using a contact element function that logic simulators generally have. At the same time, the precharge signal φ is connected to the Mo
It is configured by supplying it to the gate of an S transistor.

According to the logic simulator of this embodiment, n dynamic NAND circuits having the same precharge signal are used in a certain circuit, and if the number of input signals to the entire circuit is one, then (n+2) i) elements will be simulated. That is, there are i storage units, i comparison units, and n logic operation units.

Here, when comparing the simulation number of this embodiment with the number of the conventional example described above, it is found that, in general, as n becomes larger, the relationship between the total number of input bins m of the NAND circuit and the number i of input signals to the entire circuit becomes m >> There is a tendency that i. Therefore, dynamic NA with the same precharge signal
As the number n of ND circuits increases, the simulation efficiency is improved by approximately three times.

FIG. 3 is a configuration diagram of a dynamic NAND circuit for explaining a second embodiment of the present invention.

As shown in FIG. 3, this embodiment uses a dynamic NA
Three-person power (A to C) consisting of ND circuit IA (C)
This is an example applied to the decoder circuits of )1 to 04). This dynamic type NAND circuit IA includes an input signal check section 3A that checks input signals A to C, and logic operation sections 4A to 4C that calculate the output of this input signal check section 3A.
and a logic operation section 7. Here, the logic operation units 4A to 4C and 7 perform the same logic operations as those described in the logic operation table in Table 4 above.

That is, when the input signal is O or 1, the three-input logic operation sections 4A to 4C and the three-input logic operation section 7 operate as a static two-person NAND circuit and a three-input logic operation section, respectively. However, both have a function of outputting undefined (X) when at least one of the input signals is undefined (X).

FIG. 4 is a block diagram of the input signal check section shown in FIG. 3.

As shown in FIG. 4, the input signal checking section 3A includes storage sections 5A to 5C that store input signals 11 to 3 and are controlled by a precharge signal P, and input signals 11 to I.
3 and comparison units 6A to 6C that compare signals stored in storage units 5A to 5C. Further, these storage units 5A to 5C and comparison units 6A to 6C also perform the same logic operations as those described in the logic operation tables of Tables 2 and 3, respectively.

As described above, according to this embodiment, whereas conventional logic simulators process 21 elements, a total of 3 storage sections, 3 comparison sections, and 4 logic operation sections are processed. Since only 10 elements are required, the simulation efficiency is improved by more than twice.

Furthermore, even if a plurality of dynamic circuits exist, if the precharge signals are the same, the number of storage sections and comparison sections required is the same as the number of input signals for the entire circuit.

〔Effect of the invention〕

As described above, the logic simulator and logic simulation method of the present invention have the advantage of being able to perform precharge timing checks in dynamic circuits by providing a logic simulation behavior model compatible with dynamic circuits.

Furthermore, by using a logic simulation operation model compatible with dynamic type circuits, the present invention can share an input signal check section in dynamic type circuits having the same precharge signal. Therefore, even if there are multiple dynamic circuits with the same precharge signal, the number of elements simulated by the logic simulator will not increase significantly, so the simulation speed will be faster than that of conventional logic simulators. It has the effect of improving.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a logic simulator circuit for explaining the first embodiment of the present invention, FIG. 2 is a block diagram of the dynamic NAND circuit shown in FIG. 1, and FIG. A configuration diagram of a dynamic NAND circuit for explaining an embodiment, FIG. 4 is a configuration diagram of the input signal check section shown in FIG. 3, and FIG. 5 is a configuration diagram of a dynamic NAND circuit for explaining a conventional example using MOSFET. FIG. 1, IA...dynamic NAND circuit, 2...
Inverter circuit, 3,3A...input signal check section,
4,4A~4C17...Logic operation section, 5A~5C...
・Storage unit, 6A to 6C... Comparison unit, φ... Precharge signal, A to C... Input signal, 0.01 to 04...
・Output signal

Claims (2)

[Claims] (1) A plurality of storage sections that store the value of each input signal and output the stored value when the precharge signal is on, and a plurality of comparisons that compare the value of the input signal and the value of the storage section. 1. A logic simulator comprising: an input signal check section having an input signal check section; and an arithmetic processing section that performs arithmetic processing on outputs of each comparison section of the input signal check section. (2) It has a logical simulation operation model compatible with dynamic type circuits, stores the value of the input signal when the precharge signal is on, and stores the input signal value when the precharge signal is off. It has a function of comparing the value of the input signal with the previously stored value of the input signal when the precharge signal is on, and performs a specific operation on the value of the input signal when the precharge signal is on. A logic simulation method characterized in that the result is output when the precharge signal is off.