JPH0877240A - Logical simulation method for lsi - Google Patents

Abstract

PURPOSE: To perform high-precision logical simulation matching a circuit simulation result in a short time with a small number of parameters by calculating the delay time required for the output voltage value of a CMOS gate to vary as specified on the basis of specific conditions. CONSTITUTION: Output load capacity CL and an input transition time TTi are given and the delay time (t) required for the output voltage value of the CMOS gate to reach V0 is calculated from an equation with a small number of parameters. Here, VTH is the threshold value of a MOS transistor(TR), a is the gradient of ln1IDS and ln1VGS-VTH1, and β is the utilization coefficient of the MOS TR. For the equation, a value which is closer to that of an actual device is used as the gradient of the drain current and gate voltage of the MOS TR in consideration of the input transition time TTi. Consequently, the high-precision simulation well matching the circuit simulation result can be performed in a short time with a small number of parameters.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LSI logic simulation method using CMOS gates, and more particularly to a MOS gate delay time calculation method.

[0002]

2. Description of the Related Art Conventionally, as an LSI design support tool, a device simulator for supporting process design of devices such as transistors and device design work, and operation verification of a relatively small-scale circuit configured by combining devices are performed in an analog manner. Circuit simulator for performing the same, and a logic simulator (including timing simulator) used to perform timing verification for LSI-scale logic circuit design, layout design, and mask design that combines multiple circuits that can be verified by the circuit simulator , There is a functional simulator that designs the logic of large-scale logic circuits using functional blocks that are larger than the circuit scale handled by the logic simulator.

Each of the above simulators has ...
The gate size to be verified becomes larger in this order. If the gate size to be verified is small, it is possible to easily perform high-precision characteristic verification at the input / output waveform transition level, but this becomes difficult as the gate size becomes larger, and the delay time per unit gate is calculated. The need to shorten

As a method of calculating the delay time TD of the CMOS transistor when the logic and timing of the CMOS LSI are verified by the logic simulator, firstly, there is a method using the following formula. TD = A + B × CL where A and B are constants and CL is the output load capacitance.

The output load capacitance is the total load capacitance up to the next block of the gate output end to be verified. The longer the wiring length, the more the number of gates in the next stage (that is, the number of fanouts).
The larger the number, the larger the value. The constants A and B are determined based on the data of the plurality of output load capacitances CL so that this calculation formula is closer to the circuit simulation result (which can be regarded as the operating characteristics of the actual device). The values of the determined constants A and B are used as cell parameters
Registered in the library.

As a second method for calculating the CMOS transistor delay time in the logic simulator, a method of dividing the circuit simulation result into a plurality of regions and performing linear approximation between them is also used. According to this method, the delay time TD that changes depending on the output load capacitance CL and the input transition time TTi can be matched well with the circuit simulation result.

[0007]

The above-mentioned first method has an advantage that the calculation is simple, but has a problem that there is a large error from the characteristics of the actual device. this is,
This is because the calculation formula is a simple linear approximation and the input transition time is not taken into consideration. In recent LSIs with higher integration and higher speed, the influence of waveform blunting due to output load is becoming more and more serious, and the first method cannot sufficiently cope with this. The second method can obtain a highly accurate delay time by increasing the number of divisions, but has a drawback in that the amount of parameters to be stored increases as the accuracy increases. Further, it is not realistic to use the delay time calculation method used for the circuit simulation as it is in the logic simulation because the number of parameters is large.

The present invention has been made in view of the above points, and an object of the present invention is to provide a logic simulation method capable of calculating delay characteristics of a CMOS gate that well matches a circuit simulation result with a small number of parameters. There is.

[0009]

The present invention is firstly directed to C
A method of logic simulation of an LSI configured using MOS gates is characterized in that a delay time t until the output voltage value of the CMOS gate changes by Vo is calculated based on the following expression 1.

[0010]

[Equation 1]

In the equation 1, CL is the output load capacitance, TTi is the input transition time, VTH is the threshold value of the MOS transistor, α is the slope of lnIDS and ln│VGS-VTH│, and β is the gain coefficient of the MOS transistor.

A second aspect of the present invention is a logic simulation method for an LSI configured using CMOS gates, wherein the delay time t until the output voltage value of the CMOS gate changes by Vo is expressed by the following equation 2. It is characterized in that it is calculated based on.

[0013]

(Equation 2)

In Equation 2, CL: output load capacitance, TTi: input transition time, VTH: threshold value of MOS transistor α; slope of ln | IDS | and ln | VGS-VTH | IDSS; VDS = VGS = VDD is a saturation current value of the MOS transistor (= β (VDD-VTH) 2/2) in.

Thirdly, the present invention is a logic simulation method for an LSI constituted by using CMOS gates, wherein the delay time t until the output voltage value of the CMOS gate changes by Vo is expressed by the following mathematical expression 3. It is characterized in that it is calculated based on.

[0016]

[Equation 3]

In the equation 3, CL: output load capacitance, TTi: input transition time, VTH: threshold value of MOS transistor α; slope of ln│IDS│ and ln│VGS-VTH│ IDSS; VDS = VGS = VDD saturation current of the MOS transistor in (= β (VDD- | VTH | ) 2/2) VON; a logical threshold value of the CMOS circuit.

A fourth aspect of the present invention is an LSI logic simulation method using CMOS gates, wherein the delay time t until the output voltage value of the CMOS gate changes by Vo is expressed by the following equation 4. It is characterized in that it is calculated based on.

[0019]

[Equation 4]

In equation 4, CL: output load capacitance, TTi: input transition time, VTH: threshold value of MOS transistor α; slope of ln | IDS | and ln | VGS-VTH | IDSS; VDS = VGS = VDD MOS transistor saturation current at (= β (VDD- | VTH | ) 2/2) VON; a logical threshold value of the CMOS gate.

[0021]

In the present invention, when the output load capacitance CL and the input transition time TTi are given, a small parameter (V
TH, α, IDSS, VON) makes it possible to calculate the delay time of the CMOS gate required until the output changes by VO. Moreover, in the present invention, the α power law is applied to the drain current (IDS) -gate voltage (VGS) characteristics of the MOS transistor, that is, ln | IDS | and ln |
By using a value α closer to the actual device instead of 2 as the gradient of VGS−VTH |, it is possible to perform a highly accurate logic simulation that closely matches the circuit simulation result in a short time.

According to the second aspect of the invention, the gain coefficient β of the MOS transistor is described by the drain saturation current value IDSS under a predetermined bias condition and a simplified calculation formula is used to make the logic even easier and with a small error. Simulation becomes possible. Further, according to the third invention, a CMO
By taking into account that the logic threshold value of the S gate is different from the threshold value of the transistor alone, more accurate logic simulation becomes possible. Furthermore, the first
According to the fourth invention, which is a combination of the first invention to the third invention, it is possible to perform a highly accurate logic simulation more closely matching the circuit simulation result in a short time. Furthermore, by incorporating the above formula into a logic simulator, highly accurate timing simulation becomes possible.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. In the following description, the output fall in the CMOS inverter, that is, the output delay when the input signal rises and the NMOS transistor is turned on is mainly dealt with, and finally, the case where the input signal falls and the PMOS transistor is turned on is dealt with. Generalize including.

First, prior to the description of the embodiment of the present invention, the NMOS inverter structure of FIG.
A calculation formula generally used for calculating a delay time when the transistor is turned on will be described. The current equation of the NMOS transistor QN is expressed by the following equation 5 with the output load capacitance CL, the threshold value of the NMOS transistor VTN, and the gain coefficient βN.

[0025]

(Equation 5)

Based on this current equation, referring to FIG.
A value V with a certain output voltage considering the input transition time TTi
When the time t until reaching O is obtained, the following equation 6 is obtained.

[0027]

(Equation 6)

As shown in FIG. 2, when the delay time TD is defined from the point where the input voltage is VDD / 2 to the point where the output voltage is VDD / 2, VO = VDD / 2 is substituted into Equation 6 and By subtracting TTi / 2 from the result, the formula of the delay time TD shown in Expression 7 is obtained.

[0029]

(Equation 7)

When applied to an actual timing simulator, the delay time TD obtained by the equation 7
It is necessary to calculate the output transition time TTo. The output transition time TTo is obtained, for example, as shown in FIG. 3, by linearly approximating two points of the output voltage waveform at 0.8 VDD and 0.2 VDD, and this is directly input to the gate of the next stage. The transition time becomes TTi.

Substituting a concrete numerical value into the equation 7, the delay time T
The result of calculating D is shown by a broken line in FIG. 5 together with the circuit simulation result (dashed line). From this result, MO
It is clear from Equation 7 that only the current formula of the S transistor is solved that a large error occurs when it is applied to the logic simulation of the actual CMOS gate.

Various causes can be considered, but the following points have a great influence according to the consideration of the present inventors. (A) Due to the progress of miniaturization technology and the improvement of transistor performance, the characteristics of the actual device no longer match the conventional current equation. (B) When a gate based on a CMOS inverter is formed, the circuit threshold value is different from the threshold value of the MOS transistor alone.

Therefore, in the present invention, in order to mainly reduce the error caused by the above (a), (1) the α power law is applied to bring the transistor current equation close to the actual device characteristic, and (2) the gain The coefficient β N is described by the saturation current value IDSN to simplify the formula. Furthermore, in order to reduce the error due to the cause of (b), (3) the circuit threshold of the CMOS gate is introduced. Hereinafter, these improvements will be sequentially described.

(1) Application of α power law The α power law is the drain current IDS of the NMOS transistor.
-It means that the gate voltage VGS characteristic is generally expressed by the following equation 8.

[0035]

[Equation 8]

As a reference for the α-law, for example, "CMOS VLSI design" supervised by Takuo Sugano (Baifukan,
1989). That is, although α = 2 is used in the above Equation 5, this does not match the actual state in recent fine real devices, and to match the actual device, for example, use the optimum α according to the circuit simulation result. Is needed. Therefore, in the present invention, the essence is to use the equation 9 in which α is introduced in place of the above equation 6.

[0037]

[Equation 9]

When the equation of the delay time TD is obtained based on the equation (9) instead of the equation (7), the equation (10) is obtained.

[0039]

[Equation 10]

Actually, the circuit simulation results have revealed that the calculation by the equations 9 and 10 is performed using α = 1.3, which is in good agreement with the circuit simulation.

(2) β is described by IDSN IDSN is a saturated drain current when VDS = VGS = VDD. In calculating the delay time, it is not necessary to strictly consider the linear region, and the above-mentioned NMOS is used.
Β which is obtained from the current formula of the transistor, VGS = VD
Substituting D and IDS = IDSN, the following equation 11 is used as β.

[0042]

[Equation 11]

By rewriting the above equation 9 using this equation 11, equation 12 is obtained.

[0044]

[Equation 12]

Further, based on this equation 12, the delay time TD
The equation is

[0046]

[Equation 13]

Even when the above equations 12 and 13 are used,
Good agreement was confirmed with the circuit simulation results.

(3) Introduction of circuit threshold value VON In the case of a CMOS gate, not only the threshold value VTN of the MOS transistor but also the circuit threshold value VON is introduced.
When is rewritten, Equation 14 is obtained.

[0049]

[Equation 14]

Similarly, when the circuit threshold value VON is introduced and the equation 7 is rewritten, the equation of the delay time TD becomes the equation 15.

[0051]

(Equation 15)

Actually, for example, as the circuit threshold value VON,
A value is introduced where the input and output voltages are equal when TTi = 20 nsec and CL = 0 pF. From the circuit simulation result, VON
.Apprxeq.2 V was obtained, and the delay time calculation was carried out based on the equations (14) and (15) using this, and it was confirmed that the results closely match the circuit simulation results.

Although the above-mentioned ideas (1), (2) and (3) can achieve a certain effect independently, by combining them, a better fitting with the circuit simulation result is possible. Become.
The formula of the delay time t which is a combination of (1), (2) and (3) is the following Expression 16.

[0054]

[Equation 16]

Similarly, the equation of the delay time TD which is a combination of (1), (2) and (3) is given by the following equation (17).

[0056]

[Equation 17]

The fitting parameters in the above equations 16 and 17 are only VON, α and IDSN, and these can be obtained by a simple simulation. Further, the circuit threshold value VON has to be obtained for each cell, but since α and IDSN are the characteristics of the MOS transistor, it is only necessary to obtain the value for the MOS transistor of a predetermined type. Specifically, the delay time TD calculated based on Expression 17 is shown by a solid line in FIG.
It can be seen that a result extremely close to the result of the circuit simulation is obtained as compared with the result of the above-mentioned equation 7.

An example in which the delay time calculation method according to the present invention is specifically applied to a timing simulator is shown in FIG. 6 in comparison with a conventional example. As shown, cells (i), (j),
When (k), ... Are cascade-connected, in the conventional method,
As shown in (a), for each cell, the output load capacity CL
The timing was verified by calculating the delay time using only. On the other hand, in the present invention, in the embodiment of (b),
The delay time is calculated by considering the output transition time of the previous cell as the input transition times TTi, TTj, and TTk of the next cell together with the output load capacitance CL. In the example of (c), the input transition time is taken into consideration, but the calculation is simplified by setting this constant TTi0.

When the present invention is applied to a cell in which a signal internally passes through two stages of gates such as a buffer and an AND, characteristics can be obtained by substituting the result of the first stage into the second stage. In the case of a cell that passes through three or more stages of gates such as a flip-flop, it is considered that the input transition time dependency is substantially determined by the first stage MOS transistor, and the output load capacitance dependency or the final stage MOS transistor. . Therefore, if only the characteristics of the first stage and the last stage are focused and the delay between them is calculated in advance as a constant internal delay, the timing verification can be performed without causing a large error.

The delay time calculation method for a cell passing through two stages of gates will be specifically described with reference to FIG. First, for the first stage gate 1, the input transition time TTi
The delay time TD1 and the output transition time TTo1 are calculated by using, as the output capacitance, the capacitance up to the gate of the second stage up to 0.04 pF. Next obtained output transition time T
Using To1 as the input transition time of the second-stage gate 2, the delay time TD2 and the output transition time TTo2 of the second-stage gate 2 are obtained using the output load capacitance CL. From the above results, the total delay time TD = TD1 + TD2, the output transition time TT
o = TTo2 is required.

Next, the calculation method when passing through the three-stage gate will be specifically described with reference to FIG. As shown, there are Method 1 and simplified Method 2. In the method 1, the delay time and the output transition time are calculated by sequentially using the output transition time of the preceding stage as the input transition time for the gate 1 to the gate 3. In the calculation of the gates 1 and 2, the capacitance up to the next-stage gate up to 0.04 pF is used as the output capacitance. As a total, the delay time TD = TD1 + TD2 + TD3 and the output transition time TTo = TTo3 are obtained.

In the method 2, the delay time T of the second stage gate 2
D2 and the output transition time TTo2 are regarded as constant internal parameters, and the second stage gate 2 is not calculated. The method of obtaining the output transition time TTo2 of the second stage gate 2 is as follows, for example. First, the input transition time TTi
The effect of the change of 0 to 20 ns on the output transition time TTo1 is as follows.
It is estimated that TTo1 = 1 to 4 ns, assuming about 0.04 pF. The influence of the next output transition time TTo1 on the output transition time TTo2 of the next gate is similarly
It can be estimated that TTo2 = 1 to 2 ns. Therefore, it is assumed that TTo2 = 2 ns is constant.

To obtain the delay time TD2 as an internal delay in advance, for example, the following is performed. First, the entire cell is simulated with the input transition time TTi = 0 and the output capacitance CL = 0, and the delay time TD0 is obtained. Next, with respect to the gate 1, the delay time TD1 is obtained assuming that the input transition time is 0 and the output capacitance is 0.04 pF. Next, regarding the gate 3, the delay time TD3 is calculated assuming that the input transition time is 2 ns and the output capacitance is 0. TD0 = TD1 + TD2 + T
Since it is D3, TD2 = TD0-TD1-TD3 is obtained.

Up to this point, the output fall delay in the CMOS inverter shown in FIG. 1, that is, the NMOS transistor Q
Described the delay when N turns on. The output rise delay is as shown in FIG. 4 with respect to FIG. 2, and the delay when the PMOS transistor QP turns on is calculated mainly. Therefore, the gain coefficient βN for the NMOS transistor, the threshold value VTN, and the saturation current IDSN are respectively calculated as follows:
(Negative), threshold value VTP (negative), and saturation current IDSP (negative) must be replaced for rewriting.

The rewriting of the main calculation formulas will be described. First, the equation 9 to which the α-law is applied is rewritten to the following equation 18 for the rising delay. However, α is common to P and N.

[0066]

(Equation 18)

Similarly, the equation 12 in which the gain coefficient βN is replaced with the current value IDSN can be rewritten as the equation 19.

[0068]

[Formula 19]

Similarly, the number 1 in which the circuit threshold value VON is introduced
4 can be rewritten as Expression 20.

[0070]

[Equation 20]

Further, a combination of all of the above, Equation 16
In the case of the PMOS corresponding to, the equation is:

[0072]

[Equation 21]

Further, the above equations when the NMOS transistor is turned on and when the PMOS transistor is turned on are βN, │βP│ → │β│, VTN, │TTP
It can be generalized by making the substitutions: | → | TTH |, IDSN, | IDSP | → | IDSS |. That is, the following Expression 22 is obtained by generalizing Expression 9 and Expression 18.

[0074]

[Equation 22]

Similarly, by generalizing the equations 12 and 19, the following equation 23 is obtained.

[0076]

[Equation 23]

Similarly, by generalizing the equations (14) and (20), the following equation (24) is obtained.

[0078]

[Equation 24]

Similarly, by generalizing the equations 16 and 21, the following equation 25 is obtained.

[0080]

(Equation 25)

However, in the above generalization, the voltage value Vo in the equations 9, 12, 13, 16 and the like, which is the equation for calculating the output fall when the NMOS transistor is turned on, and the equations for generalizing these are given. Numbers 22, 23, 24, 25
It should be noted that the meaning of the voltage value VO at is different. That is, in the former case, the voltage value VO represents the change amount from OV (the initial value is VDD), whereas in the latter case, in the case of the NMOS, it means the change amount from the power supply VDD (the initial value is 0V).

Next, as the calculation formula according to the present invention, the formula 17 in the case of the output falling is used, and the formula corresponding to this is used for the output rising (that is, the formula for calculating the delay time TD derived from the formula 21). The results of an accuracy comparison test with a conventional linear approximation approximation formula will be described. The circuit used for the test is shown in FIG. The circuit 1 in FIG. 9A is a cell chain in which buffer (BUF) cells are cascade-connected, and the circuit 2 in FIG. 9B is a buffer, a flip-flop (FF) and a composite gate (MP).
It is a functional circuit including X). An error from the circuit simulation was obtained for the case where the intra-block wiring capacitance of 0.1 pF and the inter-block wiring capacitance of 1.0 pF were added to the output terminal of each cell.

The comparison results are shown in Table 1.

[0084]

[Table 1]

From Table 1, in the circuit 1, in the case of the conventional method, the signal rising error is 8% or less, but at the rising time, a large error of 20% occurs when the block wiring is performed. On the other hand, in the method of this embodiment, each error is within 10%. Circuit 2
In contrast, the conventional method has an error of about 10%, while the present embodiment has an error of about half of the error. Therefore, by incorporating the delay time calculation method according to the present invention into a logic simulator, a highly accurate logic simulation with a small error from the circuit simulation result becomes possible.

[0086]

As described above, according to the present invention, the input transition time is taken into consideration and the number of parameters is reduced.
The delay time of the CMOS gate required until the output reaches the predetermined value VO can be calculated, and by applying the α power law, which is closer to the actual device, to the transistor characteristic formula, it is possible to obtain a highly accurate result that matches the circuit simulation result well. The logical simulation can be performed in a short time.

[Brief description of drawings]

FIG. 1 shows a CMOS inverter.

FIG. 2 shows an output falling characteristic of a CMOS inverter.

FIG. 3 is a diagram illustrating output transition time.

FIG. 4 shows an output rising characteristic of a CMOS inverter.

FIG. 5 is delay time characteristic data showing effects of the embodiment.

FIG. 6 shows the delay time calculation method of the embodiment in comparison with the conventional method.

FIG. 7 shows a delay time calculation method in the case of multiple gates.

FIG. 8 shows a delay time calculation method in the case of multiple gates.

FIG. 9 shows a circuit used in the experiment.

[Explanation of symbols]

QN ... NMOS transistor, QP ... PMOS transistor.

Claims (4)

[Claims] 1. An LS configured by using a CMOS gate
In the logic simulation method of I, the delay time t until the output voltage value of the CMOS gate changes by Vo
Is calculated based on the following mathematical expression 1. [Equation 1] However, in the equation 1, CL: output load capacitance, TTi: input transition time, VTH: threshold value of MOS transistor α; slope of ln | IDS | and ln | VGS-VTH | β: gain coefficient of MOS transistor. 2. An LS constructed by using a CMOS gate
In the logic simulation method of I, the delay time t until the output voltage value of the CMOS gate changes by Vo
Is calculated based on the following equation 2. [Equation 2] However, in the equation 2, CL: output load capacitance, TTi: input transition time, VTH: threshold value of MOS transistor IDSS; saturation current value of MOS transistor at VDS = VGS = VDD (= β (VDD- | VTH |) ^2/2). 3. An LS constructed by using a CMOS gate
In the logic simulation method of I, the delay time t until the output voltage value of the CMOS gate changes by Vo
Is calculated based on the following mathematical formula 3. (Equation 3) However, in the equation 3, CL is the output load capacitance, TTi is the input transition time, VTH is the threshold value β of the MOS transistor, β is the gain coefficient of the MOS transistor VON, and the logic threshold value of the CMOS circuit. 4. An LS formed by using a CMOS gate
In the logic simulation method of I, the delay time t until the output voltage value of the CMOS gate changes by Vo
Is calculated based on the following equation 4. [Equation 4] However, in the equation 4, CL: output load capacitance, TTi: input transition time, VTH: threshold value of MOS transistor α; slope of ln | IDS | and ln | VGS-VTH | IDSS; MOS at VDS = VGS = VDD saturation current value of the transistor (= β (VDD-VTH) 2/2) VON; a logical threshold value of the CMOS gate.