JP2853241B2 - Semiconductor integrated circuit and method for changing clock time width - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method of changing a clock time width thereof.

2. Description of the Related Art Conventionally, in a semiconductor integrated circuit, a voltage level is made to correspond to a logical value, and a binary logic representing a logical value 0 for a low potential level and a logical value 1 for a high potential level based on a threshold voltage is used. Have been. In general, a semiconductor integrated circuit is configured by a combination of a binary logic circuit that receives one or a plurality of logical values and outputs one logical value. When a logical value propagates through a binary logic circuit of the semiconductor integrated circuit, a single-phase or multi-phase square wave clock having a fixed period is used to synchronize the propagation of the logical value.

A conventional example will be described with reference to FIG. The clock φ2 is a single-phase square wave having a constant period T. 210,220,230
Is a latch that takes in a logical value input at the rising edge of the clock φ2, temporarily stores the logical value, and outputs the logical value as it is without changing the logical value. Numerals 240 and 50 are binary logic circuits in which the input logical values are output as they are without changing the logical values, and the propagation times of the logical values are 5 * T / 6 and T / 6, respectively.

The operation of the circuit of FIG. 8 will be described below with reference to the timing chart of FIG. In FIG. 9, a, b,
c and d represent changes in the logical values at points a, b, c and d in FIG. The time t when the clock φ2 rises is set to t = 0. t =
Input logical value 1 from IN to 0. The latch 210 captures the logical value 1 when the clock φ2 rises, that is, at t = 0. The output a of the latch 210 is input to the binary logic circuit 240. The output b of the binary logic circuit 240 becomes a logic value 1 at t = 5 * T / 6, and is taken into the latch 220 at the rise of the clock φ2 at t = T. The output c of this latch 220 is 2
It is input to the value logic circuit 50. The output d of the binary logic circuit 50 becomes a logical value 1 at t = 7 * T / 6, and is taken into the latch 230 at the rise of the clock φ2 at t = 2 * T. As can be seen from FIG. 9, the propagation time of the logical value 1 from IN to OUT is 2 * T.

SUMMARY OF THE INVENTION However, in a semiconductor integrated circuit, when a binary logic circuit is changed and the propagation time of a logic value becomes longer than a clock cycle, data is not efficiently propagated at high speed. There was a point.

The binary logic circuit 240 shown in FIG. 8 is output as it is without changing the input logic value, and the propagation time of the logic value is
Assume that the binary logic circuit 40 is changed to 25 * T / 24. The circuit is shown in FIG. In FIG. 10, the clock φ2 is a single-phase square wave having a constant period T. 210,220,230
Is a latch that takes in a logical value input at the rising edge of the clock φ2, temporarily stores the logical value, and outputs the logical value as it is without changing the logical value. 40, 50, a binary logic circuit in which the input logical value is output as it is without changing the logical value, and the propagation time of the logical value is 25 * T / 24, T / 6, respectively.

Hereinafter, the operation of the circuit of FIG. 10 will be described with reference to the timing chart of FIG. In FIG. 11, a, b,
c and d represent changes in the logical values at points a, b, c and d in FIG. The time t when the clock φ2 rises is set to t = 0. t =
Input logical value 1 from IN to 0. The latch 210 captures the logical value 1 when the clock φ2 rises, that is, at t = 0. The output a of the latch 210 is input to the binary logic circuit 40. The output b of the binary logic circuit 40 becomes a logical value 1 at t = 25 * T / 24, and is taken into the latch 220 at the rise of the clock φ2 at t = 2 * T. Output c of this latch 220
Is input to the binary logic circuit 50. The output d of the binary logic circuit 50 becomes a logical value 1 at t = 13 * T / 6, and is taken into the latch 230 at the rise of the clock φ2 at t = 3 * T. First
As can be seen from FIG. 1, the propagation time of the logical value 1 from IN to OUT is 3 * T.

Conventionally, as can be seen from FIGS. 8 and 9, from IN to OU
The propagation time of a logical 1 to T was 2 * T. But,
As shown in FIGS. 10 and 11, since the propagation time 25 * T / 24 of the logic value of the binary logic circuit 40 becomes longer than the clock cycle T, the propagation time of the logic value 1 from IN to OUT is 3 * T, and the logical value is not efficiently propagated at high speed.

An object of the present invention is to provide a semiconductor integrated circuit and a clock time width changing method capable of efficiently and quickly transmitting a logic value of the semiconductor integrated circuit in view of the above problem.

Means for Solving the Problems A semiconductor integrated circuit according to the present invention comprises a first latch and a second latch, each having a different threshold voltage of a clock input;
A binary logic circuit having a propagation time greater than the clock period, an input connected to the first latch, and an output connected to the second latch, wherein the voltage of the clock is applied to the first latch; The time required to reach the threshold voltage of the second latch after one cycle of the clock after the threshold voltage is reached is longer than the propagation time of the binary logic circuit.

The clock time width changing method of the present invention has a propagation time longer than the clock period, and the input is supplied to the first latch,
A method for changing a clock time width of a semiconductor integrated circuit including a binary logic circuit having an output connected to a second latch, wherein the clock voltage reaches a threshold voltage of the large latch, The threshold voltage of the first latch and the second latch is set so that the time required to reach the threshold voltage of the second latch after one cycle of the clock is longer than the propagation time of the binary logic circuit. Is different from the first
And the threshold voltage of at least one of the second latch and the second latch is changed.

According to the semiconductor integrated circuit and the clock time width changing method of the present invention, the threshold voltage of the second latch is obtained one cycle after the clock voltage reaches the threshold voltage of the first latch. , The threshold voltage of the clock input of the first latch and the threshold voltage of the clock input of the second latch are different, so that the logic value of the semiconductor integrated circuit can be efficiently increased. It can propagate at high speed.

Embodiment (Embodiment 1) FIG. 1 shows an embodiment of a semiconductor integrated circuit according to the present invention.
This will be described with reference to FIGS. 2, 3, and 4. FIG. FIG. 1 is a circuit diagram showing an embodiment of the semiconductor integrated circuit of the present invention, FIG. 2 is a timing chart of the semiconductor integrated circuit of FIG. 1, and FIG. 3 is a clock of a single-phase triangular wave used in the present invention. FIG. 4 is a circuit diagram of two types of latches used in the present invention.

FIG. 3 shows a clock φ1 used in the present invention. In this embodiment, a description will be given using a single-phase triangular wave as a clock having different voltage levels and different time widths. Assuming that the cycle of the clock φ1 is T and the first rising time of the clock φ1 is t = 0, the voltage level V of the clock at the time t is: V = 4 * Vm * t (0 ≦ t ≦ T / 4) V = -4 * Vm * t + 2 * Vm (T / 4 <t≤T / 2) V = 0 (T / 2 <t≤T). It is assumed that V = VT1 at t = T / 6 and V = VT2 at t = T / 12.

In FIG. 1, reference numeral 20 denotes a latch shown in FIG.
Reference numerals 10 and 30 denote latches shown in FIG. FIG. 4 shows two types of latches (a) and (b) used in the present invention. In FIG. 1A, reference numeral 60 denotes a CMOS inverter to which a clock φ1 is input. Assuming that the p-channel gate length is wp and the n-channel gate length is wn in the CMOS inverter 60, wp
> Wn. When the voltage of the clock φ1 input to the CMOS inverter 60 exceeds the threshold voltage VT1, the n-channel transistor 80 is turned on. 70, 90, 100 and 110 are inverters. That is, FIG. 1A shows a CMOS inverter 60.
When the voltage of the clock φ1 input to the terminal exceeds the threshold voltage VT1, the logic value input from IN is taken in, temporarily stored, and acts as a latch for outputting directly from OUT without changing the logic value. . In FIG.
Is a CMOS inverter to which the clock φ1 is input.
The p-channel gate length is set to wp and n by the CMOS inverter 120.
Assuming that the gate length of the channel is wn, wp <wn. CMOS
When the voltage of the clock φ1 input to the inverter 120 exceeds the threshold voltage VT2, the n-channel transistor 140
Turn on. 130, 150, 160, 170 are inverters.
That is, FIG. 9B shows that when the voltage of the clock φ1 input to the CMOS inverter 120 exceeds the threshold voltage VT2,
A logical value input from N is taken in, temporarily stored, and functions as a latch for outputting from OUT without changing the logical value.

40 and 50 in FIG. 1 output the input logical value without changing it, and the propagation time of the logical value is 25
* T / 24, T / 6 binary logic circuit.

Hereinafter, the operation of the circuit of FIG. 1 will be described with reference to the timing chart of FIG. In FIG. 2, a, b,
c and d represent changes in the logical values at points a, b, c and d in FIG.

The time t when the clock φ1 rises is set to t = 0.
At t = 0, a logical value 1 is input from IN. The latch 10 captures the logical value 1 input when the voltage of the clock φ1 exceeds the threshold voltage VT2, that is, at t = T / 12. The output a of the latch 10 is input to the binary logic circuit 40. The output b of the binary logic circuit 40 becomes a logical value 1 at t = 27 * T / 24. The latch 20 captures the logical value 1 input to the latch 20 when the voltage of the input clock φ1 exceeds the threshold voltage VT1, that is, at t = 7 * T / 6. The output c of this latch 20 is 2
It is input to the value logic circuit 50. The output d of the binary logic circuit 50 becomes a logical value 1 at t = 4 * T / 3. When the voltage of the clock φ1 exceeds the threshold voltage VT2, the latch 30 captures the logical value 1 input to the latch 30. As can be seen from FIG. 2, the propagation time of the logical value 1 from IN to OUT is 25 * T / 12.

Conventionally, as can be seen from FIGS. 10 and 11, when the propagation time (25 * T / 24) of the logic value of the binary logic circuit 40 is longer than the clock period T, the logic from IN to OUT The propagation time of the value took 3 * T. When the present invention is applied to FIG. 1 including a binary logic circuit having the same propagation time and a latch having a different threshold voltage of the clock input, the output from IN to OUT
The propagation time of the logical value to is 25 * T / 12, and the logical value is efficiently and quickly propagated.

Also, in addition to the triangular wave used as an example of the clock in the first embodiment, a sine wave as shown in FIG. 5A or a sine wave as shown in FIG. A staircase waveform as shown can be used. It is apparent that similar effects can be obtained when clocks having different voltage levels and different time widths are used as multilayer clocks.

Embodiment 2 In a semiconductor integrated circuit using clocks having different voltage levels and different time widths, a method of changing the clock time width according to the present invention will be described. FIG. 6 shows a flowchart of a clock time width changing method used in the present invention.

(Step 1) Using a logic simulator or the like, all the binary logic circuits sandwiched by the latches included in the semiconductor integrated circuit are extracted, and the propagation time of the logic value of the binary logic circuit is obtained.

(Step 2) Of the binary logic circuits sandwiched by the latches,
It is determined whether the time from when the latch at the preceding stage captures the logical value to when the latch at the subsequent stage captures the logical value is greater than the propagation time of the binary logic circuit between the latches. If there is something big, go to (Step 3).
If not, go to (Step 4).

(Step 3) The threshold voltage of the preceding latch of the binary logic circuit sandwiched by the latches extracted in (Step 2) is made smaller than the threshold voltage of the subsequent latch. Then, the process returns to (Step 2).

(Step 4) The process ends.

Therefore, an embodiment of the present invention will be described with reference to FIG. In FIG. 7A, reference numeral 180a is the latch of FIG. 4A. 190 and 200 are latches shown in FIG. 4 (b). 40,
50 is output as it is without changing the input logical value, and the logical value propagation time is 25 * T / 24, T / 6, respectively.
It is a value logic circuit.

The method of changing the clock time width will be described below with reference to the flowchart of FIG.

(Step 1) The binary logic circuit 40 sandwiched between the latches 180a and 190 and the binary logic circuit 50 sandwiched between the latches 190 and 200 shown in FIG. , The propagation time of the logical value is 25 * T / 2
4. It should be T / 6.

(Step 2) Time t = 0 when clock φ1 rises
Then, the latch 180a at the preceding stage of the binary logic circuit 40 extracted in (Step 1) is configured to operate when the voltage of the clock φ1 exceeds the threshold voltage VT1, that is, the logical value input at t = T / 6. Ingest. The latch 190 at the subsequent stage captures the logical value input when the voltage of the clock φ1 exceeds the threshold voltage VT1, that is, at t = 7 * T / 6. The time from when the latch 180a at the preceding stage of the binary logic circuit 40 captures the logical value to when the latch 190 at the subsequent stage captures the logical value is T. Similarly, the latch 19 in the preceding stage of the binary logic circuit 50 extracted in (Step 1)
0 means that when the voltage of clock φ1 exceeds the threshold voltage VT1,
That is, the logical value input at t = 7 * T / 6 is taken.
The latch 200 in the subsequent stage has the voltage of the clock φ 1
When T1 is exceeded, that is, the logical value input at t = 13 * T / 6 is taken. The time from when the latch 190 at the preceding stage of the binary logic circuit 50 captures the logical value to when the latch 200 at the subsequent stage captures the logical value is T. 40 of the binary logic circuits extracted in (Step 1) are T between the time when the latch 180a of the preceding stage captures the logical value and the time when the latch 190 of the subsequent stage captures the logical value is between the latches. The propagation time of the binary logic circuit 40 is larger than 25 * T / 24. (Step 3)
What.

(Step 3) The threshold voltage of the latch 180a at the preceding stage of the binary logic circuit 40 sandwiched by the latches extracted at (Step 2) is set to VT2 smaller than the threshold voltage VT1 of the latch 190 at the subsequent stage. That is, the latch 180a shown in FIG.
Change to 0b. Then go to (Step 2).

(Step 2) The time t when the clock φ1 rises is t
Assuming that = 0, the latch 180b at the preceding stage of the binary logic circuit 40 takes in the logic value input when the voltage of the clock φ1 exceeds the threshold voltage VT2, that is, at t = T / 12. The latch 190 at the subsequent stage captures the logical value input when the voltage of the clock φ1 exceeds the threshold voltage VT1, that is, at t = 7 * T / 6. The time from when the latch 180b at the preceding stage of the binary logic circuit 40 captures the logical value to when the latch 190 at the subsequent stage captures the logical value is 13 * T / 12, and the time of the binary logic circuit 40 between the latches is 13 * T / 12. Propagation time less than 25 * T / 24. Go to (Step 4).

(Step 4) The process ends.

As described above, in a semiconductor integrated circuit having clocks with different voltage levels and different time widths, the threshold voltage of the preceding latch of the binary logic circuit having a propagation time longer than the clock cycle is set to the threshold voltage of the subsequent latch. The time width of the clock can be changed by making it smaller than the threshold voltage. The propagation time of the logical value from IN to OUT, which was 3 * T conventionally, is changed to 25 * T / 12, and the logical value is efficiently and quickly increased. Can propagate.

In this embodiment, the threshold voltage of the preceding latch of the binary logic circuit having a propagation time longer than the clock cycle is set smaller than the threshold voltage of the subsequent latch. Is larger than the threshold voltage of the preceding latch, the time width of the clock can be changed, and the same effect can be obtained.

Effect of the Invention As described above, according to the semiconductor integrated circuit and the clock time width changing method of the present invention, after the clock voltage reaches the threshold voltage of the first latch, the clock 1
To make the time to reach the threshold voltage of the second latch after the period longer than the propagation time of the binary logic circuit,
Since the threshold voltage of the clock input of the second latch is different from that of the second latch, the logical value of the semiconductor integrated circuit can be efficiently and quickly propagated, and the practical effect is extremely large.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of the semiconductor integrated circuit of the present invention, FIG. 2 is a timing chart of the semiconductor integrated circuit of FIG. 1, and FIG. 3 is a clock of a single-phase triangular wave used in the present invention. FIG. 4, FIG. 4 is a circuit diagram of two types of latches used in the present invention, FIG. 5 is a diagram showing another clock used in the present invention, and FIG. 6 is a flowchart showing a method of changing the time width of the clock of the present invention. FIG. 7 is a circuit diagram of a semiconductor integrated circuit according to the present invention. FIG. 8 is a circuit diagram of a conventional semiconductor integrated circuit.
The figure is a timing chart of the semiconductor integrated circuit of FIG.
FIG. 10 is a circuit diagram of a conventional semiconductor integrated circuit, and FIG.
FIG. 4 is a timing chart of the semiconductor integrated circuit shown in FIG. 10, 30, 180b, 190, 200... Latch for storing a logical value when the voltage of clock φ1 exceeds VT2, 20, 180a..., Latch for storing a logical value when the voltage of clock φ1 exceeds VT1, 40. Output without changing the value of the logic value, and the propagation time of the logic value is 25 * T / 24
Value logic circuit, 50 ... Output without changing the value of the input logical value, and the propagation time of the logical value is 1 * each.
T / 6 binary logic circuit, 60... Clock φ1 input threshold voltage T1 inverter, 120... Clock φ1 input threshold voltage VT2 inverter.

Claims (2)

(57) [Claims] 1. A first latch and a second latch, each having a different threshold voltage of a clock input, having a propagation time longer than the clock cycle, wherein an input is applied to the first latch, and an output is applied to the first latch. A second logic circuit connected to two latches, the threshold value of the second latch being set one cycle after the clock has reached the threshold voltage of the first latch. A semiconductor integrated circuit, wherein a time to reach a voltage is longer than a propagation time of the binary logic circuit. 2. A method of changing a clock time width of a semiconductor integrated circuit having a binary logic circuit having a propagation time longer than a clock cycle and having an input connected to a first latch and an output connected to a second latch. A time period from when the voltage of the clock reaches the threshold voltage of the first latch to when the voltage of the clock reaches the threshold voltage of the second latch after one cycle of the clock is determined by the binary logic circuit. , So that the threshold voltages of the first latch and the second latch are different from each other.
Changing the threshold voltage of at least one of the first latch and the second latch.