JPH02148241A - Cache memory control system - Google Patents

Abstract

PURPOSE:To constitute a cache memory system so that a failure part can be supported easily even when a mounted cache memory device is used as it is by executing an operation test of an information processor by switching an operation mode of the cache memory device. CONSTITUTION:A cache hit/miss deciding circuit 44 decides a normal mode in which a cache memory device 40 operates regularly or a minicache mode for executing an operation only at the time of cache hit by mode information M from a mode register 43. By setting the cache memory device 40 to the minicache mode, a CPU 10 can execute an operation test of an information processor excluding a principal part of the cache memory device 40 in a state that the cache memory device 40 is mounted. Subsequently, after confirming a fact that the device is normal, the operation test of the principal component is executed by setting the cache memory device 40 to the normal mode. In such a way, a failure of the principal part of the device or other failure can be discriminated simply in a state that the cache memory device is mounted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a cache memory control method suitable for predicting the location of a failure in an information processing device equipped with a cache memory device.

(Prior Art) Recent information processing devices have a cache data memory between a main memory that stores instructions, data, etc. and a CPU, in which a copy of a portion of the storage contents of the main memory is stored in units of cache blocks. A cache memory device is typically provided.

In such an information processing device, when the CPU executes a program, the CPU stores a memory address in the main memory where the target instruction or data (hereinafter referred to as data including instructions) is stored in the main memory. If the data at this address (i.e., the target data) exists in the cache data memory (i.e., cache hit/miss)
is checked in the cache memory device.

In order to perform the above-mentioned check (cache hit/miss judgment), the cache memory device contains tag part information including an address tag indicating the address area corresponding to each of the above-mentioned blocks located in the cache data memory. A cache tag memory registered in an entry corresponding to the cache tag memory and a cache hit/miss determination circuit are provided. The cache hit/miss determination circuit refers to the entry in the cache tag memory based on the memory address output from the CPU to the address bus, and determines whether or not the address tag corresponding to the memory address is registered in the entry. Perform the error judgment operation (operation ■).

If a cache hit is determined, the target data is retrieved from the block in the cache data memory corresponding to the entry referred to above, and transferred to the CPU (as if it were read data from the main memory). Operation ■) is performed. This makes main memory access apparently faster.

On the other hand, if a cache miss is determined by the cache hit/miss circuit, the following two operations
will be held. Operation (2) is an operation in which tag part information including an address tag corresponding to a memory address on the address bus is written into the entry in the referenced cache tag memory. In addition, operation (■) reads the data of the cache block corresponding to the memory address on the address bus from the main memory, stores the read block data in the block in the cache data memory corresponding to the entry referenced above, and This is an operation in which only the target data (data requested by the CPU) of the data is transferred to the CPU.

(Problems to be Solved by the Invention) In an information processing device equipped with a cache memory device, each of the operations (1) to (4) above in the Cazonille memory device must all be performed normally. However, there is no guarantee that these will work normally during a projection function test or a product function test, which poses a problem in imagining the location of a malfunction in the information processing device. Conventionally, when performing function tests, it is necessary to use a special memory board for testing in place of the installed cache memory device.Even if the memory device is used as it is, it is easy to predict where the failure will occur when testing the information processing device. It is to be.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides first mode information for instructing a cache memory device included in an information processing device to a first mode in which the cache memory device normally operates; a mode setting means in which one of second mode information is set which instructs a second mode in which operation is performed only when the button is pressed, and a main memory when the first mode information is set in this mode setting means. A catch hit/miss that performs a normal operation of determining a catch hit/miss depending on the memory address to be accessed, and performs a special operation of uniquely determining a catch hit when the second mode information is set in the mode setting means. determining means, and performing an operation test of the information processing device while the cache memory device is operated in a first mode associated with a normal operation of the cash hit/miss determination means or a second mode associated with a special operation. It is characterized by the following.

(Function) According to the above configuration, by switching the information set in the mode setting means, the operation mode of the cache memory device is determined based on the result of determining cache hit/miss based on the memory address. The cache memory device can be divided into the original operating mode (first mode), which performs complex operations, and the operating mode (second mode), which performs simple operations that are always cached regardless of the memory address. By conducting tests in each condition, it is possible to determine whether the problem is in the main part (main functional part) of the cache memory device or something else.

(Embodiment) FIG. 1 is a block diagram showing an embodiment of an information processing apparatus including a cache memory device to which the present invention is applied. In the figure, 10 is a CPU that controls the whole;
3 is a main memory in which various programs and data are stored; 30 is a bus for the CPU 10, which is composed of an address bus 3L, a data bus 32, and a control bus 33.

40 is a cache memory device. The cache memory device 40 has a cache data memory in which a copy of a portion of the main memory 20 is placed in units of 2n-byte cache blocks, and a cache tag memory 42 having the same number of entries as the number of blocks in the cache data memory 41. The cache data memory 41 and the cache tag memory 42 are accessed by the upper m−n bits of the lower m bits of the memory address on the address bus 31. Each entry in the cache tag memory 42 has a cache data memory 4 corresponding to the same entry.
The address tag ATAG (upper address excluding the lower m bits of the corresponding memory address) indicating the 2n-byte address area to which the block placed in 1 belongs and the valid bit V indicating whether the same address tag ATAG is valid or not. The included tag part information is registered.

The cache memory device 4o also includes a mode register 43 in which mode information M indicating the operation mode of the device is set;
and a cache hit/miss determination circuit 44. The mode information M set in the mode register 43 is composed of, for example, 1 bit, and M-0 indicates a normal mode (first mode) in which the cache memory device 40 normally operates.
, and in M-1, the cache memory device 40 operates in a mini-cache mode (
2nd mode). In the normal mode, the cache hit/miss determination circuit 44 selects the upper m−n bits of the lower m bits of the memory address on the address bus 31.
A well-known cache hit/miss determination is performed based on the address tag ATAG in the entry in the cache tag memory 42 specified by the bit, the valid bit V1, and the upper address excluding the lower m bits of the same memory address.
The mini-cash mode is configured to uniquely determine the cash hit.

The cache memory device 40 further includes a cash register/
Controls the sequence of access to the main memory 20, cache data memo IJ 41, etc. according to the determination result of the error determination circuit 44, the type of memory access request (read/write type), and the contents of the mode register 43 (mode information M). control unit 45 and bus 30 busy/
When controlling the ready, it has a ready/ready control circuit 46.

Next, the operation of one embodiment of the present invention will be explained.

Cache memory device 4 in the information processing device shown in FIG.
0, the 1-bit mode information M set in the mode register 43 causes either normal mode or mini-cache mode to operate.

First, the operation in normal mode will be explained using an example of a memory read request from CPU10.

When the CPU 10 wants to read data (including instructions) from the main memory 2o, it outputs a memory address indicating the read destination to the address bus 31. The upper m−n bits of the lower m bits of the memory address on the address bus 31 are used for block designation of the cache tag memory 42 and entry designation of the cache tag memory 42. By specifying this entry, the cache tag memory 42
The contents of the corresponding entry (tag section information) are read out, and the address tag ATAG and valid bit V in the information are led to the cache hit/miss determination circuit 44. The cache hit/miss determination circuit 44 is led to the upper address excluding the lower m bits of the memory address on the address bus 31, and also 1-bit mode information M set in the mode register 43.

The cash hit/miss determination circuit 44 determines that when the 1-bit mode information M from the mode register 43 is "0" (
In other words, if the normal mode is specified), the normal cash hit/miss determination operation is performed. That is, the cache hit/miss determination circuit 44 compares the address tag ATAG from the cache tag memory 42 and the above-mentioned upper address from the address bus 31, and determines that they match and the valid bit V from the cache tag memory 42 is valid. (V-1
), a cache hit/miss (indicating whether the data in the main memory 20 indicated by the memory address on the address bus 31 exists in the cache data memory 41) is determined.

The cash hit/miss determination result of the cash hit/miss determination circuit 44 is led to the control section 45 and the busy/ready control circuit 4B. If the cache hit/miss determination circuit 44 determines a cache hit at the time of a memory read request, the control unit 45 selects the block in the cache data memory 41 indicated by the upper m−n bits of the lower m bits of the memory address on the address bus 31. , and performs control to output the data requested by CPU10 out of the 2n-byte data in the same block onto the data bus 32. At this time, the cash hit/miss determination circuit 44
The control bus 33
The busy/ready signal line (not shown) in the memory access request source (CPU
o) is notified that data on the data bus 32 can be input.

On the other hand, when the cache hit/miss determination circuit 44 determines a cache miss (miss), the control unit 45 selects the lower n of the memory address on the address bus 31.
The data (2n bytes) of the block in the main memory 20 specified by the upper address excluding bits is read from the main memory 20 and copied to the corresponding block in the cache data memory 41, and among the data in this copy block data, from CPU10 Control is performed to output requested data onto the data bus 32. Furthermore, the control unit 45 notifies the busy/ready control circuit 46 when the data copying is completed. The busy/ready control circuit 46 maintains the busy/ready signal line in the control bus 33 in a busy state when the cache hit/miss determination circuit 44 determines a cache miss as described above. The busy/ready control circuit 4B controls the control unit 4.
When the copy completion is notified from CPU 5, the busy/ready signal line is set to the ready state as in the cash hit determination, and the memory access request source (CPU to)
Notify that data entry is possible.

Next, the operation of the mini-cache mode will be described using as an example the case of a memory read request from the CPU 10, similar to the above-described normal mode.

The mini-cache mode is specified by setting the mode information M of logic "]" in the mode register 43 as described above. Catching hit/miss determination circuit 44
is the 1-bit mode information M from the mode register 43
If is “1” (mini cache mode specified),
Unlike the case of the normal mode described above, a cache hit is uniquely determined (regardless of whether the address tag ATAG from the cache tag memory 42 and the above-mentioned upper address from the address bus 31 match/mismatch). If the cache hit/miss determination circuit 44 determines a cache hit at the time of a memory read request, the control unit 45 performs the following operations.
As described above, read access to the block in the cache data memory 41 indicated by the upper m-n bits of the lower m bits of the memory address on the address bus 31 is permitted, and the CPU reads out the 2n byte data in the same block.
Control is performed to output the data requested from l0 onto the data bus 32. At this time, the busy/ready control circuit 46 sets a busy/ready signal line (not shown) in the control bus 33 to a ready state, and notifies the memory access request source (the CPU 10) that data input is possible. do.

In the mini-cache mode, as described above, a cache hit is always determined and a cache miss is never determined. Therefore, as in the normal mode described above, from the main memory 1) 20 to the cache data memory 4
A complicated sequence peculiar to a cache miss such as copying block data to 1 does not occur. Therefore, by setting the cache memory device 40 to mini-cache mode with correct data written in the cache data memory 41 in advance, the CPU 10 can perform information processing excluding the main part (main functional part) of the cache memory device 40. Perform device operation test on cache memory device 4
It becomes possible to execute with 0 installed. In this test, after confirming that the device is normal, the cache memory device 40 is set to normal mode and an operation test is performed, thereby making it possible to check the operation of the main parts of the cache memory device 40. . In addition,
Data writing to the cache data memory 41 is performed by the CP
Although it is possible to perform this by U10, here, it is performed from a device locally connected to bus 30. Furthermore, the mode information M can be set in the mode register 43 in a similar manner. Of course, setting using a switch or the like is also possible.

Note that the above-mentioned operation in response to the catch hit/miss determination result of the catch hit/miss determination circuit 44 is performed in the same manner as in the conventional case. However, the operation when a cache hit is determined at the time of a memory write request is slightly different when applying the write-through method in which write data is written not only to the cache data memory but also to the main memory based on the cache hit determination. This is because when attempting to perform memory write access in the mini-cache mode, writing to the main memory 20 also occurs.

Therefore, in this embodiment, the mode information M set in the mode register 43 is also led to the control unit 45, and when the mini-cache mode is specified by the information M,
Even if the cache hit/miss determination circuit 44 uniquely determines that there is a cache hit, the memory write request/miss
At times, writing to the main memory 20 is prevented from occurring.

[Effects of the Invention] As described in detail above, according to the present invention, by switching the information set in the mode setting means, the operation mode of the cache memory device can be determined based on the memory address as to cache hit/miss. The cache memory device's original operating mode (first
The cache memory device can be implemented by testing in each of these separate states. It is possible to easily determine whether the problem is in the main part (main functional part) of the cache memory device or something else.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 10... CPU, 20... Main memory, 31... Address bus, 32... Data bus, 33... Control bus, 40... Cache memory device, 4■.
. . . Cache data memory, 42 . . . Cache tag memory, 43 . . . Mode register, 44 . . Hit/miss determination circuit, 45 . Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Scope of Claims] An information processing device including a cache memory device having a cache data memory in which a copy of a part of the stored contents of a main memory is placed, wherein the cache memory device normally operates in the cache memory device. a mode setting means in which either first mode information instructing a first mode and second mode information instructing a second mode in which the cache memory device operates only when a cache hit is set; and the mode setting means When the first mode information is set in the mode setting means, a normal operation is performed to determine cache hit/miss according to the memory address for accessing the main memory, and the second mode information is set in the mode setting means. A cache hit/miss determination means is provided which performs a special operation to uniquely determine a cache hit when the mode setting means is set, and the information set in the mode setting means is switched, and the cache memory device is configured to perform a special operation to uniquely determine a cache hit. An operation test of the information processing apparatus is performed while the information processing apparatus is operated in a first mode associated with a normal operation of the cache hit/miss determination means or a second mode associated with a special operation of the cache hit/miss determination means. A cache memory control method featuring: