JPH08221270A - Data processor - Google Patents

Abstract

PURPOSE: To prefetch the interrupt program. CONSTITUTION: The data processor is provided with cache memories 20 to 22, prefetch buffers 23 to 25 for the memories 20 to 22, and control circuit 26 prefetching the command to the prefetch buffers 23 to 25 in parallel with the command fetch from the cache memories 20 to 23 by a CPU 3. The head address of the interrupt program is given to a register 27 during the interrupt transient control such as a retrieval required for the CPU 3 to move on the interrupt program. The device is provided with a control circuit 26 which prefetches a command to the prefetch buffer according to the interrupt address information given to the register 27.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device in which a central processing unit uses an instruction cache memory and an instruction prefetch buffer to perform data processing, and more specifically, a technique for extending the instruction prefetch function to interrupts. The present invention relates to a technique effectively applied to, for example, a data processor or a microcomputer and its application system.

[0002]

2. Description of the Related Art In order to improve the data processing capacity of a central processing unit, a RAM (random access memory),
A cache that reads some information from a mass storage device such as a ROM (Read Only Memory), hard disk device, floppy disk device, etc., but that can access instructions and data faster than a mass storage device. It is common practice to have the memory internal or closely external to the central processing unit. Such a central processing unit
While the information exists in the cache memory, the execution is continued while referring to the instructions and data in the cache memory, and the execution result is temporarily stored in the cache memory to access the external mass storage device. The data processing capability can be dramatically improved as compared with the execution. However, when the information required by the central processing unit does not exist in the cache memory, the cache memory performs the operation of causing the central processing unit to interrupt the execution of the instruction and reading and holding the necessary information from the external mass storage device. Then, the central processing unit restarts the execution of the interrupted instruction. If this state occurs frequently, the performance of the central processing unit is deteriorated. Therefore, in order to maximize the performance of such a central processing unit, it is necessary that the information required during execution be always present in the cache memory so that there is no interruption of instruction execution.

The cache memory is, for example, a cache tag that stores an effective address (virtual address or physical address) indicating which position (address) of the external storage device corresponds to one cache line information that constitutes one entry. , A data part for storing information of consecutive n words starting from the effective address, and a valid bit indicating whether the information stored in the cache line is valid. Incidentally, the contents of the cache memory may be updated as necessary, and a dirty bit indicating that the contents are different from the contents of the external mass storage device may be provided.

In the instruction cache memory, it is judged whether or not valid information exists in the instruction cache memory based on the instruction address from the central processing unit and the cache tag information in the instruction cache memory. If present, the central processing unit fetches the instruction from cache memory. If it does not exist, information for one line (n words) of the cache memory including the instruction address is read from the external mass storage device to the data part of the predetermined line of the corresponding cache memory by burst transfer called line fetch. Put in. Then, the line fetched instruction is fetched by the central processing unit. If there is no valid information in the cache memory during instruction execution, the central processing unit cannot start execution of the instruction until the required instruction is read from the external storage device by line fetch. This waiting time, that is, the instruction execution stop time, is called a mishit penalty. The mishit penalty is a data processing as the operation speed of the central processing unit dramatically increases and the difference in access time from the external storage device increases. Significantly affects performance degradation.

Therefore, by utilizing the period during which the central processing unit is not exchanging data with the external storage device,
It is possible to employ a prefetching method of reading information expected to be used by the central processing unit in the future in advance of execution of the central processing unit. This prefetch is realized by almost the same operation as the line fetch except that the expected address is used. However, if prefetch is performed, the instruction fetch from the cache memory by the central processing unit and the line fetch from the external storage device to the cache memory may conflict with each other in the cache memory, so the instruction prefetch buffer may be, for example, one line of the cache memory or more. May be prepared. This allows
The instruction can be prefetched into the instruction prefetch buffer in parallel with the instruction fetch from the instruction cache memory by the central processing unit. Such an instruction cache memory configuration is generally called a non-blocking cache memory. As an example of a document describing a technique for prefetching an instruction, Japanese Patent Laid-Open No. 3-97
There is a 032 publication.

[0006]

[Problems to be Solved by the Invention]
When continuing from the lower instruction address to the upper instruction address, the instruction prefetch always simply prefetches the information (n words) for one line of the next cache memory to the current execution address. There is definitely an effect alone. However, if the next program address to be executed cannot be dynamically or statically estimated from the execution of the current program (the instruction address to be executed is discontinuous in the middle due to occurrence of a predetermined event), an interrupt etc. Caused by. In this specification, an interrupt is C
It is used as a concept including the occurrence of exception events such as address errors that occur during execution of PU instructions. Interrupt is C
When it is requested from the outside of the PU, the event that causes it is generated asynchronously with the operation of the CPU.
When an interrupt is generated inside the CPU, it is virtually impossible for the CPU to predict when it will occur. Therefore, it has been clarified by the present inventors that the instruction of the interrupt processing program for responding to such an interrupt request has not been prefetched in the past, and the performance degradation due to this has been difficult. . In this way, instructions and data are prefetched within the predictable range in the internal or external cache memory for high performance, and prefetching is performed for programs that cannot predict when processing will start, such as interrupts. It has been clarified by the present inventor that the performance of the cache memory provided for speeding up is not fully utilized.

It is an object of the present invention to provide a data processing device capable of prefetching an interrupt processing program whose execution start time cannot be predicted. Further, the present invention is a data processing apparatus which can achieve the above-mentioned object by slightly changing the configurations of the cache memory and the instruction prefetch buffer having many kinds of conventional prefetch functions, in other words, suppressing the cost increase. Is to provide.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, there is always a time gap from the occurrence of the interrupt until the instruction execution by the central processing unit is switched to the interrupt processing program (processing program for responding to the interrupt request). To
The interrupt processing program is prefetched into an instruction prefetch buffer or an instruction cache to improve data processing performance. In order to improve the data processing performance of the central processing unit, it is necessary to cause the instruction cache memory to have a high probability of retaining an instruction having a high execution probability.
To increase the probability, it is possible to deal with it by simply increasing the capacity of the instruction cache memory, but this is not realistic because there is a drawback that the system cost increases. In this respect, the present invention focuses on the prefetch mechanism of the instruction cache memory and the instruction prefetch buffer, and adds some ingenuity to the instruction prefetch algorithm (control flow) and the structure of the cache memory and the instruction prefetch buffer for them, thereby reducing the cost. Achieve high performance of the instruction cache memory by suppressing the increase. The means for doing so will be described below.

[1] A data processing device (data processor 1) includes a central processing unit (3) for executing an instruction and an instruction prefetch buffer (2 for prefetching the instruction.
3, 24, 25), an instruction cache memory (20, 21, 22) for holding prefetched instructions, and an instruction corresponding to an instruction fetch address in response to an instruction fetch instruction, the prefetch buffer, the instruction cache memory, or A cache and prefetch control circuit (26) for controlling to acquire from the outside and controlling to acquire an instruction corresponding to an instruction prefetch address from the outside to the prefetch buffer in response to an instruction of the instruction prefetch
When an interrupt request is accepted, an instruction (406) for instructing the instruction prefetch buffer to prefetch an instruction based on the start address information of the processing program for responding to the request is given to the cache and the prefetch control circuit. 4) and are provided.

[2] The instruction prefetch of the interrupt processing program is performed in parallel with the interrupt transition control period for the central processing unit to save the internal state after the interrupt occurs. From the viewpoint of increasing the chances of instruction prefetching during this interrupt transition control period, the central processing unit responds to the interrupt request after the central processing unit receives the interrupt acceptance notification from the interrupt control circuit. Further, the data processing device is formed on one semiconductor substrate by further including data storage means for saving the internal state of the central processing unit during the transition control period until the execution of the processing program. For example, when the data storage means is a data cache memory (DCACHE), a write back buffer (WBB) may be provided between the data cache memory and the outside. The write back is also called copy back.

[3] The interrupt control circuit (4) stores the start address information of the interrupt processing program for responding to the interrupt request accepted by the address register (27).
The cache and prefetch control circuit (26) can be configured to perform instruction prefetch based on the address information held in the address register. Further, the interrupt control circuit (4) provides a table (40) for holding various start address information corresponding to an interrupt factor in order to output the start address information of the interrupt processing program, and when an interrupt request is accepted, The address corresponding to the cause of the request is set in the table (40).
To the address register (27). At this time, if the degree of freedom for mapping the interrupt processing program is taken into consideration, the above table (4
0) may be rewritable by the central processing unit (3). Further, the interrupt control circuit (4) can receive the start address information of the interrupt processing program from the peripheral circuit (7) of the accepted interrupt request source and give it to the address register (27). is there.

[4] An instruction cache memory has a cache data section (20) for storing a plurality of instructions having a predetermined number of words as one data block, and a cache for associating the instruction of the cache data section with its instruction address. The instruction when the address section (21) and a cache comparison circuit (22) for detecting whether a part (ATAG) of the instruction access address matches the address information (CTAG) of the cache address section In the prefetch buffer, a buffer data unit (2 that can store an instruction having a number of words equal to the number of instruction words of one data block of the cache data unit as one data block (data for one line of the cache data unit 20)
3), and a buffer address part (24) for associating the command of the buffer data part with the command address thereof,
Part of the instruction access address (ATAG, IDX) is the address information (BTAG, IDX) of the buffer address part.
Buffer comparison circuit (25) for detecting whether or not
It is good to configure with and. As a result, the prefetch for the instruction prefetch buffer can be performed by the same control as the line fetch for one cache line in the instruction cache memory. At this time, the cache and prefetch control circuit (2
6) is a cache comparison circuit (22) and a buffer comparison circuit (2) in response to the instruction prefetch command.
The instruction prefetch to the instruction prefetch buffer is started by detecting the non-coincidence comparison result from both of 5) (step S44 = NO), and substantially unnecessary prefetch is not performed. When the instruction access to the instruction prefetch buffer after completion of the instruction prefetch is performed, the content of the prefetch completed instruction prefetch buffer is written in the cache memory by detecting the comparison result of the coincidence in the buffer comparison circuit (step S8). As a result, it is possible to eliminate the inconvenience of erasing an existing cache entry from the instruction cache memory by an instruction that does not result in a buffer hit and is not used even if prefetched into the instruction prefetch buffer. In response to such a prefetch mechanism, the interrupt control circuit 40, when accepting an interrupt request, issues a command (406) for prefetching an instruction in the instruction prefetch buffer based on the start address information of the processing program for responding to the request. ) To the cache and prefetch control circuit 26.

[5] In the above-mentioned means [4], an interrupt control circuit is added in addition to the central processing unit as an instruction prefetch instruction generation source. At this time, in order to share the address register holding the instruction access address for instruction fetch and instruction prefetch with the instruction prefetch command from both sides for instruction fetch, the start address of the interrupt processing program and the value of the program counter , Selecting means (271, 27) for giving to the address register one address selected from the prefetch address generated based on the value of the program counter.
2), the cache and prefetch control circuit (26) detects a mismatched comparison result from both the cache comparison circuit and the buffer comparison circuit in response to an instruction fetch command, and causes the selection means to have a program counter (30). ) Value is selected, and when the instruction generation source is the interrupt control circuit, the selection means selects the start address of the interrupt processing program. When the command generation source is the central processing unit, the selecting means is made to select the prefetch address generated based on the value of the program counter.

[0016]

According to the above-mentioned means, the central processing unit saves the value of the program counter, the value of the processor status register, etc. by hardware from the occurrence of the interrupt until the program is switched to the interrupt processing. After saving the necessary information, the interrupt processing program will be executed. When pipeline processing is adopted, it is also necessary to save various types of information in order to minimize disturbance of the pipeline due to interrupts before moving to the interrupt processing program. The data processing device prefetches the instruction of the interrupt processing program in parallel with the interrupt transition control such as saving. The instruction address to be prefetched is given from the interrupt control circuit (4) to, for example, the address register (27), and the address register (2)
An instruction of the prefetch operation using the value of 7) is given from the interrupt control circuit (4) to the cache and prefetch control circuit (26). The opportunity of memory access required for prefetching the interrupt processing program is given when the bus is free during the save processing or the like. For example, in a data processing device that adopts an architecture that has a plurality of sets of the same register and saves the register by switching the register at the time of interrupt, since the bus is free at the time of switching, the interrupt processing program is Instructions can be prefetched. In addition, with regard to data, non-blocking with a data cache memory and write-back buffer
In the case where the cache memory is used, even if the external memory area is used as the save area of the register, the cache memory can store the data to be saved in the case of a cache hit. The instruction of the interrupt processing program can be prefetched depending on the timing. Even in the case of a cache miss, the write-back buffer temporarily stores the write-back data to the external memory for replacing the entry, so that the write-back to the external memory can be postponed.

[0017]

【Example】

[Interrupt transition control and parallel instruction prefetch]
First, a data processor 1 according to an embodiment of the present invention.
In order to easily understand each part of the above, a configuration for instruction fetch and prefetch by the data processor 1,
Then, interrupt transition control and prefetching of an interrupt processing program in parallel therewith will be schematically described.

FIG. 1 is a partial block diagram of a data processor according to an embodiment of the present invention. Although not particularly limited, the data processor 1 shown in FIG. 1 is made of single crystal silicon or the like by a known semiconductor integrated circuit manufacturing technique.
It is formed on each semiconductor substrate. The data processor 1 of this embodiment includes an instruction cache / prefetch unit 2 and a central processing unit (CPU) as an arithmetic control unit, which are representatively shown.
3 and an interrupt control circuit 4, which are connected to the internal data bus IDB and the internal address bus IAB. 5
Reference numerals 1, 52, 53, 54 and 55 are representatively illustrated external interfaces, and mean circuit blocks having external terminals and buffer circuits for input / output. A main memory 6 and peripheral circuits 7 and 8 exemplarily shown in FIG.
B and the external address bus EAB or the like.

The instruction cache / prefetch unit 2
Includes an instruction cache memory (20, 21, 22), an instruction prefetch buffer (23, 24, 25) for the instruction cache memory, and a cache and prefetch control circuit 26. The cache and prefetch control circuit 26 controls the instruction fetch from the main memory 6 and the operations of the instruction cache memory and the instruction prefetch buffer.

The program executed by the central processing unit 3 is stored in the main memory 6, and a plurality of instructions recently executed by the central processing unit are stored in the cache data section 20 of the instruction cache memory. The buffer data unit 23 of the instruction prefetch buffer is a buffer memory in which the data read from the main memory 6 at the time of a cache miss in the instruction cache memory or the data read from the main memory 6 for instruction prefetch is temporarily stored. is there. The cache and prefetch control circuit 26 stores a predetermined number of words (8 words according to this embodiment) of instructions in the buffer data section 23, and when the instruction is ready to be used (buffer hit), the instruction string is stored. Internally transferred to the cache data unit 20 as a new entry. The program counter 30 holds the instruction address to be executed next by the central processing unit 3.

In the instruction fetch by the central processing unit 3, the cache comparison circuit 22 determines whether or not the instruction corresponding to the instruction address of the program counter 30 exists in the instruction cache data section 20.
The cache and prefetch control circuit 26 is notified of the result by making a determination by referring to the contents of 1. Further, the buffer comparison circuit 25 judges whether or not the instruction corresponding to the instruction address of the program counter 30 exists in the buffer data section 23, by referring to the contents of the buffer address section 24, and the result is the buffer hit signal 251. The cache and prefetch control circuit 26 is notified at. When the cache hit is notified by the signal 221, the cache / prefetch control circuit 26 transfers the instruction corresponding to the instruction address of the program counter 30 from the cache data unit 20 to the instruction register 31. When the cache miss is notified by the signal 221 and the buffer hit is notified by the signal 251, the cache and prefetch control circuit 2
6 transfers the instruction corresponding to the instruction address of the program counter 30 from the buffer data section 23 to the instruction register 31. When the cache miss is notified by the signal 221 and the buffer miss is notified by the signal 251, the cache and prefetch control circuit 26 gives the instruction address of the program counter 30 to the main memory 6 via the address register 27, and The instruction read from the main memory 6 is transferred to the instruction register 31 through the buffer data section 23. The instruction address of the program counter 30 at this time is given to the address register 27 via the selectors 272 and 271. The access to the main memory 6 is a burst access, and when an instruction for 8 words in total is stored in the buffer data section 23 and a buffer hit is notified by the signal 251, the instruction of 8 word is a new entry. Is stored in the cache data unit 20 as

Cache and prefetch control circuit 26
Performs instruction prefetch when the central processing unit 3 is not accessing the bus. The access to the main memory 6 for the instruction prefetch is a burst access to the main memory 6 as in the case of the cache miss and the buffer miss, and a total of 8 words of instructions are stored in the buffer data unit 23, and When a buffer hit is notified by the signal 251, the 8-word instruction is stored in the cache data unit 20 as a new entry. As described above, in the case of instruction prefetch, the instruction stored in the buffer data unit 23 is not immediately transferred to the cache data unit 20. An instruction that does not result in a buffer hit even if prefetched is executed by the cache data unit 20.
This is because it is inconvenient to add an existing entry that was once used to execute an instruction from the instruction cache memory when adding it as a new entry. The instruction address to be prefetched is given to the address register 27 by increasing the instruction address of the program counter 30 by one cache line by the counter 273 (+8 according to this embodiment). The timing of giving the instruction prefetch address to the address register 27 is synchronized with the instruction of the instruction prefetch from the central processing unit 3.

Further, in the present embodiment, the interrupt control circuit 4 issues an instruction prefetch command for the interrupt processing program by utilizing the above-mentioned configuration for instruction prefetch. When the interrupt control circuit 4 receives any interrupt requested by the interrupt request signals 401, 402, and 404 shown in FIG. 1, the interrupt control circuit 4 notifies the central processing unit 3 of the interrupt by a signal 405, Further, the cache and prefetch control circuit 26 is instructed to prefetch the interrupt processing program by a signal 406. The central processing unit 3 notified of the interrupt by the signal 405 starts interrupt transition control for saving the current internal state required for returning from the interrupt processing program. At this time, the interrupt control circuit 4 supplies the start address of the interrupt processing program corresponding to the accepted interrupt request to the address register 27 as an instruction prefetch address via the selectors 272 and 271. The cache and prefetch control circuit 26 instructed to perform the instruction prefetch operation by the signal 406 performs the instruction prefetch operation using the start address of the interrupt processing program supplied to the address register 27 to the interrupt transition control of the central processing unit 3. Start in parallel with the period.

The central processing unit 3 has a program counter 30 and a status register 3 which are connected to an internal data bus IDB through a data register or a bus switch 37 similar thereto, as shown in FIG.
3, the save register 34, the arithmetic circuit 35, and the control circuit 36 are provided, and the internal address bus IAB is coupled to the arithmetic circuit 35. The arithmetic circuit 35 includes a general-purpose register 351, an arithmetic logic calculator 352, a shifter 353, and the like. The control circuit 36 decodes the instruction fetched in the instruction register 31 to generate a control signal necessary for sequentially executing the instructions, and after receiving the interrupt signal, shifts the instruction execution state to a predetermined interrupt processing program. The interrupt transition control up to the above is performed. The control logic for realizing them can employ microprogram control or wired logic, or a logic configuration using both in combination. In FIG. 11, the interrupt transition control unit 360 is representatively shown. When the interrupt signal 405 is activated, the interrupt transition control unit 360 generates a control signal in accordance with its logical configuration, saves internal information required at the time of restoration, and then performs branch processing to the interrupt processing program. To do. The internal information to be saved is the program counter 3
0, the value of the status register 33, the value of the general-purpose register 351 and the like. The value of the status register 33 includes the processor status word (PSW).
The saving of the information held by the program counter 30 and the status register 33 is performed to the save register 34 when it is not a multiple interrupt (interrupt accepted multiple times during execution of a predetermined interrupt processing program), and multiple interrupts are performed. In this case, the main memory 6 is used. In many cases, the saving of information held by the general-purpose register 351 is performed in the main memory 6. The interrupt transition control unit 360 generates control information for controlling such save processing according to its hardware configuration.

Although not specifically shown in FIG. 1, the data processor 1 of the present embodiment has a data cache memory for storing data used for instruction execution by the central processing unit 3 and a data cache memory. Write back buffer (write buffer). The data cache memory and the write-back buffer will be described separately with reference to FIGS. 8 and 9, but the data cache memory holds the data of the main memory 6 which has been used once together with its address information. When the cache memory is the primary storage, the data shared with the main memory as the secondary storage must be matched (matched). At this time, when a cache hit occurs in the write access and the entry of the cache memory is rewritten, there are a write-through method and a write-back method as a control method of writing back the content to the secondary storage. In the write-through method, data is written to the secondary storage at the same time when the cache memory is rewritten. The write-back method is a method in which, when a cache memory is rewritten in a write access, the rewritten contents are written back to the main memory when a cache miss occurs and the entry is replaced with a new entry. Although not particularly limited, the data processor 1 of the present embodiment adopts the write back method. The write-back buffer is a buffer memory for temporarily holding the write data to the main memory 6 for reflecting the information held in the data cache memory in the corresponding data of the main memory 6 when the information is rewritten. Therefore, when a memory access with the main memory 6 as the save destination is performed, if the data cache memory has an entry corresponding to the access address, the data processor 1 needs to activate the external bus access. do not do. In addition, the write-back buffer arranged between the data cache memory and the main memory 6 is used to replace the cache entry when a cache miss occurs in the data cache memory.
Since the data to be written back to the main memory 6 is temporarily stored and the writing of the data related to the cache miss to the cache memory is prioritized, the activation of the external bus cycle for the writing back can be postponed. As a result, in the saving process in the interrupt transition control, it is not necessary to perform all of them by accessing the main memory 6 by starting the external bus cycle. In other words, there are always a plurality of cycles during which the external bus cycle is not activated in the save processing during the interrupt transition control period by the central processing unit 3. Therefore, in parallel with the interrupt transition control by the central processing unit 3, the cache and prefetch control circuit 26 can guarantee the operation of prefetching the interrupt processing program from the main memory 6.

[Overall Configuration of Data Processor] Now that the outlines of instruction fetch and prefetch in the data processor 1 have been understood in the above description, the details of each part of the data processor 1 will be described again with reference to FIG.

The instruction cache memory has a cache data unit 20 for storing a plurality of data of a predetermined number of words as one data block, and a cache data unit 2.
A cache address portion 21 for associating the data of 0 with the address of the data, and a part of the instruction address (address tag ATAG) is used as the cache address portion 21.
The cache comparison circuit 22 for detecting whether or not it matches the tag information (cache tag CTAG) of FIG. According to the present embodiment, the cache data unit 20 includes a plurality of sets of 8-word data storage regions of word # 0 to word # 7 (words # 0 to # 7 form one data block), and a cache address unit. 21 is a cache tag C corresponding to an 8-word data storage area (# 0 to # 7)
It comprises a pair of TAG and its valid bit Vc. The 8-word data storage area (# 0 to # 7) and the corresponding cache tag CTAG and valid bit Vc are simply called a cache line. Here, in the data processor 1 of the present embodiment, the address signal for instruction access can be regarded as the word WRD, the index IDX, and the address tag ATAG from the least significant side. Word W at this time
RD is word # 0 included in one cache line
It can be regarded as address information for selecting one from word # 7. According to this example, the word WRD has 3 bits. The index IDX can be regarded as address information for selecting one cache line from a plurality of cache lines. For example, when the cache data section 20 has 256 cache lines, the index IDX is 8 bits. The cache tag CTAG holds the address tag ATAG common to each instruction stored in the words # 0 to # 7 of the corresponding cache line. The valid bit Vc indicates the validity (existence or definiteness) of the cache line including it by its logical value, for example, a logical value "1".
Is valid, and “0” is invalid.

The instruction prefetch buffer has a buffer data section 23 and a buffer address section 24 for associating the data of the buffer data section 23 with its address.
And a buffer comparison circuit 25 for detecting whether or not a part of the instruction address (address tag ATAG and index IDX) matches the address information (prefetch buffer tag BTAG and index IDX) of the buffer address section 24. . The buffer data section 23 is similar to the cache data section 20 in word #
Equipped with a data storage area of 8 words from 0 to word # 7,
The data storage area (# 0 to # 7) is not particularly limited, but one set is provided. Buffer address section 24
Has a prefetch buffer tag BTAG corresponding to 8 words of data stored in the buffer data section 23, a valid bit Vb, and a write completion bit C. The prefetch buffer tag BTAG holds an address tag ATAG common to each instruction stored in the words # 0 to # 7 of the buffer data section 23. Effective bit Vb
Indicates the validity of the data contained in the buffer data section 23 by its logical value. For example, the logical value "1" is valid.
0 "indicates invalidity. The write completion bit C is stored in the buffer data section 23 in words # 0 to # when the instruction prefetch is performed.
Whether or not a total of 8 words of 7 has been written is indicated by its logical value. For example, the logical value "1" indicates that writing is completed.
0 "means incomplete.

Each word # 0 to # of the buffer data section 23
Input data to the storage area corresponding to 7 is supplied from the main memory 6 via the internal data bus IDB. The storage information stored in the buffer data section 23 is made writable in the storage areas # 0 to # 7 of the desired cache line of the cache data section 20. According to the writing from the buffer data unit 23 to the cache data unit 20, the information of the prefetch buffer tag BTAG is changed to the cache address unit 21.
To the cache tag CTAG. At this time, the cache line is selected by the buffer address section 24.
The index IDX is supplied to the cache data unit 20 and the cache address unit 21 via the selector 201. One word of the data stored in the storage areas # 0 to # 7 of one cache line selected by the cache data unit 20 is selected via the selector 200. Further, the selector 230 selects one data from the storage areas # 0 to # 7 of the buffer data section 23 and supplies it to the bypass path 231. Selector 2
The selection control of 00 and 230 is performed by the cache and prefetch control circuit 26 based on the word WRD. The instruction cache memory shown in FIG. 1 is illustrated as a direct map type cache memory, but a set associative type can be adopted. In that case, the instruction prefetch buffer can also be realized by adding more in accordance with the number of sets or the number of ways in the set associative format.

In FIG. 1, as a register for holding an instruction address, a program counter 30 included in the central processing unit 3 and an address register 27 provided in the instruction cache prefetch unit 2 are shown. The program counter 30 holds an instruction address to be executed next by the central processing unit 3. The address register 27 holds an instruction address to be fetched or prefetched from the main memory 6. Address tag ATAG and index ID of the instruction address that the address register 27 should hold
The X and the word WRD are output by the program counter 30, the interrupt control circuit 4 or the counter 273, one of them is selected by the selectors 271, 272 and supplied to the address register 27. The instruction address information held by the program counter 30 is supplied to the path 275. The start address of an interrupt processing program, which will be described later, output from the interrupt control circuit 4 is supplied to the path 274. The counter 273 generates an instruction prefetch address based on the instruction address held by the program counter 30. That is, the counter 273 is the program counter 3
Input a value of 0, increase it by one cache line (increase by +8 words), and output it. The output selection of the counter 273 by the selector 271 is performed based on a prefetch command.

The selection of the cache line for the cache data section 20 and the cache address section 21 is performed by decoding the output of the selector 201 by a decoder (index decoder) not shown. The selector 201 selects and outputs the index IDX of the address held by the program counter 30, the index IDX of the address held by the address register 27, or the index IDX held by the buffer address unit 24. The cache comparison circuit 22 determines the validity of the cache line by the validity bit Vc of the cache line selected based on the output of the selector 201, and when it indicates that it is valid, the cache comparison circuit 22 selects it by the selector 220. It is determined whether the generated address tag ATAG matches the cache tag CTAG of the cache line, and the cache hit signal 221 is activated if the determination result is a match.
As a result, the cache and prefetch control circuit 26
Is notified of a cache hit. The selector 220 is
Address tag A supplied from the program counter 30
The address tag ATAG supplied from the TAG or the address register 27 is selected. The buffer comparison circuit 25
Inputs the valid bit Vb of the buffer address section 24, and when it indicates that it is valid, the selector 22
It is determined whether the address tag ATAG selected by 0 matches the prefetch buffer tag BTAG of the buffer address part 24 and the index IDX selected by the selector 250 matches the index IDX of the buffer address part 24, When the respective judgment results are in agreement, the buffer hit signal 251 is activated.
As a result, the cache and prefetch control circuit 26
Is notified of a buffer hit. The selector 250 is the index ID supplied from the program counter 30.
X or the index IDX supplied from the address register 27 is selected.

The interrupt control circuit 4 arbitrates and accepts interrupt requests from inside or outside the data processor 1 according to information for prioritizing various interrupt requests and masking the interrupt requests, and accepts the received interrupt requests. Controls that a response is returned. FIG. 1 representatively shows external interrupt request signals 401 and 402, a response signal 403 to them, and an internal interrupt request signal 404 from the central processing unit 3. A signal 405 is an interrupt signal for notifying the central processing unit 3 that the interrupt control circuit 4 has accepted the interrupt. Interrupt signal 40
When the central processing unit 3 recognizes the acceptance of the interrupt by 5, the central processing unit 3 saves the information stored in the program counter 30 and the status register 33 according to the control of the interrupt transition control unit 360 as described above. . When the evacuation process is completed, the program counter 30
Is set to the start address (interruption start address) of the interrupt processing program for responding to the accepted interrupt request, whereby the central processing unit 3 is made ready to execute the interrupt processing program. The period required for the central processing unit 3 to change its inside from the execution state of the normal processing program to the execution state of the interrupt processing program for the interrupt request is called an interrupt transition period. An example of the processing of the central processing unit 3 during the interrupt transition period will be described later with reference to FIG.

The interrupt control circuit 4 includes a central processing unit 3
In parallel with the interrupt transition period, the instruction cache prefetch unit 2 starts prefetching of the interrupt processing program. That is, the interrupt control circuit 4 is provided with a table 40 that holds the start address of the interrupt processing program in association with the interrupt factor, and accepts an interrupt request 402 from the peripheral circuit 8 or an interrupt request 403 from the central processing unit 3, for example. Then, the start address of the interrupt processing program corresponding to the request is set to the table 40 above.
Information from the selected start address is selected from the route 274.
Is supplied to the address register 27 via. Also,
The peripheral circuit 7 has an interrupt start address register 71 for storing the start address of the interrupt processing program. In other words, the start address of the interrupt processing program corresponding to the peripheral circuit 7 is set in the table 40. Otherwise, when the interrupt request source has a function of outputting the address information held in the interrupt head address register 71 to the internal data bus IDB when the interrupt request source is notified by the signal 403, When the control circuit 4 accepts an interrupt in response to the interrupt request signal 401 from the peripheral circuit 7, the control circuit 4 receives the interrupt start address output from the peripheral circuit 7 and sends it to the path 27.
4 to the address register 27. The table 40 is rewritable by the central processing unit 3,
The degree of freedom of address mapping for the interrupt processing program (interrupt handler) written by the user is guaranteed.
The table 40 can be composed of a plurality of registers that can be read and written by the central processing unit 3, for example.

When the interrupt control circuit 4 gives the start address of the interrupt processing program to the register 27, an instruction to prefetch an instruction according to the start address (interrupt start address) is given by the interrupt acceptance signal 406 to the cache and prefetch control circuit. Give to 26.

The start address of the interrupt processing program output from the interrupt control circuit 4 to the path 274 is also supplied to the central processing unit 3. According to the example of FIG. 11, the start address of the interrupt processing program is the latch 3 of the control circuit 36.
61. The central processing unit 3 uses the interrupt signal 40
After performing the interrupt transition control based on the notification of the interrupt by 5, set the start address of the interrupt processing program from the latch 361 to the program counter 30,
Move on to execution of interrupt processing program.

In FIG. 2, an interrupt control logic 70 and an interrupt start address register 71 are typically shown in the peripheral circuit 7. The interrupt control logic 70 activates the interrupt request signal 401 when the operation of the peripheral circuit 7 requires the execution of a predetermined interrupt processing program by the central processing unit 3. Although not particularly limited, the interrupt response signal 403 includes identification information unique to the interrupt request source. Therefore, when the interrupt control circuit 4 accepts the interrupt request by the interrupt request signal 401, it outputs an interrupt response signal 403 including identification information unique to the peripheral circuit 7, whereby the peripheral circuit 7 confirms that the interrupt request is accepted. Recognized,
The start address of the interrupt processing program stored in the interrupt start address register 71 is set to the external data bus ED.
Output to B. The initialization of the interrupt start address register 71 can be performed by the central processing unit 3. The start address of the interrupt processing program output to the external data bus EDB is taken into the interrupt control circuit 4 of the data processor 1 via the external interface 55. The peripheral circuit 8 shown in FIG. 2 has an interrupt control logic 80 that recognizes an interrupt request and acceptance, and does not have an interrupt start address register. That is, the start address of the interrupt processing program to be executed by the central processing unit 3 in response to the interrupt request from the peripheral circuit 8 is the interrupt control circuit 4 described above.
Stored in the table 40 of FIG.

The main memory 6 has a work area for the data processor 1 and a storage area for storing operation programs (instruction sets) and data for the central processing unit 3. The interrupt processing program and other programs to be read by the instruction cache / prefetch unit 2 are the main memory 6 concerned.
It is stored in. According to the present embodiment, the access address for the main memory 6 is given from the external interface 54 of the data processor 1 via the external address bus EAB. In this embodiment, the main memory 6 can access data in word units. An access address for instruction fetch and instruction prefetch for the main memory 6 is given from the address register 27 of FIG. At this time, the instruction cache / prefetch unit 2
The instruction prefetch to the buffer data unit 23 can be performed by burst transfer. When the main memory 6 itself has a burst transfer mode, the burst transfer mode is set according to the specifications of the main memory 6 and the address of the first word of burst transfer is supplied. For example, when the main memory 6 has a burst transfer function of 8-word information, the word WRD of the address register 27
Is a bit string designating the word to be fetched first, and the address of the address register 27 is supplied to the main memory 6. If the main memory 6 does not have the burst transfer mode, the cache and prefetch control circuit 26 makes the word WRD of the address register 27 access the main memory 6 as a bit string for word designation to be fetched first, and the word is accessed every time the access is made. An 8-word instruction is prefetched by eight memory accesses while sequentially updating WRD. That is, in this case, the cache and prefetch control circuit 26 can control the word WRD of the address register 27 to perform a counting operation as a 3-bit ring counter (not shown). The lower 3 bits (word WRD) of the interrupt start address stored in the table 40 of the interrupt control circuit 4 or the interrupt start address register 71 of the peripheral circuit 7 and the word WRD of the program counter 30 are also registered via the selectors 271, 272. Two
7 words WRD can be supplied.

[Control Mode of Instruction Fetch and Prefetch Activation] FIG. 3 shows an operation flowchart of instruction fetch and prefetch activation based on a command from the central processing unit 3. In the figure, the instruction prefetch instruction does not include the instruction prefetch instruction from the interrupt control circuit 4.

The central processing unit 3 requests the cache and prefetch control circuit 26 to instruct the cache and prefetch control circuit 26 to infer an instruction which will be executed next by inferring from the currently executed instruction. At this time, the central processing unit 3 gives the instruction fetch address held by the program counter 30 to the instruction cache prefetch unit 2. The instruction cache prefetch unit 2 starts control of the instruction fetch operation using the given instruction fetch address as the effective address (step S1). In the instruction fetch operation, it is searched whether the instruction to be fetched exists in the cache data unit 20 of the instruction cache memory or the buffer data unit 23 of the instruction prefetch buffer. In FIG. 3, for convenience, the processing is roughly classified into a case where the instruction to be fetched exists in the instruction cache memory, a case where the instruction exists in the instruction prefetch buffer, and a case where neither of them exists.

When the control of the instruction fetch operation is started,
In the cache data section 20 and the cache address section 21, one cache line is selected by the index IDX of the program counter 30. Whether the valid instruction has already been read into the selected cache line is indicated by the valid bit Vc of the relevant cache line. When the valid bit Vc is true (logical value "1"), the cache included in the relevant cache line. The cache comparison circuit 22 compares the tag CTAG with the address tag ATAG included in the program counter 30. When the comparison result is a match (step S2 = YES, and step S3 = Y)
ES), the cache and prefetch control circuit 26 is notified by the cache hit signal 221 that the required instruction exists in the cache line. As a result, the cache and prefetch control circuit 26 controls the selectors 200 and 32 according to the information in the word WRD of the program counter 30 to transfer (fetch) the necessary instruction to the instruction register 31 of the central processing unit 3 (step S4). . It should be noted that the selector 32 arranged in the preceding stage of the instruction register 31 in FIG. 1 selects the output information of the selector 200 or the information from the bypass path 231, and when the cache hit occurs, the output information of the selector 200 is changed to the cache miss. In the case of, the information from the bypass route 231 is selected. The instruction is given from the cache and prefetch control circuit 26 by a signal 261.

Although not particularly limited, after the instruction fetch of step S4, the central processing unit 3 gives an instruction prefetch command to the cache and prefetch control circuit 26 at a timing when the bus access by the central processing unit 3 is not performed. For example, the instruction address of the program counter 30 at that time is incremented by one cache line in the counter 273, and the updated address information (stored in the address register 27 is stored in the address register 27 during a period in which there is no bus access by the central processing unit 3. The operation of instruction prefetch is started based on the above. (Step S
5). The processing when there is an instruction for instruction prefetch will be described later with reference to FIG.

When a cache miss occurs in the instruction cache memory, the result of hit determination in the instruction prefetch buffer is referred to. That is, in the instruction prefetch buffer, the valid bit Vb indicates whether or not a valid instruction has already been read into the buffer data unit 23 that can store an instruction for one cache line. When the valid bit Vb is true (logical value “1”), the prefetch buffer tag BTAG and index ID of the buffer address section 24
X is the program counter 30 in the buffer comparison circuit 25.
Address tag ATAG and index IDX. When the comparison result is a match (step S2 = YE
S, and step S3 = NO), the cache and prefetch control circuit 26 is notified by the signal 251 that the necessary instruction exists in the buffer data unit 23, and the cache and prefetch control circuit 26 uses the word WRD of the program counter 30. 230 based on the information of
And transfers the required instruction selected by the selector 230 to the central processing unit 3 via the bypass path 231 (step S7), and the instruction is fetched into the instruction register 31.

At this time, even if the valid bit Vb is true, if the instruction prefetch buffer is reading an instruction from the external main memory 6, that is, if the read completion bit C is false (logical value "0"), the cache The prefetch control circuit 26 transfers the relevant instruction to the central processing unit 3 after the completion of reading the 8-word data in step S6. When prefetching the instruction of the first word from the main memory 6 to the buffer data section 23 of the instruction prefetch buffer, the cache and prefetch control circuit 26 initializes the read completion bit C to false (logical value "0"). The cache and prefetch control circuit 26 has means for counting the number of word data written to the buffer data unit 23 of the instruction prefetch buffer, and the count value is 8
Read completion bit C is true (logical value "1")
Set to.

The 8-word instruction prefetched from the main memory 6 to the buffer data section 23 of the instruction prefetch buffer is written to the corresponding cache line in the cache data section 20 of the instruction cache memory (step S8), The valid bit Vc in the cache address portion 21 is true (logical value "1" = O
N) and the contents of the buffer tag BTAG of the buffer address unit 24 are set in the cache tag CTAG. Then, the valid bit Vb in the buffer address portion 24 of the instruction prefetch buffer is false (logical value "0").
= OFF) (step S9). This prevents subsequent hits in both the instruction cache memory and the instruction prefetch buffer. Then, similarly to the above, the instruction prefetch is instructed (step S1).
0).

When writing the contents of the instruction prefetch buffer to the instruction cache memory, the corresponding cache line is selected using the information of the index IDX held by the buffer address section 24. Further, in a set associative instruction cache memory of two or more ways, it is necessary to control which way the instruction string of the instruction prefetch buffer is written. be able to. This is a logic for weighting when replacing the data part of a cache line, and is used to indicate the most recently referenced cache line. Therefore, when replacing the data part, the cache line not specified by the LRU is targeted for replacement.

When a cache miss occurs in the instruction cache memory and a buffer miss occurs in the instruction prefetch buffer (step S2 = NO), the central processing unit 3 cannot execute the instruction until the necessary instruction is read from the main memory 6. Therefore, the instruction prefetch operation is immediately started. That is, the cache and prefetch control circuit 26 starts the operation of prefetching an instruction from the main memory 6 based on the value of the address register 27 (the instruction address of the program counter 30) (step S
12). As a result, when the instruction at the address to be fetched is read, the word W of the program counter 30 is read.
The selector 230 is controlled based on the information of the RD, and the instruction selected by the selector 230 is the bypass path 2
It is transferred to the central processing unit 3 through 31 and the instruction is fetched into the instruction register 31 (steps S13, S).
14). In this embodiment, the instructions required by the central processing unit 3 are first read from the main memory 6. That is, 8-word instructions are burst-transferred from the main memory 6 starting with the instruction at the address to be fetched in order to reduce the miss hit penalty of the central processing unit 3. Therefore, in the control flow of FIG. 3, only the first one-word instruction read into the instruction prefetch buffer is bypass route 23.
The data is transferred to the central processing unit 3 via 1. Furthermore, if the instruction prefetch buffer is reading an instruction from the external main memory 6 (read completion bit C is false), the operation of the instruction prefetch buffer is stopped (read completion) to simplify the transaction of the external bus. The fetch operation is started (step S11).

[Invocation of Instruction Prefetch Based on Interrupt] The instruction prefetch instruction shown in FIG. 3 is generated due to the instruction fetch instruction according to the value of the program counter 30. Other instruction factors of the instruction prefetch include the instruction prefetch instruction of the interrupt processing program given to the cache and prefetch control circuit 26 by the signal 406 from the interrupt control circuit 4 upon acceptance of the interrupt as described above. The instruction prefetch command is generated in step S56 or S57 in FIG. 5 or step S63 in FIG. Details of FIGS. 5 and 6 will be described later.

[Control Procedure of Instruction Prefetch] FIG. 4 shows a control procedure by the cache and prefetch control circuit 26 when the instruction of the instruction prefetch is received. When there is an instruction prefetch instruction, it is determined whether the instruction is an instruction prefetch (interrupt prefetch) instruction from the interrupt controller 4 or an instruction prefetch (normal prefetch) instruction at the instruction execution stage by the central processing unit 3 ( Step S41). In the case of normal prefetch, the output of the counter 273 or the output of the program counter 30 is selected as the instruction prefetch address and set in the address register 27. The instruction prefetch address set in the address register 27 is supplied to the instruction cache memory and the instruction prefetch buffer (step S42). In the case of interrupt prefetch, the interrupt processing start address from the interrupt control circuit 4 is selected as the instruction prefetch address and set in the address register 27.
The instruction prefetch address set in the address register 27 is supplied to the instruction cache memory and the instruction prefetch buffer (step S43). A cache hit / miss and a buffer hit / miss are determined for the instruction prefetch address (step S44), and if the same instruction string already exists in the instruction cache memory or the instruction prefetch buffer, read from the main memory 6. Is suppressed (the instruction prefetch operation is ended) to prevent a wasteful transaction on the external bus (step S44 = YES).

If the same instruction sequence does not exist in the instruction cache memory and the instruction prefetch buffer (step S44 = NO), it is judged whether it is a normal prefetch (step S47). Determination (step S49 =
After waiting for "YES", the instruction for one line of the buffer data section 23 is read into the instruction prefetch buffer and started (step S45). In the case of normal prefetch (step S47 = YES), it is determined whether the prefetch buffer is in the read completion state by referring to the completion bit C (step S48). If it is in the completion state, the instruction prefetch buffer is read in step S45. Reading is started. If the prefetch buffer is not in the read completion state (step S48 = NO), the process is terminated without waiting for the completion of the reading of one line into the instruction prefetch buffer that has already started. If it waits until the reading is completed, the reading to the instruction prefetch buffer can be completed each time there is an instruction of the instruction prefetch from the central processing unit, but the responsiveness to the urgent processing request (for example, interrupt request) that occurs during that Be lowered. Further, even if it is not necessary to wait for the completion of the reading of one line to the already started instruction prefetch buffer, as is clear from the flowchart of FIG. Is generated, so there is no inconvenience. In the case of interrupt prefetch, the reason why the instruction prefetch buffer is read after waiting for the determination of step S49 = YES is to prioritize the prefetch of the interrupt processing program and improve the responsiveness to the interrupt. Therefore, in the case of the interrupt prefetch, the instruction read based on another instruction of the instruction prefetch is not started, and the interrupt prefetch is always performed, so that the responsiveness to the interrupt is improved.

In the process of step S45, the value of the address tag ATAG of the address register 27 is set in the prefetch buffer tag BTAG of the instruction prefetch buffer, and the instructions are burst read from the external main memory 6 at the instruction prefetch address of the address register 27. It is a process to start. At that time, the valid bit Vb of the instruction prefetch buffer is set to true (logical value “1”) and the read completion bit C is set to false (logical value “0”), indicating that the instruction prefetch buffer is in operation (step S46). . The read completion bit C of the instruction prefetch buffer
Is true when the instruction sequence for one line is read (logical value "1")
Is set to indicate that the read operation is completed.

In FIG. 4, the instruction reading for one line of the interrupt processing program in the case of the interrupt prefetch (step S45) is performed within the interrupt transition period of the central processing unit 3 shown in FIG. In the present embodiment, the instruction prefetched from the main memory 6 can be transferred to the program counter 30 at least after the instruction of 8 words is read into the buffer data unit 23 for the sake of simplification of control. This depends on step S6. Therefore, in the case of the present embodiment, when the CPU transits to the interrupt processing for the first time after the interrupt transition period longer than the memory cycle time necessary for burst transfer of the 8-word instruction from the main memory 6 to the data buffer unit 23 exists. With, the instruction of the interrupt processing program can be fetched without disturbing the pipeline. However, if the storage capacity of the data buffer unit 23 is small (the line length of the cache line is short), the minimum period required for instruction prefetch of the interrupt processing program also becomes short. Further, in the interrupt transition control, if a process of changing the interrupt completion bit C to the true value is added immediately before the start address of the interrupt processing program is set in the program counter 30, step S6 of FIG. 3 is substantially ignored. Even if the 8-word instruction prefetch is not completed during the interrupt transition period, the head instruction of the interrupt processing program can be fetched into the program counter 30 in step S7. However, although not shown, it is needless to say that control for adjusting the timing of interrupt completion is substantially required in step 8.

[Control of Interrupt Control Circuit When Interrupt Occurs] FIG. 5 shows the interrupt control circuit 4 when an external interrupt occurs.
The control flow of is shown. The interrupt control circuit 4 receives external interrupt request signals 401 and 402 from the peripheral circuits 7 and 8. At this time, the interrupt control circuit 4 uses a plurality of peripheral circuits 7,
When an external interrupt is received from 8 at the same time, an interrupt priority determining circuit (not shown) and a reception mask circuit corresponding to a request signal are provided in order to judge which of them is accepted. Then, it is determined which external interrupt is accepted based on the information set in these circuits (step S5).
0).

If an external interrupt is accepted (step S51 = YES), the interrupt control circuit 4 gives an interrupt signal 405 to the central processing unit 3 to instruct to interrupt the current program execution and shift to interrupt transition control. Yes (step S52). As a result, the central processing unit 3 shifts to the interrupt transition control of FIG. 7, which will be described later, and starts the current program execution stop and save processing for returning from the interrupt processing program.

The interrupt control circuit 4 performs the following processing in parallel with the interrupt transition control by the central processing unit 3. That is, the interrupt control circuit 4 determines whether to receive the start address of the interrupt processing program from an external peripheral circuit or to use the value stored in the table 40 according to the interrupt request source (step S53). In the former case, the interrupt start address is supplied from the register 71 of the peripheral circuit 7.
The latter corresponds to the peripheral circuit which does not have such an interrupt start address supply function. This determination can be made by a method such as giving meaning to the information added to the external interrupt request signal or the terminal receiving the external interrupt request signal. The setting of the interrupt start address in the table 40 and the register 71 can be performed at the time of starting the system shown in FIG. 1 and FIG. Alternatively, another method such as storing a fixed value can be adopted.

When the start address of the interrupt processing program is received from the peripheral circuit 7 (step S53 = YES),
The interrupt control circuit 4 informs the peripheral circuit 7 of the request source from which peripheral circuit the external interrupt is received by the external interrupt response signal 403 (step S54). On this occasion,
The response signal 403 includes a protocol for the interrupt control circuit 4 to receive information for identifying a peripheral circuit, information indicating an external interrupt factor, and the start address of the interrupt processing program (prompt acceptance or completion of acceptance). The response from the peripheral circuit can be improved by adding a series of procedures such as for indicating.

When the interrupt control circuit 4 receives the start address of the interrupt processing program from the peripheral circuit (step S55 = YES), this address is transferred to the central processing unit 3 and the address register 27, and is sent to the cache and prefetch control circuit 26. Is instructed by the signal 406 to fetch the instruction of the interrupt processing program (step S5).
6). The address transferred to the address register 27 is
It is used as a prefetch address for prefetching the first instruction of the interrupt processing program. The address transferred to the central processing unit 3 is used as an address for fetching the first instruction of the interrupt processing program into the instruction register 31 after the interrupt transition period. As a result of the instruction fetch of the interrupt processing program being performed by the cache and prefetch control circuit 26 during the interrupt transition control period by the central processing unit 3, the instruction of the interrupt processing program to be fetched in the instruction register 31 has already been written in the instruction cache memory. Alternatively, the situation in which the main memory 6 is read from the beginning when the interrupt processing program is executed since it is read in the instruction prefetch buffer is almost eliminated.

For the peripheral circuit 8 that does not have an interrupt start address register itself, the same process as above is performed by using the address information stored in the register such as the table 40 of the interrupt control circuit 4. Is performed (step S53 = NO).

FIG. 6 shows a control flow of the interrupt control circuit 4 when an internal interrupt occurs. The internal interrupt is an interrupt that occurs when the central processing unit 3 executes a program, and occurs when an error occurs during the program processing or a predetermined event occurs in an internal timer or the like. The basic processing contents are the same as those in FIG. 5, except that the interrupt start address is given from the interrupt control circuit 4 and the interrupt response signal 405 returns to the central processing unit 3 that it corresponds to the internal interrupt request. Since the other points are realized in steps S60 to S63 similar to FIG. 5, detailed description thereof will be omitted.

[Processing During Interrupt Transition Period by Central Processing Unit] FIG. 7 shows an example flowchart of the processing (interrupt transition control) during the interrupt transition period of the central processing unit 3. The processing shown in the figure is such that the internal information for returning from the interrupt processing program and the value of the program counter are saved, the internal initialization for transition to the interrupt processing program, and the start address of the interrupt processing program are programmed. The processing is set in the counter 30. That is, when the central processing unit 3 is notified of the interruption acceptance by the signal 405, first, the current program execution is stopped, and the internal information of the central processing unit 3, such as the processor status word (PSW) of the status register, is sent to the data processor. 1 is saved inside or outside, and the PSW is initialized (step S70). Next, as the return address from the interrupt process, the value of the program counter 30 or a value before and after the value (depending on whether the process after the recovery is a continuation process from the interrupted process or is re-executed from the beginning).
Is saved inside or outside the data processor 1 (step S71). Then, the privilege level is changed to the highest level if necessary (step S72). Then, the information related to the interrupt, for example, the interrupt factor analysis information, and the values of other registers necessary for returning from the interrupt are saved internally or externally (step S73). The respective save destinations are the save counter 34 that makes a pair with the program counter or the PSW register, the external main memory 6, the built-in data cache memory, or the like. After the processing is completed, on condition that the interrupt start address is supplied from the interrupt control circuit 4 (step S74 = YES),
The interrupt start address from the interrupt control circuit 4 is given to the program counter 30, and a transition is made to the interrupt processing program (step S75). Step S described in FIG.
The period from 70 to "end" is the interrupt transition period of the central processing unit 3.

[Non-Blocking Cache] FIG. 8 is a block diagram for explaining the configuration of a non-blocking cache not shown in FIG.
In FIG. 8, ICACHE is the instruction cache memory described in FIG. 1, IPB is the instruction prefetch buffer described in FIG. 1, DCACHE is a data cache memory, W
BB is a write back buffer and RB is a read buffer. Input of instruction prefetch buffer IPB, output of write back buffer WBB, and read buffer RB
Is connected to the external data bus EDB via the external interface 55. Instruction prefetch buffer IP
B, read buffer RB, and write back buffer W
BB functions as a buffer unit for preventing the operations of the instruction cache memory ICACHE and the data cache memory DCACHE from being suppressed,
In that sense, the configuration of the cache memory shown in FIG. 8 is a non-blocking cache, and since the cache memory is physically separated for instructions and data, it is positioned as a Harvard architecture type non-blocking cache. Other configurations are not shown, but they are exactly the same as the configurations described in FIGS. 1 and 2. In such a configuration, the central processing unit 3
Is fetching an instruction from the instruction cache memory ICACHE, the instruction can be prefetched into the instruction prefetch buffer IPB in parallel with this. Further, when the instruction is prefetched to the instruction prefetch buffer IPB, the data cache memory DCACH
Data can be accessed via E. For example, write-back for maintaining data consistency (coincidence) with the main memory 6 is performed via the write-back buffer WBB in consideration of the timing when the bus is vacant. Can be done from Further, there are many cases in which the main memory 6 is not accessed and only the data cache memory DCACHE is accessed even in the saving process when an interrupt occurs.

FIG. 9 shows another example of the non-blocking cache. The example shown in the figure is a case where a unified cache memory that stores instructions and data in the same cache memory is adopted. In FIG. 9, UCAC
The HE is a cache memory that has the configuration of the instruction cache memory described in FIG. 1 and is also used as the data cache memory. RB is a read buffer, WB1 is a first write buffer, and WB2 is a second write buffer. In this case, the function of the instruction prefetch buffer IPB of FIG. 8 is realized by the read buffer RB. The read buffer RB and the write buffers WB1 and WB2 function as buffer means for preventing the operation of the unified cache memory UCACHE, and in that sense, the cache memory configuration shown in FIG. 9 is also the same. It is a non-blocking cache. In that case, the write buffer WB2 is not always necessary. Other configurations are not shown in FIG.
The configuration is the same as that described with reference to FIG. In such a configuration, when the central processing unit 3 is fetching an instruction from the unified cache memory UCACHE, the instruction can be prefetched to the read buffer RB in parallel with this. Further, while prefetching an instruction into the read buffer RB, data access via the unified cache memory UCACHE can be performed to the write buffers WB1 and WB2, and for example, data matching with the main memory 6 ( The write back for maintaining the (match) can be performed later via the first write buffer WB1 in consideration of the timing when the bus is vacant. In addition, there are many cases in which the main memory 6 can be written in the write buffers WB1 and WB2 in advance without accessing the main memory 6 even in the saving process when an interrupt occurs.

[Single Chip Microcomputer]
FIG. 10 shows an embodiment in which the data processor described in FIG. 1 is further expanded to another data processor, that is, a microcomputer and a data processing system. The part shown as MCU in FIG. 10 can be configured as a single chip microcomputer on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In FIG. 10, the cache and prefetch control circuit 2, the central processing unit (CPU) 3, the interrupt control circuit 4, and the main memory 6 are equivalent to the circuit module described in FIG. In FIG. 10, the main memory 6 includes a RAM and a ROM. A cache memory device indicated by 900 is a circuit block including the instruction prefetch buffer and the instruction cache memory described in FIG. Besides, a data cache memory and a write back buffer may be included. In addition, another cache memory device 90
1 may be provided. Other circuit modules include a hard disk device 910 and a floppy disk device 91.
1, a file control device 909 for controlling the number 1, a display control device 912 for performing drawing control for the frame buffer 913 and a display control for the monitor 914, and a bus right monitoring device 90.
2. A high-speed data transfer device 903 such as a direct memory access controller, a system monitoring device 905, a communication interface device 906, peripheral devices such as a parallel / serial port 915 interfaced with a printer 916 and a keyboard 917, and an input / output controller 904. And memory controller 908
And so on. The cache memory device 900, 90
1 is a relatively small capacity for reading a part of information in a large-capacity storage device (main memory 6 including RAM and ROM, hard disk device 910, floppy disk device 911, etc.), but instructions and data compared to a large-capacity storage device. To allow fast access.

According to the above embodiment, the following operational effects are obtained. [1] The central processing unit 3 saves the value of the program counter 30, the value of the status register 33, and the like by hardware from the occurrence of the interrupt until the program is switched to the interrupt process, and further saves necessary information. After that, the interrupt processing program is executed. When pipeline processing is adopted, it is also necessary to save various types of information in order to minimize disturbance of the pipeline due to interrupts before transitioning to the interrupt processing program. The data processor 1 prefetches the instruction of the interrupt processing program in parallel with the period of such interrupt transition control by the central processing unit 3. The instruction address to be prefetched is given from the interrupt control circuit 4 to the address register 27, and the instruction of the prefetch operation using the value of the address register 27 is given from the interrupt control circuit 4 to the cache and prefetch control circuit 26. The memory access required for prefetching the interrupt processing program is performed when the bus is free during the interrupt transition period (when the central processing unit 3 is not accessing the bus). According to the present embodiment, the central processing unit 3 has the save register 34, and the data cache memory DCAC
Since the non-blocking cache memory including the HE and the write-back buffer WBB is adopted, when the internal state of the central processing unit 3 is saved, the main memory 6 is saved by saving certain information in the save register 34. Access to the main memory 6 can be omitted when the data cache memory DCACHE is a cache hit at the time of saving. Further, even if a cache miss occurs, the write back buffer W can be omitted.
By the action of BB, the writing back to the main memory 6 at the time of exchanging the entries can be postponed. In this way, during the interrupt transition control period, the instruction of the interrupt processing program can be prefetched depending on the vacant timing of the bus while the main memory 6 is not accessed by the central processing unit 3.

[2] During the interrupt transition period of FIG. 7, instruction prefetch (interrupt prefetch) based on an interrupt request is performed in parallel. That is, the interrupt processing program is prefetched through the gap where the central processing unit 3 is performing interrupt transition control. Therefore,
It is possible to prefetch the instruction even for an interrupt processing program whose execution start time is difficult to predict. If the instruction of the interrupt processing program is prefetched into the buffer data unit 23 of the instruction prefetch buffer, the instruction fetch for transitioning to the interrupt processing program can be fetched from the buffer data unit 23 of the instruction prefetch buffer in step S75 of FIG. From the start of execution of the interrupt processing program, the performance of the instruction cache memory and the instruction prefetch buffer can be fully utilized to speed up the interrupt processing.

[3] When the instruction cache memory is composed of the cache data unit 20, the cache address unit 21, and the cache comparison circuit 22, the instruction prefetch buffer includes the buffer data unit 23, the buffer address unit 24, and the buffer data unit 23. , And the buffer comparison circuit 25, the instruction prefetch buffer can be prefetched under the same control as the line fetch for one cache line in the instruction cache memory. At this time, the cache and prefetch control circuit 26 responds to the instruction prefetch command by the cache comparison circuit 22.
The instruction prefetch to the instruction prefetch buffer is activated by detecting the mismatched comparison results from both the buffer comparison circuit 25 and the buffer comparison circuit 25 (step S44 = NO), and substantially unnecessary prefetch is not performed. The contents of the prefetch-completed instruction prefetch buffer are written into the cache memory by detecting the comparison result of the coincidence in the buffer comparison circuit 25 at the time of accessing the instruction after the completion of the instruction prefetch to the instruction prefetch buffer (step S8). . As a result, it is possible to eliminate the inconvenience of erasing an existing cache entry from the instruction cache memory by an instruction that does not result in a buffer hit and is not used even if prefetched into the instruction prefetch buffer. For such a prefetch mechanism, the interrupt control circuit 40
When an interrupt request is accepted, a command 4 for prefetching an instruction in the instruction prefetch buffer based on the start address information of the processing program for responding to the request
06 is given to the cache and prefetch control circuit 26, so that the prefetch is performed based on the interrupt start address, so that the above-described operation and effect can be obtained without requiring many modifications and additional circuits in the conventional cache memory. be able to.

[4] In addition to the central processing unit 3, the interrupt control circuit 4 is added as an instruction prefetch instruction generation source. Selector means 271, 272 for providing the address register 27 with one address selected from the start address of the interrupt processing program, the value of the program counter 30, and the prefetch address generated based on the value of the program counter 30, The cache and prefetch control circuit 26 causes the selecting means to select the value of the program counter 30 by detecting the mismatched comparison result from both the cache comparison circuit and the buffer comparison circuit in response to the instruction fetch instruction, and the instruction prefetch When the instruction generation source is the interrupt control circuit 4, the selection means 271, 272 is caused to select the start address of the interrupt processing program, and the instruction generation source is the central source for the instruction prefetch command. In the case of the processing device 3, the selection means 27 , 272 by selecting the prefetch address generated based on the value of the program counter 30, the address register 27 holding the instruction access address for instruction fetch and instruction prefetch It can be shared with the instruction fetch along with the command.

[5] By storing the interrupt start address in the rewritable table 40 or register 71 by the central processing unit 3, the degree of freedom for mapping the interrupt processing program can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes. For example,
The instruction prefetch buffer can be configured with a storage area for a plurality of cache lines of the instruction cache memory.
The configuration of the cache memory is not limited to the above embodiment and can be modified in various ways.

[0070]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

During the interrupt transition period from the occurrence of the interrupt to the execution of the interrupt processing program by the central processing unit, the interrupt control circuit outputs the start address of the interrupt processing program to the prefetch and cache control circuit. Instructs program prefetch. With this, the prefetch and cache control circuit can prefetch the interrupt processing program in parallel with the period of the interrupt transition control by the central processing unit. Memory access is required for instruction prefetch of the interrupt processing program. Such memory access is realized in a bus cycle during the interrupt transition control by the central processing unit. Such an empty cycle of the bus is provided, for example, by providing a data cache memory, or by configuring a non-blocking cache having a buffer in the data cache memory, and further, the central processing unit has a save register built-in or a bank register. Guaranteed by configuration. By prefetching the instructions of the interrupt processing program in this manner, the performance of the instruction cache memory and the instruction prefetch buffer can be fully utilized from the start of execution of the interrupt processing program, and high-speed data processing can be realized. Furthermore, since the prefetch is performed based on the interrupt start address, the conventional cache memory does not require many modifications and additional circuits, in other words, the cost increase is suppressed and the above effect is obtained. be able to.

[Brief description of drawings]

FIG. 1 is a partial block diagram of a data processor according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a system configuration example using the data processor of FIG.

FIG. 3 is a flowchart of an example of a basic control mode of instruction fetch and prefetch activation based on an instruction fetch instruction from a central processing unit.

FIG. 4 is a flowchart showing an instruction prefetch control procedure.

FIG. 5 is a control flowchart of an example of an interrupt control circuit when an external interrupt occurs.

FIG. 6 is a control flowchart of an example of an interrupt control circuit when an internal interrupt occurs.

FIG. 7 is a flowchart of an example of pre-interruption processing of the central processing unit.

FIG. 8 is a block diagram for explaining a configuration of a non-blocking cache, which is not clearly shown in FIG. 1, as a representative of Harvard architecture.

FIG. 9 is a block diagram showing another example of a non-blocking cache using a unified cache memory.

FIG. 10 is a block diagram of an embodiment when the data processor described in FIG. 1 is further developed to another data processor or microcomputer and a data processing system.

FIG. 11 is a block diagram of an example of a central processing unit.

[Description of Codes] 1 data processor 2 instruction cache / prefetch unit 20 cache data unit 21 cache address unit CTAG cache tag Vc valid bit 22 cache comparison circuit 23 buffer data unit 24 buffer address unit BTAG buffer tag Vb valid bit C read completion bit 25 buffer comparison circuit 26 cache and prefetch control circuit 27 address register ATAG address tag IDX index WRD word 3 central processing unit 30 program counter 4 interrupt control circuit 40 table 401, 402, 404 interrupt request signal 405 interrupt signal 406 interrupt acceptance signal 6 main Memory 7 Peripheral circuit 8 Peripheral circuit IPB Instruction prefetch buffer ICACHE Instruction cache memory WB B write back buffer DCACHE data cache memory RB read buffer WB1, WB2 write buffer UCACHE unified cache memory

Claims (10)

[Claims] 1. A central processing unit that executes instructions, an instruction prefetch buffer that prefetches the instructions, an instruction cache memory that holds the prefetched instructions, and an instruction that responds to an instruction fetch address in response to an instruction fetch instruction. A cache and prefetch control circuit that performs control for acquiring from the prefetch buffer, the instruction cache memory, or the outside, and an instruction corresponding to the instruction prefetch address in response to the instruction of the instruction prefetch from the outside, and a prefetch control circuit; When a request is accepted, an interrupt control circuit for giving an instruction for prefetching an instruction to the instruction prefetch buffer to the cache and the prefetch control circuit based on the start address information of the processing program for responding to the request is provided. A data processing device characterized in that it is made up of 2. The central processing unit during a transition control period from when the central processing unit receives a notice of acceptance of an interrupt from the interrupt control circuit until when the central processing unit starts execution of a processing program that responds to the interrupt request. 2. The data processing device according to claim 1, further comprising a data storage unit used for saving the internal state of the device, which is formed on one semiconductor substrate as a whole. 3. The data processing apparatus according to claim 2, wherein the data storage means is a data cache memory, and a write back buffer is provided between the data cache memory and the outside. . 4. The interrupt control circuit supplies start address information of a processing program for responding to an interrupt request accepted by the interrupt control circuit to an address register, and the cache and prefetch control circuit supplies the address held in the address register. 4. The data processing device according to claim 1, wherein the instruction prefetch is performed based on information. 5. The interrupt control circuit is provided with a table for storing the start address information of the processing program for responding to the interrupt request in association with the interrupt factor, and when accepting the interrupt request, responding to the factor of the request. The data processing device according to claim 4, wherein address information is supplied from the table to the address register. 6. The interrupt control circuit further receives the start address information of a processing program for responding to the interrupt request from the peripheral circuit of the accepted interrupt request source, and supplies it to the address register. The data processing device according to claim 5, wherein 7. The data processing device according to claim 5, wherein the table is rewritable by the central processing unit. 8. A central processing unit that executes instructions, an instruction prefetch buffer that prefetches the instructions, an instruction cache memory that holds the prefetched instructions, and an instruction that responds to an instruction fetch address in response to an instruction fetch instruction. The prefetch buffer, the instruction cache memory, or a cache and a prefetch control circuit that performs control to obtain from the outside and perform control to obtain an instruction corresponding to an instruction prefetch address from the outside to the prefetch buffer in response to an instruction of the instruction prefetch. The instruction cache memory includes a cache data section for storing a plurality of instructions of a predetermined number of words as one data block, a cache address section for associating an instruction of the cache data section with its instruction address, and an instruction access unit. And a cache comparison circuit that detects whether or not a part of the address matches the address information of the cache address section, and the instruction prefetch buffer has a number of instructions equal to the number of instruction words of one data block of the cache data section. Can be stored as one data block, a buffer address part for associating an instruction in the buffer data part with its instruction address, and whether part of the instruction access address matches the address information in the buffer address part. A cache comparison circuit that detects whether or not the cache and prefetch control circuit detects an instruction by detecting a mismatched comparison result from both the cache comparison circuit and the buffer comparison circuit in response to the instruction prefetch command. Instruction pref to prefetch buffer When the interrupt request is accepted, an instruction to prefetch an instruction to the instruction prefetch buffer based on the start address information of the processing program for responding to the request is issued to the cache and prefetch control circuit. A data processing device comprising: an interrupt control circuit provided to the device. 9. The prefetch-completed instruction prefetch buffer by detecting a comparison result of a match in the buffer comparison circuit at the time of instruction access to the instruction prefetch buffer after the instruction prefetch is completed. 9. The data processing device according to claim 8, wherein the contents of the above are controlled to be written in a cache memory. 10. An address register for holding an instruction access address for instruction fetch and instruction prefetch, and a start address of an interrupt processing program, a value of a program counter, and a prefetch address generated based on the value of the program counter. Selecting means for giving one address selected from the address register to the address register, and the cache and prefetch control circuit is a comparison result of a mismatch from both the cache comparison circuit and the buffer comparison circuit in response to an instruction fetch command. By causing the selection means to select the value of the program counter,
For the instruction prefetch command, if the instruction factor is the interrupt control circuit, the selecting means is caused to select the start address of the interrupt processing program, and the instruction factor is the central processing unit for the instruction prefetch command. 10. The data processing device according to claim 8 or 9, characterized in that the selection means is made to select the prefetch address generated based on the value of the program counter.