JPH0214571A - Solid-state image pick-up device - Google Patents

Abstract

PURPOSE:To prevent deterioration in transfer efficiency at the time of the large signal output and the saturation output disunity of a photodiode by providing a means for impressing a timing pulse, in which the potential under a reset gate may be higher than the potential under an output gate in the timing where electric charge is stored in the charge detection part. CONSTITUTION:A reset pulse to be impressed on a reset gate is not RS itself but RS' where its level is changed by a level converter 9. A low level value is set up higher than 0 in the pulse RS' to be impressed on the reset gate. A high level is impressed on the reset gate in the timing (a) corresponding to a reset mode for being in a state of charge sweeping-out. Further, a low level is impressed on the reset gate in the timing (b) corresponding to a charge storage mode and this low level is higher set than OV so that the potential under the reset gate is higher set up than the potential under the OG gate. Consequently, the maximum storage charge amount QF.Jmax of the FJ part is restricted by the potential under the reset gate 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a solid-state imaging device, and more particularly to a solid-state imaging device having a signal charge detection section.

(Prior Art) FIG. 8 is a sectional view showing a partial configuration of a conventional solid-state imaging device having a charge detection section.

A charge transfer section for transferring signal charges is formed by forming an n-type impurity layer 3.4 on the surface of a p-type semiconductor substrate 10, and forming a transfer electrode 7.7' on the layer with an insulating layer 9 interposed therebetween. is forming.

In addition, the high concentration n-type impurity layer 1' constitutes a floating junction type charge detection section (hereinafter referred to as FD) for temporarily accumulating and detecting signal charges transferred from the charge transfer section, and detects the detected signal. is the output signal O via buffer 8
8. The n-type impurity layer 3' is formed between the n-type impurity layer 4 of the charge transfer section and the high concentration n-type impurity layer 1', and together with the electrode 6 (hereinafter referred to as OG agate) formed thereon, it forms the output gate section. , and functions as a final gate to transfer signal charges transferred from the charge transfer section to the FD. Further, this portion serves as a barrier for accumulating signal charges at the boundary with the FD (hereinafter referred to as the FJ portion).

The detected signal charge is swept out through the n-type impurity layer 2 to the high concentration n+ type impurity layer 1 (hereinafter referred to as a reset drain) to which a voltage RD is applied by operating the electrode 5 (hereinafter referred to as a reset gate).

FIG. 9 is a potential diagram of the portion Xl-X2 shown in FIG. 8, and FIG. 10 is a timing chart showing the timing of pulses applied to the reset gate 5 and transfer electrodes 7, 7'. Note that the method of driving the charge transfer section in this case is two-phase drive, where φH1' and φH2 are pulses applied to the transfer electrodes 7 and 7', and R8 is a reset pulse applied to the reset gate 5.

FIG. 9(a) shows the timing when a high-level pulse is applied to the reset gate 5 at timing a in FIG. 10, that is, the state at the time of charge sweeping. At this time,
The potential under the reset gate 5 must be higher than the voltage applied to the reset drain 1 for reliable charge sweeping.

Figure 9(b) shows the FJ at timing b in Figure 10.
Q in the figure shows a state in which charge is accumulated in the area.
F, Jmax indicates the maximum charge storage capacity of the FJ section.

In this way, in the conventional solid-state imaging device, in the charge accumulation state shown in FIG. 9(b), the potential under the OG agate is formed higher than the potential under the reset gate 5. As shown in the figure, the maximum accumulated charge iQ is limited by P, Jmax due to the potential under the OG agate, and if the transferred signal charge QT exceeds the maximum accumulated charge amount Q, P, Lmax QQ The charge flows back into the charge transfer section and the remaining T-F
, Jmax is performed. That is, FIG. 11 shows a state in which a signal charge Q having a charge amount of P, Jmax, which is larger than the maximum accumulated charge amount Q, is transferred to the FJ section at timing b shown in FIG. 10, and FIG. At timing C shown in FIG. 10, charges of QQ are left behind in the charge transfer section T-P and Jmax, respectively.

When such residual charges occur, the transfer efficiency appears to be degraded, and in the case of an area sensor, for example, horizontal flow of images occurs, resulting in a significant deterioration of image quality.

In addition, when there are multiple signal charges, for example, the signal charges photoelectrically converted by two-dimensionally arranged photodiodes are sequentially transferred by a transfer means within a predetermined period, and these are detected in a charge detection section in the conventional manner. In this case, if there are variations in the saturation charge amount of each of the plurality of photodiodes, and the saturation output of all or some of them is less than the maximum accumulated charge amount Q, then F, Jmax Uniform light stronger than the original that reaches the smallest saturation charge Q among diodes is 5ATa+i
n, which causes unevenness in the output.

FIG. 13 shows the output waveform during a predetermined period (reading period) in which output unevenness occurs in such a state. As shown in the figure, the photoder 5ATIl+nSATm including the saturated output voltage V, (output voltage of Q)
The saturation output voltage of in iode is V(Q)F
, Jmax P, Jsax (output voltage), the output waveform is uneven. When such an output is output to a monitor or the like, when strong light is incident, unevenness occurs depending on the position, resulting in an extremely unsightly image.

In addition, regardless of the signal charge, if the maximum value output to the outside of the device is large and exceeds the input tolerance of an external circuit such as a signal processing circuit outside the device, the input tolerance will be exceeded. Even normal waveform parts may be affected. Therefore, if the external circuit is designed with a margin such that the allowable input value is larger than the maximum output value in order to reduce such influence, problems such as increased power consumption of the circuit occur.

FIG. 14 shows the input/output characteristics of a general external circuit. Here, V represents the input permissible amplitude value, which is the point at which the output is saturated and no longer increases even with N5AT as the input increases.

Further, FIG. 15(a) shows an output waveform of a conventional device inputted to an external circuit, and FIG. 15(b) shows an output waveform of the external circuit. When an output equal to or higher than the input permissible amplitude value V as shown in Fig. 15(a) is input to the external N5AT circuit, the human power permissible amplitude value V Output N5AT Even if the normal output is below, the input permissible amplitude value V or less is N5
Development occurs where the waveform is disturbed due to the influence of the output on the AT.

The present invention was made to solve the above problems, and
It is an object of the present invention to provide a solid-state imaging device that is free from deterioration in transfer efficiency when a large signal is output, which occurs in a charge detection section of the solid-state imaging device, and which is free from uneven saturation output of a photodiode.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a floating junction type charge detection section that temporarily stores and detects signal charges transferred from a charge transfer section via an output gate, and a floating junction type charge detection section that is adjacent to the charge detection section and detects the signal charges transferred from the charge transfer section through an output gate. In a solid-state imaging device including a charge discharging section that discharges signal charges temporarily accumulated in the detection section via a reset gate at a predetermined timing, when the charge is accumulated in the charge detection section, the signal charge under the reset gate is Means is provided for applying a timing pulse such that the potential is higher than the potential under the output gate.

Further, it is preferable that the maximum amount of charge accumulated in the charge detection section is equal to or less than the minimum amount of charge generated from a plurality of pixels.

(Function) In the solid-state imaging device of the present invention, the potential under the reset gate is set higher than the potential under the output gate at the storage timing in the charge storage section.
A situation in which excess transferred charges flow back into the charge transfer section and remain behind does not occur.

When the amount of accumulated charge is set below the minimum amount of charge from a plurality of pixels, saturation output unevenness does not occur.

(Example) Embodiments of the present invention will be described in detail below based on the drawings.

FIG. 1 is a schematic sectional view showing the configuration of a solid-state imaging device according to the present invention, and the same parts as in FIG. 8 are given the same numbers and detailed explanation thereof will be omitted.

In the configuration of FIG. 1, the reset pulse applied to the reset gate is not R3 itself shown in FIG.
This is changed in level by a level converter 9 to become R3'.

FIG. 2 is a waveform diagram showing the timing waveform of a pulse applied to the reset gate of the charge storage device according to the present invention.

As shown in the figure, the pulse R applied to the reset gate
Unlike the conventional case, the low level value of S' is set higher than 0.

Figures 3 (a) and (b) respectively show the potential during the timing pulse shown in Figure 2. At timing a, which corresponds to the reset mode, a high level is applied to the reset gate, and the charge is swept out. It is in.

Also, at timing b, which corresponds to the charge accumulation mode, a low level is applied to the reset gate, and as mentioned above, this low level is higher than OV, unlike in the past, so the potential under the reset gate is It is higher than the lower potential. Therefore, the maximum accumulated charge ff1Q, .

Figure 4 shows the value of the maximum accumulated charge IAQ with respect to the low level of the reset pulse as a graph.
x In the region A in the figure, the potential under the reset gate is lower than the potential under the OG agate, and the maximum accumulated charge mQ is constant regardless of the low level value of the reset P and Jiax reset pulses.

Region B is a region according to the present invention, where the potential under the reset gate is higher than the potential under the OG gate and lower than the voltage at the reset drain. As is clear from the figure, the maximum accumulated charge amount Q can be controlled by changing the low level of the reset pulse. Furthermore, the region C indicates a region where the potential under the reset gate is higher than the reset drain voltage, and the charge is always swept out, and no charge accumulation occurs.

By increasing the low level value of the reset pulse in this manner, the aforementioned conventional signal charges are not left behind, and image deterioration does not occur.

FIG. 15 shows the output waveform of the readout cycle when all of the plurality of photosensitive pixels reach a saturated state, and corresponds to FIG. 13. In the figure, V indicates the minimum output value of all outputs, and according to the present invention, the low level of the reset pulse is controlled, and the maximum accumulated charge amount Q is set to the minimum output P, which corresponds to the Jmax force value V. The amount of charge Q, which is equivalent to SAT
It is set to m r n 5ATl11n or lower. In this way, the maximum accumulated charge Q
Set the amount of charge Q to below P, Jmax
By using SATmtn, the output waveform becomes the 6th
As shown in the figure, = r = flat, and the saturation output unevenness for each pixel can be apparently eliminated, and the charge ff1Q
It is possible to eliminate the non-uniformity of the output that occurs when light stronger than the light reaching SATm 1 n is input to the pixel.

FIG. 7 shows a waveform diagram for explaining the effect when the solid-state imaging device according to the present invention is connected to an external circuit. As shown in Figure 7(a), the maximum accumulated charge Q
Let the value of the output value V be P, Jmax
N5A inputs an output of V or more to the external circuit from N5AT to control it to be equal to or lower than F, Jmax■
T. It prevents things from happening.

Therefore, as shown in FIG. 7(b), the output of the external circuit can be a good output without distortion, and the waveform disturbance that has been a problem with the conventional device can be eliminated.

In the embodiment described above, the maximum accumulated charge mQ
As a control method, the reset gate F, No IIa
Although a level conversion means was used to maintain a specific relationship between X and the width of the timing pulse applied to the output gate,
A similar effect can be obtained by forming the n-type impurity layer under the reset gate at a higher concentration than before.

The same effect can also be obtained by lowering the voltage applied to the OG gate or by forming the n-type impurity layer under the OG agate to have a lower concentration than the conventional one.

〔Effect of the invention〕

As explained above, according to the present invention, even if a charge exceeding the storage capacity of the charge detecting section is transferred, it is possible to prevent the generation of residual charge in addition to the transfer, thereby preventing image drift. In addition, by controlling the storage capacitance of the charge detection section, it is possible to prevent output unevenness due to uniform incidence of strong light due to variations in saturation output of pixels. Furthermore, it is possible to prevent disturbances in the external circuit output waveform of the maximum output value exceeding the input permissible value of the external circuit, and high image quality can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a partial configuration of a solid-state imaging device according to the present invention, FIG. 2 is a waveform diagram showing the timing waveform of an input pulse applied to the reset gate in FIG. 1, and FIG. timing a. 4 is a graph showing the relationship between the maximum accumulated charge amount and the low level of the reset pulse, and 5 and 6 are according to the present invention? I! A graph showing output waveforms from multiple pixels in a read cycle of a 1m storage device, FIG. 7 is a graph showing output waveforms of the device according to the present invention and an external circuit output waveform, and FIG. 8 is a cross-sectional structure of a conventional solid-state imaging device. Figure 9 is a potential diagram at the Xl-X2 portion shown in Figure 8, Figure 10 is a conventional manual pulse timing diagram, and Figures 11 and 12 show the problem of charge being left behind in the conventional device. Potential diagram, 1st
Figures 3 and 14 are output waveform diagrams showing conventional problems,
FIG. 15 is a graph of external circuit input/output characteristics in a conventional device. 1... Reset drain, 1'... Floating junction type charge detection section, 2. 3. 3'... impurity layer,
5...Reset gate, 6...OG agate 7.7
'... Transfer electrode, 8... Buffer, 9... Level converter, 10... P-type semiconductor substrate.

Claims (1)

[Scope of Claims] 1. A floating junction type charge detection section that temporarily stores and detects the signal charge transferred from the charge transfer section via the output gate, and a floating junction type charge detection section that is adjacent to the charge detection section and temporarily stores the signal charge in the charge detection section. In the solid-state imaging device, the potential under the reset gate is discharged from the output gate at the timing when the charge is accumulated in the charge detection section. A solid-state imaging device characterized in that a timing pulse applying means is provided so that the potential becomes higher than a lower potential. 2. Under the reset gate and under the output gate so that the maximum amount of charge accumulated in the charge detection section is equal to or less than the minimum amount of charge among the signal charges generated by a plurality of photosensitive pixels and transferred to the charge detection section. 2. The solid-state imaging device according to claim 1, wherein a potential of is determined.