JPH03258173A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To reduce fixed pattern noise by setting a gate level of a JFET to a negative level at the start of a storage period after the end of a reset period. CONSTITUTION:A gate level of a JFET2 is set to a negative level at the start of a storage period after the end of a reset period. An electron of an electron.electron-hole pair excited by an incident light for the storage period is absorbed by an n-channel layer and the electron hole is stored in a gate in the floating state. A channel conductance is modulated by a change in a gate level and the drain current is modulated and amplified. When a vertical selection MOSFET 4 of an n-th row is conductive by a vertical scanning pulse Yn, a drain current of the n-th row picture element charges a vertical signal line 13 of each column. A horizontal selection MOSFET 18 is conductive sequentially from a first column by horizontal scanning pulse x1, x2 during selection of the (n+1)th row of picture elements by a pulse Yn+1 and the stored charge in each column of vertical signal line 1 is sequentially outputted via a video signal line 19.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a solid-state imaging device in which each pixel has a signal amplification function and a method for driving the same, and particularly to suppressing variations in reset potential between pixels.

(Prior Art) FIG. 5 shows a conventional amplification type solid-state imaging device AMI (Ampl
ified MOS Itelligent Imag
er) (TV Society Journal Vol.

41, No. 11.1987. pp, 1075~
1082), and FIG. 6 is a circuit diagram of one pixel thereof. As shown in FIG. 6, one pixel 51 includes a photodiode 61, an amplification MO8FET 62, and a vertical selection MO
It is composed of an 8FET63 and a reset MO8FET64. The optical information signal obtained by the photodiode 61 is amplified by the MO8FET 62 for amplification, and as shown in FIG.
It is an XY address type in which 8FETs 54 are selected and read. Further, the gate of the reset MO8FET 64 in the nth row and the gate of the vertical selection MO8FET 63 in the (n+1)th row are connected to the same first horizontal signal line 55, and the drain of the reset MO8FET 64 is connected to the second horizontal signal line 56. The second horizontal signal line 56 of the nth row and the (
By simultaneously selecting the first horizontal signal lines 55 in the (n+1) row, the photodiodes 61 are reset during the -horizontal scanning period.

First, a series of operations of accumulating, reading, and resetting optical signal charges will be explained. FIG. 7 is a diagram showing drive waveforms of a conventional amplification type solid-state imaging device AMI. At the beginning of the accumulation period 71, the photodiode 61 is set to the initial value (2) shown in FIG. 7 through the reset MO8FET 64. The electron and hole pairs excited by the incident light during the accumulation period 71 are absorbed by the n-layer and the holes by the grounded p-layer of the photodiode 61, respectively, so that the potential of the n-layer changes due to the incident light. decrease accordingly. This n-layer potential is applied to the gate of the amplification MO8FET 62, and the amplified drain current is output through the vertical selection MO8FET 63 and the horizontal selection MO8FET 54.

After reading out the nth row, the vertical scanning circuit 52
At the same time that the pixel in the n+1) row is selected, the MO8FET 64 for the nth row becomes conductive for one horizontal scanning period, and the photodiode 61 in the nth row is reset to the initial value R again, and the above-mentioned cycle continues. Repeated.

Next, the reset period of the photodiode 61 will be explained. Figures 8(a), (b), and (c) show the photodiode 6e and the reset MO8FET 64.
FIG. Here, photodiode 6
1 also serves as the source of the reset MO8FET64. During the accumulation period 71, the reset MO8FET64
are shielded and analyzed, and the photoexcited electrons 81 are accumulated in the photodiode 61, as shown in FIG. 8(a). During the reset period 72, the reset MO8FET6
4 becomes conductive, the surface potential under the gate rises, and the electrons 81 accumulated in the photodiode 61 are transferred to the drain of the reset MO8FET 64 to which a positive voltage is applied. The potential of the photodiode 61 is reset to the drain voltage VR. After the reset period 72 ends, as shown in FIG. 8(e), the electrons 82 accumulated under the gate of the reset period 72
Since some of the electrons 83 are distributed to the photodiode 61, the potential of the photodiode 61 +t
V, decreases by Δ■.

(Problems to be Solved by the Invention) As described above, in the conventional amplification type solid-state imaging device, the reset period of the photodiode, that is, the photoelectric conversion section is (VR-Δ■). Δ■ depends on the threshold voltage of the reset transistor, and due to variations in the geometric dimensions of the reset transistor and spatial variations in the vertical scanning pulse output, the threshold voltage of the reset transistor varies between each pixel. occurs, so Δ■ also varies. Therefore, there is a problem in that the gate potential of the amplifying transistor after the reset period ends varies from pixel to pixel, and fixed pattern noise such as black dots, white dots, or uneven sensitivity always occurs at the same position on the screen.

(Means for Solving the Problems) In the present invention, pixels are arranged in a matrix on the surface of a semiconductor substrate, and each pixel resets optical signal charges accumulated in a photoelectric conversion region, a signal amplification transistor, and a photoelectric conversion region. and vertical selection transistors,
In a solid-state imaging device in which a vertical scanning circuit for sequentially selecting each pixel, a horizontal scanning circuit, a vertical signal line, and a horizontal signal line are formed, the signal amplification transistor is a junction field effect transistor (JFET). The gate also serves as a photoelectric conversion region, the reset transistor and the vertical selection transistor are insulated field effect transistors (MISFETs), and the gate of the JFET is connected to the source of the reset MISFET,
The source of the JFET is connected to the drain of the vertical selection MISFET, the drain of the JFET is connected to a first power supply, the gate of the reset MISFET is connected to a first horizontal signal line, and the reset MISFET is connected to the drain of the vertical selection MISFET.
The drain of T is connected to a second power supply, the gate of the vertical selection MISFET is connected to a second horizontal signal line,
The source of the vertical selection MISFET is connected to a vertical signal line, and the source of the vertical selection MISFET is connected to the reset MISFET of the n-th row and the (n-th
The vertical selection MISFETs in the +1) row are selected at the same time, the reset MISFETs are made conductive during reset, a reverse voltage is applied to the gate of the JFET to punch through between the gate and the substrate, and the reset period is After the termination, the reset MISFET is cut off and the J
The device is characterized in that it has means for setting the gate of the FET in a floating state.

(Function) For example, when the JFET is an n-type, a negative reset voltage of sufficient magnitude to punch through the n-type channel layer between the gate (p-type) and the substrate (p-type) during the reset period is applied to the JFET.
When applied to the gate of the FET, holes flow through the substrate toward the gate. After the reset period ends, the gate of the JFET becomes a floating state, and holes flowing from the substrate to the gate are accumulated in the gate, causing the gate potential to rise and the channel potential to rise accordingly. An energy barrier becomes large for holes attempting to flow into the gate, and the gate potential settles to a constant value when the barrier becomes equal to the diffusion potential of the pn junction (threshold state). This gate potential does not depend on variations in the threshold voltage of the reset transistor. Therefore, fixed pattern noise can be reduced.

The same thing is possible when the JFET is p-type.

(Example) Examples of the present invention are shown below. FIG. 1 is a block diagram of one pixel of the solid-state imaging device according to the present invention, and FIG. 2 is a block diagram of the solid-state imaging device according to the present invention. As shown in Figure 2,
A vertical scanning circuit 11 in which a plurality of pixels 1 are arranged in a matrix and sequentially selects each pixel 1. In addition to the horizontal scanning circuit 12, a vertical signal line 13 is formed in each column, and a first horizontal signal line 14 and a second horizontal signal line 15 are formed in each row. Here, the first horizontal signal line 14 in the nth row and the second horizontal signal line 15 in the (n+1)th row are connected to each other via two switch elements 16 and 17 composed of MOSFETs by the vertical scanning pulse. The configuration is such that they are selected at the same time. As shown in FIG. 1, one pixel 1 includes a vertical junction field effect transistor (JFET) 2 for signal amplification whose gate also serves as a photoelectric conversion region;
It is composed of an insulated field effect transistor (MOSFET) 3 for resetting optical signal charges accumulated in the photoelectric conversion region and a vertical selection MO8FET 4. JFET
The gate of JFET2 is connected to the source of MO8FET3 for reset, and the source of JFET2 is connected to MO8FET4 for vertical selection.
The drain of the JFET 2 is connected to the first power supply 5. The gate of the reset MO8FET3 is connected to the first horizontal signal line 14, and the reset MO8FET3 is connected to the first horizontal signal line 14.
The drain of the 8FET 3 is connected to the second power supply 6. The gate of the vertical selection MO8FET 4 is connected to the second horizontal line 15 , and the source of the vertical selection MO8FET 4 is connected to the vertical signal line 13 .

FIG. 3 is a diagram showing driving waveforms of the solid-state imaging device when the JFET 2 is of n-type. The operation will be explained using this diagram. At the beginning of the accumulation period 32 after the end of the reset period 31, the gate potential of the JFET 2 is set to a negative voltage 2, which will be described later. In this accumulation period 32,
The electron-hole pairs excited by the incident light are absorbed by the n-channel layer, and the holes are accumulated in the floating gate. Channel conductance is modulated by changes in gate potential, and drain current is modulated and amplified. MO8 for vertical selection of the nth row by the vertical scanning pulse Yn
When the FET 4 becomes conductive, the drain current of the pixel belonging to the nth row charges the vertical signal line 13 of each column. Subsequently, while the pixels in the (n+1)th row are selected by the vertical scanning pulse Y0+1, the horizontal scanning pulses Xi, X2.・
・MO8FET18 for horizontal selection sequentially from the first row
becomes conductive, and the charge accumulated in the vertical signal line 1 of each column is sequentially output through the video signal line 19. In parallel, the reset MO8FET 3 of the nth row becomes conductive for one horizontal scanning period, and the The gate potential of the JFET 2 in the n row is reset to ■ again, and the above-described cycle is repeated.

Next, in order to show the difference from the reset operation in a conventional amplification type solid-state imaging device, the reset operation of the solid-state imaging device according to the present invention will be described in the case where the JFET 2 is an n-type. Figure 4 (a), (b), and (c) are JFE
It is a schematic potential diagram in the depth direction under the gate of T2. As described above, in the electron-hole pairs excited by the incident light during the accumulation period 3, the electrons are absorbed by the n-type channel layer, and the holes are accumulated in the floating gate (a). When the readout ends and the reset period 31 begins, the holes accumulated in the gate of JFET2 are swept out to the drain of reset MO8FET3 to which voltage VD is applied, and the gate of JFET2 becomes (■). b). here,
■If we apply a negative voltage large enough to punch through between the gate of our JFET2 and the substrate, holes will flow from the substrate toward the gate, and the drain of the reset MO8FET3 will flow like the accumulated holes. swept away. After reset period 31, JFET
The gate of No. 2 is in a floating state, and the holes flowing from the substrate toward the gate are accumulated in the gate, so the potential of the gate increases, and the potential of the channel increases accordingly, so the holes flowing from the substrate to the gate are The energy barrier becomes large with respect to the hole, and in a state (threshold state) where the barrier becomes equal to the pn junction diffusion potential ■, the gate potential settles to a constant value ■2 <(c). Here, (2) does not depend on variations in the threshold voltage of the reset transistor, which has been a problem in the past. Therefore, fixed pattern noise can be reduced.

The above explanation also applies when the JFET is p-type,
In this case, the same effect can be obtained by reversing the conductivity type of each transistor in the pixel and reversing the polarity of each power supply.

(Effects of the Invention) According to the present invention, even if the threshold voltage of the reset transistor varies between pixels due to variations in the geometric dimensions of the reset transistor and spatial variations in the vertical scanning pulse output, Variations in the reset potential of the photoelectric conversion unit are suppressed, and fixed pattern noise can be reduced.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of one pixel of a solid-state imaging device according to the present invention, FIG. 2 is a configuration diagram of a solid-state imaging device according to the present invention, and FIG.
The figure shows the drive waveform of the solid-state imaging device in the present invention,
FIGS. 4(a), (b), and (c) are diagrams for explaining suppression of variations in reset potential of a solid-state imaging device according to the present invention, and FIG. 5 is a configuration diagram of a conventional amplification type solid-state imaging device. Fig. 6 is a diagram showing the configuration of one pixel of a conventional amplified solid-state imaging device, Fig. 7 is a diagram showing drive waveforms of the conventional amplified solid-state imaging device, and Fig. 8 (a), (b), (c). is a surface potential diagram of a photodiode and a reset MO8FET portion. In the figure, 1, 51...pixel, 2... vertical JFET for signal amplification, 3.6411. MO8FET for reset
, 4, 63... MO8FET for vertical selection, 5... First power supply, 6... Second power supply, 11, 52... Vertical scanning circuit, 12.53... Horizontal scanning circuit, 13...
Vertical signal line, 14.55...first horizontal signal line, 15
．． 56... Second horizontal signal line, 16.17... Switch for horizontal signal line selection, 18.54... MO8FET for horizontal selection, 19.57... Video output line, 20.5
8...Load resistance, 31.72...Reset period of the pixel in the nth row, 32.71 is the accumulation period of the pixel in the nth row, 3
3.73... Vertical selection period for pixels in row n, 61...
Photodiode, 62... MO8FET for signal amplification
, 81.82.83...indicates an electron.

Claims (1)

[Claims] (1) Pixels are arranged in a matrix on the surface of a semiconductor substrate, and each pixel consists of a photoelectric conversion region, a signal amplification transistor, a transistor for resetting the optical signal charge accumulated in the photoelectric conversion region, and a vertical selection transistor. , a solid-state imaging device in which a vertical scanning circuit for sequentially selecting each pixel, a horizontal scanning circuit, and a vertical signal line and a horizontal signal line are formed, the signal amplification transistor being a junction field effect transistor (JFET), Its gate also serves as a photoelectric conversion region, and the reset transistor and vertical selection transistor are insulated field effect transistors (MISFETs), and the gate of the JFET is connected to the source of the reset MISFET, and the source of the JFET is is connected to the drain of a vertical selection MISFET, the drain of the JFET is connected to a first power supply, the gate of the reset MISFET is connected to a first horizontal signal line, and the drain of the reset MISFET is connected to a second is connected to the power supply of the vertical selection MI
The gate of the SFET is connected to a second horizontal signal line, the source of the vertical selection MISFET is connected to a vertical signal line, and the reset MISFET of the n-th row and the (n+1
) rows of the vertical selection MISFETs are simultaneously selected;
At the time of reset, the reset MISFET is turned on, a reverse voltage is applied to the gate of the JFET to punch through between the gate and the substrate, and after the reset period ends, the reset MISFET is turned off and the JFE is turned on.
A solid-state imaging device characterized by having means for setting a gate of T in a floating state.