JPH02143537A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To control the geometrical process and the impurity concentration in excellent reproducibility with high precision for equalizing the electric properties such as threshold voltage, etc., by a method wherein an active layer and a Schottky barrier are formed in selfalignment by assembling the formation of a dummy gate, the deposition of an insulating layer, the anisotropical etching and the ion-implantation technology together. CONSTITUTION:After forming a dummy gate 106 of a silicon oxide film on a semiinsulating GaAs substrate 101, silicon ion is implanted using the dummy gate 106 as a mask to form an n<+>-type contact layers 103 further forming the first sidewall films 107 on both sides of the dummy gate 106. The dummy gate 106 and the first sidewall films 107 only are selectively etched away and after etching away the substrate 101 using a silicon nitride film 108 as a mask and further after silicon ion implantation using the silicon nitride film 108 again, the substrate 101 is activated to form an active layer 102. After depositing a thin silicon oxide film 109, the second sidewall films 110 are formed of the silicon nitride film 108. Finally, after exposing the active layer 102, a Schottky gate 104 is formed further forming an ohmic electrode 105.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a method for manufacturing a field effect transistor.

[Conventional technology]

A conventional method for manufacturing a field effect transistor will be explained with reference to FIG.

First, as shown in FIG. 3(a), an n-type active layer 2 and an n+-type high concentration layer 3 are epitaxially grown on a semi-insulating GaAs substrate 1, and then a high concentration layer 3 is grown as shown in FIG. 3(b). Concentration R
3 and the active layer 2 to form a recess, and a Schottky gate 4 is formed on the exposed active layer 2. Thereafter, an ohmic electrode 5 was formed on the high concentration layer 3, and a field effect transistor was manufactured.

[Problem to be solved by the invention]

The above-mentioned conventional field-effect transistor manufacturing method has the disadvantage that a Schottky gate is formed on the active layer exposed by etching, resulting in variations in etching dimensions and poor uniformity in device characteristics such as threshold voltage. be.

An object of the present invention is to provide a method for manufacturing a field effect transistor with good reproducibility.

[Means to solve the problem]

A method for manufacturing a field effect transistor according to the present invention includes forming a dummy gate on a semi-insulating compound semiconductor substrate, performing ion implantation using the dummy gate as at least a part of a mask, and forming contact layers on both sides of the dummy gate. After that, a step of forming a first sidewall film on both sides of the dummy gate, a step of depositing a first insulating film, and a planarization etch-back using a resist are performed to expose the dummy gate and the first sidewall film. a step of etching away the
After etching the semi-insulating compound semiconductor substrate using the first insulating film as a mask, an insulating film of the rear cylinder 2 with an active layer formed by ion implantation and activation treatment is deposited, and further an insulating film is formed on the top of the active layer. forming a second sidewall film on the side surface of the trench; and selectively etching the second insulating film on the active layer using the second sidewall film as a mask to expose the surface of the active layer. After that, the method includes a step of forming a Schottky gate, and a step of forming an ohmic electrode on the contact layer.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1A to 1E are vertical cross-sectional views of semiconductor chips arranged in the order of steps for explaining a first embodiment of the present invention.

First, as shown in FIG.
After forming a dummy gate 106 with a silicon oxide film on the A s substrate 101, silicon ions are implanted using a predetermined pattern of photoresist film and the dummy gate 106 as a mask to form an n+ type contact layer 103, and then a silicon oxide film is formed. is deposited and anisotropically etched to form a first sidewall film 107 on both sides of the dummy games 1-106.

Next, as shown in FIG. 1(b), the silicon nitride film 108
After depositing, planarization is performed using a resist, and after exposing the dummy gate 106 and the first sidewall film 106 by etching back, the dummy gate 106 and the first sidewall film 107 are removed.
Then, the silicon nitride film 1 is selectively etched.
08 as a mask, semi-insulating GaAs substrate 101 is
Etching is performed to a thickness of 0 nm to 1100 nm, silicon ions are implanted using the silicon nitride film 108 as a mask, and then activated to form an active layer 102.

Next, as shown in FIG. 1(C), 50 nm to 1100 nm
After depositing n thin silicon oxide 109, a second sidewall film 109 is formed of a silicon nitride film. Next, in Figure 1 (d>
As shown in FIG. 3, after wet etching the silicon oxide film 7 to expose the active layer 102, a Schottky gate 104 is formed. Finally, as shown in FIG. 1(e), an ohmic electrode 105 is formed.

Except for the formation of the dummy gate, no mask alignment process is used, and the geometric dimensions of the gate portion are determined by the thicknesses of the silicon oxide film and the silicon nitride film, so it can be processed with high precision. Furthermore, since the impurity concentration of the active layer is determined by ion implantation, controllability is good. Therefore, field effect transistors with uniform electrical characteristics can be manufactured with good reproducibility.

FIGS. 2(a) and 2(b) are longitudinal sectional views of semiconductor chips arranged in the order of steps for explaining a second embodiment of the present invention.

First, as shown in FIG. 2(a), a dummy gate 206 is formed on a semi-insulating GaAs substrate 201. Using the dummy gate 206 as a mask, silicon ions are implanted to form a first contact layer 203a. Furthermore, a first sidewall film 207 is formed on the sidewall of the dummy gate 206, and silicon ions are implanted to form a second contact with higher precision than the first contact layer 203a! 203b is formed.

After that, similarly to the first embodiment, the silicon nitride film 208
Deposition, planarization with resist, etch back, selective etching of dummy gate 206 and first sidewall film 207, etching of semi-insulating GaAs substrate 201, formation of active layer 202 by silicon ion implantation and activation, silicon oxide film 209, the second sidewall film 210 is formed, and the Schottky gate 204 is formed.
An ohmic electrode 205 is formed as in b).

In this embodiment, an LDD structure can be realized by setting the first contact Ml 203a to an intermediate concentration between the active layer 202 and the second contact layer 203b, which has the advantage of improving the characteristics of the field effect transistor. be.

〔Effect of the invention〕

As explained above, the present invention combines dummy gate formation, insulating layer growth, anisotropic etching, and ion implantation techniques to form the active layer and Schottky barrier in a self-aligned manner. The impurity concentration can be controlled with high precision with good reproducibility, and field effect transistors with uniform electrical characteristics such as threshold voltage can be manufactured.

[Brief explanation of the drawing]

Figure 1 (a) to (e), Figure 2 (a), (b) and Figure 3
Figures (a) to (C) are longitudinal cross-sectional views of semiconductor chips arranged in the order of steps for explaining a first embodiment, a second embodiment, and a conventional example of the present invention, respectively. 1.101,201...Semi-insulating GaAs substrate, 2.102.202...Active layer, 3,103...
Contact layer, 203a...first contact layer, 2
03b... second contact layer, 4, 104, 204
...Schottky Gate, 5,105,205...
Ohmic electrode, 106, 206... dummy gate,
107,207...first side wall membrane, 108°208.
...Silicon nitride film, 109,209...Silicon oxide film, 110,210...Second sidewall film.舊Z concavity

Claims (1)

[Claims] A dummy gate is formed on a semi-insulating compound semiconductor substrate,
forming a first sidewall film on both sides of the dummy gate after performing ion implantation using the dummy gate as at least a part of a mask to form a contact layer on both sides of the dummy gate; and depositing a first insulating film. , the dummy gate and the first
After exposing and selectively etching away the sidewall film of the semiconductor substrate, etching the semi-insulating compound semiconductor substrate using the first insulating film as a mask, forming an active layer by ion implantation and activation treatment. After that, a second insulating film is deposited, and a second sidewall film is formed on the side surface of the groove formed on the top of the active layer. A field effect transistor comprising: forming a Schottky gate after selectively etching an insulating film to expose the surface of the active layer; and forming an ohmic electrode on the contact layer. Production method.