JP2757262B2 - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
- Publication number
- JP2757262B2 JP2757262B2 JP1145464A JP14546489A JP2757262B2 JP 2757262 B2 JP2757262 B2 JP 2757262B2 JP 1145464 A JP1145464 A JP 1145464A JP 14546489 A JP14546489 A JP 14546489A JP 2757262 B2 JP2757262 B2 JP 2757262B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- crystal silicon
- semiconductor layer
- silicon semiconductor
- shaped groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title claims description 73
- 238000000034 method Methods 0.000 title claims description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 16
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 38
- 230000003647 oxidation Effects 0.000 claims description 16
- 238000007254 oxidation reaction Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 15
- 238000000206 photolithography Methods 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 239000013078 crystal Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 37
- 229910052814 silicon oxide Inorganic materials 0.000 description 37
- 229910052581 Si3N4 Inorganic materials 0.000 description 23
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 23
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 17
- 108091006146 Channels Proteins 0.000 description 15
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 14
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- -1 boron ions Chemical class 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、高耐圧大電流で用いられる電力用半導体デ
バイスの分野において低オン抵抗化と高信頼化を可能に
した半導体装置の製造方法に関するものである。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device which enables low on-resistance and high reliability in the field of power semiconductor devices used at high withstand voltage and high current. Things.
従来のこの種の半導体装置の製造方法について、一例
を第３図（ａ）〜（ｆ）に示して説明する。第３図にお
いて、まずｎ型の低抵抗単結晶シリコン半導体基板１上
にｎ型の高抵抗単結晶シリコン半導体層２をエピタキシ
ヤル成長したシリコン半導体基板を用いて、単結晶シリ
コン半導体層２の第１主面側にボロンをイオン注入して
ｐ型のチヤネル領域３を形成した後、熱酸化によりシリ
コン酸化膜４を形成し、さらに減圧化学気相成長法によ
りシリコン窒化膜5,多結晶シリコン膜6,シリコン酸化膜
７を順次形成する（第３図（ａ））。次にフォトリソグ
ラフイにより所望の領域のみにレジストパターンを形成
し、これをマスクとしてRIE法で各シリコン酸化膜7,多
結晶シリコン膜6,シリコン窒化膜5,シリコン酸化膜４を
順次エツチングし、レジスタを除去する。続いて前記シ
リコン酸化膜7,多結晶シリコン膜6,シリコン窒化膜5,シ
リコン酸化膜４をマスクとしてRIE法でｐ型のチヤネル
領域３をエツチングし、高抵抗シリコン半導体層２に到
る所望の深さにＵ字型の溝1aを形成し、その後シリコン
酸化膜７を除去する。次いでこの溝1aの内面に薄い酸化
膜を形成した後、直ちにこの薄い酸化膜を除去し、ゲー
ト酸化膜８を形成する（第３図（ｂ））。次に減圧化学
気相成長法により多結晶シリコン膜９を堆積した後、PO
Cl3からの気相拡散により多結晶シリコン膜９に隣を拡
散し、さらに減圧化学気相成長法により多結晶シリコン
膜10を堆積する（第３図（ｃ））。次に前記多結晶シリ
コン膜10,多結晶シリコン膜９をRIE法によりエツチング
し、シリコン窒化膜５を露出する（第３図（ｄ））。次
に前記シリコン窒化膜５をマスクとして選択酸化を行い
シリコン酸化膜11を形成し、該シリコン窒化膜５を除去
した後、例えば隣のイオン注入を行い、ｎ型のソース領
域12を形成する（第３図（ｅ））。次いでシリコン酸化
膜４を除去した後、厚いAl電極13を堆積しソース電極と
する。最後にシリコン半導体基板の第２主面側にCr−Ni
−Agを堆積し、ドレイン電極14を形成することにより高
耐圧大電流MIS型半導体装置が完成する（第３図
（ｆ））。An example of a conventional method of manufacturing this type of semiconductor device will be described with reference to FIGS. 3 (a) to 3 (f). In FIG. 3, first, an n-type high-resistance single-crystal silicon semiconductor layer 2 is epitaxially grown on an n-type low-resistance single-crystal silicon semiconductor substrate 1 to form a single-crystal silicon semiconductor layer 2. After boron ions are implanted into the main surface to form a p-type channel region 3, a silicon oxide film 4 is formed by thermal oxidation, and a silicon nitride film 5 and a polycrystalline silicon film are formed by low pressure chemical vapor deposition. 6. A silicon oxide film 7 is sequentially formed (FIG. 3A). Next, a resist pattern is formed only in a desired region by photolithography, and using this as a mask, each silicon oxide film 7, polycrystalline silicon film 6, silicon nitride film 5, and silicon oxide film 4 are sequentially etched by RIE, Remove the register. Subsequently, the p-type channel region 3 is etched by RIE using the silicon oxide film 7, the polycrystalline silicon film 6, the silicon nitride film 5, and the silicon oxide film 4 as a mask, and a desired region reaching the high-resistance silicon semiconductor layer 2 is obtained. A U-shaped groove 1a is formed at the depth, and then the silicon oxide film 7 is removed. Next, after forming a thin oxide film on the inner surface of the groove 1a, the thin oxide film is immediately removed to form a gate oxide film 8 (FIG. 3B). Next, after depositing a polycrystalline silicon film 9 by a low pressure chemical vapor deposition method,
The polycrystalline silicon film 9 is diffused next to the polycrystalline silicon film 9 by gas phase diffusion from Cl 3, and a polycrystalline silicon film 10 is further deposited by a low pressure chemical vapor deposition method (FIG. 3C). Next, the polycrystalline silicon film 10 and the polycrystalline silicon film 9 are etched by RIE to expose the silicon nitride film 5 (FIG. 3D). Next, selective oxidation is performed using the silicon nitride film 5 as a mask to form a silicon oxide film 11, and after removing the silicon nitride film 5, for example, next ion implantation is performed to form an n-type source region 12 ( FIG. 3 (e). Next, after removing the silicon oxide film 4, a thick Al electrode 13 is deposited and used as a source electrode. Finally, Cr-Ni is applied to the second main surface of the silicon semiconductor substrate.
By depositing -Ag and forming the drain electrode 14, a high withstand voltage and large current MIS type semiconductor device is completed (FIG. 3 (f)).
なお、このような構造の半導体装置は、例えば公知文
献（IEEE TRANSACTIONS ON ELECTRON DEVICES（H.−R.C
HANG et al.,“Self−Aligned UMOSFET's with a Speci
fic On Resisitance of 1mΩ・cm2",IEEE VOL.ED−34 N
O.11,1987,p2329））に開示されている。A semiconductor device having such a structure is disclosed in, for example, a known document (IEEE TRANSACTIONS ON ELECTRON DEVICES (H.-RC
HANG et al., “Self-Aligned UMOSFET's with a Speci
fic On Resisitance of 1mΩ · cm 2 ", IEEE VOL.ED-34 N
O. 11, 1987, p2329)).
しかし、ここに述べた第３図の従来技術においては、
以下に述べる２つの問題点がある。第３図（ｂ）におい
てシリコン窒化膜５の端部とＵ字型の溝1aの上部のコー
ナー部がほぼ一致する構造となつているため、コーナー
部で形成されるゲート酸化膜８は薄くなり、その結果ゲ
ート酸化膜８全体としての耐圧が劣化し素子の信頼性が
低下するといつた問題が生じる。また、かかる構造の半
導体装置の平面パターンを第４図に示す。この図ではｐ
型のチヤネル領域3,n型のソース領域12,U字型の溝1aの
位置関係を示してある。この第４図における平面パター
ンでは、ｐ型のチヤネル領域３の電位をｎ型のソース12
と同電位にするための電極コンタクトがｐ型のチヤネル
領域３の表面上に取られるため、チヤネルコンタクトの
幅だけ素子のゲート幅は狭くなる。すなわちMIS型トラ
ンジスタのオン抵抗を十分に小さくすることができな
い。However, in the prior art of FIG. 3 described here,
There are two problems described below. In FIG. 3 (b), since the end of the silicon nitride film 5 and the upper corner of the U-shaped groove 1a substantially coincide with each other, the gate oxide film 8 formed at the corner becomes thinner. As a result, there arises a problem that the breakdown voltage of the gate oxide film 8 as a whole deteriorates and the reliability of the device decreases. FIG. 4 shows a planar pattern of a semiconductor device having such a structure. In this figure, p
The positional relationship between the channel region 3, the n-type source region 12, and the U-shaped groove 1a is shown. In the plane pattern shown in FIG. 4, the potential of the p-type channel region 3 is
Since the electrode contact for making the same potential as that described above is formed on the surface of the p-type channel region 3, the gate width of the element is reduced by the width of the channel contact. That is, the ON resistance of the MIS transistor cannot be sufficiently reduced.
また、第５図に上記従来技術の持つ欠点の内,p型チヤ
ネル領域への電極コンタクトの点に関して対策を施した
DMOS（Doble−Diffused MOS）構造の半導体装置の製造
方法が、例えば公知文献（IEEE ELELCTRONDEVICE LETTE
RS（G.CHEN et al.,“A Novel Contact Process for Po
wer MOSFET's",IEEE VOL.EDL−7,NO.12,1986,p.672））
に開示されている。第５図を用いてその構造と製造方法
について概説する。FIG. 5 shows a countermeasure for the electrode contact to the p-type channel region among the drawbacks of the conventional technology.
A method for manufacturing a semiconductor device having a DMOS (Doble-Diffused MOS) structure is disclosed in, for example, a known document (IEEE ELELCTRONDEVICE LETTE).
RS (G. CHEN et al., “A Novel Contact Process for Po
wer MOSFET's ", IEEE VOL.EDL-7, NO.12, 1986, p.672))
Is disclosed. The structure and manufacturing method will be outlined with reference to FIG.
第５図において、ｎ型の低抵抗単結晶シリコン半導体
基板15の上にｎ型の高抵抗単結晶シリコン半導体層16を
エピタキシヤル成長したシリコン半導体基板を出発基板
として、その第１主面側にゲート酸化膜17を形成した
後、減圧化学気相成長法により多結晶シリコン膜18を堆
積する（第５図（ａ））。次にフォトリソグラフイによ
りゲートパターンを形成した後、RIE法により多結晶シ
リコン膜18を加工しゲート電極を形成する。次いで局所
的なイオン注入とその後の拡散によりｐ型のチヤネル領
域19及びｎ型のソース領域20を形成する。次に化学気相
成長法によりシリコン酸化膜21を形成し、フオトリソグ
ラフイ工程により形成したレジストパターンをマスクと
してコンタクトホールを形成した後、ソース電極として
Al22を例えば２μｍ堆積する（第５図（ｂ））。続いて
窒素雰囲気中で例えば500℃,30分の条件でアニールを行
い、ｐ型のチヤネル領域19に到る深さまでAl22をスパイ
クさせる。次にAl23を単結晶シリコン半導体基板の第２
主面側に蒸着し，ドレイン電極とすることによりDMOS構
造の半導体装置が完成する（第５図（ｃ））。In FIG. 5, a silicon semiconductor substrate obtained by epitaxially growing an n-type high-resistance single-crystal silicon semiconductor layer 16 on an n-type low-resistance single-crystal silicon semiconductor substrate 15 is used as a starting substrate. After forming the gate oxide film 17, a polycrystalline silicon film 18 is deposited by a low pressure chemical vapor deposition method (FIG. 5A). Next, after forming a gate pattern by photolithography, the polycrystalline silicon film 18 is processed by RIE to form a gate electrode. Next, a p-type channel region 19 and an n-type source region 20 are formed by local ion implantation and subsequent diffusion. Next, a silicon oxide film 21 is formed by a chemical vapor deposition method, a contact hole is formed using a resist pattern formed by a photolithography process as a mask, and then a source electrode is formed.
Al22 is deposited to a thickness of, for example, 2 μm (FIG. 5B). Subsequently, annealing is performed in a nitrogen atmosphere, for example, at 500 ° C. for 30 minutes to spike Al 22 to a depth reaching the p-type channel region 19. Next, Al23 is applied to the second of the single crystal silicon semiconductor substrate.
A semiconductor device having a DMOS structure is completed by vapor deposition on the main surface to form a drain electrode (FIG. 5 (c)).
かかるDMOS構造の半導体装置では、ｐ型のチヤネル領
域19の電極コンタクトを縦方向に取つているため、表面
パターン上でチヤネル領域19への電極コンタクトを設け
る必要がなく、実際のチヤネル幅がそのままパターン上
でのゲート幅と等しくなる。しかしコンタクトホールは
フオトリソグラフイで決定されているため、ゲート電極
としての多結晶シリコン膜18の間隔はフオトリソグラフ
イ時の位置合わせ余裕で決定される。そのため、素子の
微細化が不可能なため低オン抵抗化が図れず、素子の高
性能化を図るには不向きである。In the semiconductor device having such a DMOS structure, since the electrode contact of the p-type channel region 19 is taken in the vertical direction, it is not necessary to provide the electrode contact to the channel region 19 on the surface pattern, and the actual channel width is not changed. It is equal to the gate width above. However, since the contact hole is determined by photolithography, the interval between the polycrystalline silicon films 18 as the gate electrode is determined by the alignment margin at the time of photolithography. Therefore, it is not possible to reduce the on-resistance because the element cannot be miniaturized, which is not suitable for improving the performance of the element.
このように、以上述べた２つの従来技術において前者
（第３図）のものは、ｎ型ソース領域とｐ型チヤネル領
域への電極コンタクトが自己整合的に取られているた
め、Ｕ時型溝の間隔が縮められる利点を有しているが、
ｐ型チヤネル領域への電極コンタクトを平面で取るため
実効ゲート幅がパターン上でのゲート幅より小さくな
り、さらにＵ字型溝端部でのゲート酸化膜の耐圧が低く
信頼性に乏しいという問題点があつた。As described above, the former (FIG. 3) of the two prior arts described above has a U-shaped groove because the electrode contacts to the n-type source region and the p-type channel region are made in a self-aligned manner. Has the advantage of reducing the distance between
Since the electrode contact to the p-type channel region is made in a plane, the effective gate width becomes smaller than the gate width on the pattern, and furthermore, the withstand voltage of the gate oxide film at the end of the U-shaped groove is low and the reliability is poor. Atsuta.
また、後者（第５図）のものは、ｐ型チヤネル領域へ
の電極コンタクトが縦型であるため、実効チヤネル幅と
パターン上でのゲート幅が一致する利点を有している
が、この電極コンタクトがフオトリソグラフイーで決定
されるため、隣り合うゲート電極どおしの間隔を狭めら
れない。そのため、素子の微細化が不可能となり低オン
抵抗化が図れず、素子の高性能化を図るには不向きであ
るという問題点があつた。The latter (FIG. 5) has the advantage that the effective channel width and the gate width on the pattern match because the electrode contact to the p-type channel region is vertical. Since the contact is determined by photolithography, the distance between adjacent gate electrodes cannot be reduced. For this reason, there has been a problem in that the element cannot be miniaturized and a low on-resistance cannot be achieved, which is not suitable for improving the performance of the element.
本発明はかかる従来技術が持つ問題点を鑑みてなされ
たものであり、その目的は、高耐圧大電流で用いられる
電力用半導体デバイスの分野において高性能，高信頼化
を実現可能にした半導体装置の製造方法を提供すること
にある。The present invention has been made in view of the problems of the conventional technology, and has as its object to provide a semiconductor device capable of realizing high performance and high reliability in the field of power semiconductor devices used with high withstand voltage and high current. It is to provide a manufacturing method of.
このような目的を達成するため、本発明は、第１主面
の表面側から見て第１の導電型を有する第１の単結晶シ
リコン半導体層，第２の導電型を有する第２の単結晶シ
リコン半導体層，第１の導電型を有する第３の単結晶シ
リコン半導体層から成る積層構造の単結晶シリコン半導
体基板を用いてMOS型半導体装置を製造する方法におい
て、前記第１主面上に第１の絶縁膜と第２の絶縁膜を順
次堆積する工程と、フオトリソグラフイーで描画したレ
ジストをマスクとして前記第２の絶縁膜と前記第１の絶
縁膜を順次除去し、該第１と第２の絶縁膜の加工面及び
前記第１の単結晶半導体層の表面からなる第１のＵ字型
の溝を形成する工程と、前記レジスト除去後に第３の絶
縁膜を堆積し、続いて異方性エツチングにより平坦部の
該第３の絶縁膜のみを除去し、前記第１のＵ字型の溝の
側壁部のみに第３の絶縁膜を残す工程と、前記第２の絶
縁膜と第３の絶縁膜をマスクとして前記第１の単結晶シ
リコン半導体層と第２の単結晶シリコン半導体層を異方
性エツチングし、前記第２の単結晶シリコン半導体層よ
りも深い第２のＵ字型の溝を形成する工程と、前記第２
及び第３の絶縁膜を除去し、前記第１の絶縁膜をマスク
として前記第２のＵ字型の溝の内面を酸化してゲート酸
化膜を形成する工程と、前記第２のＵ字型の溝内部に非
単結晶シリコン半導体層を埋め込み前記単結晶シリコン
半導体基板の表面を平坦化する工程と、前記第１の主面
側で前記第１の絶縁膜で覆われていない領域を選択酸化
することにより第４の絶縁膜を形成する工程と、前記第
１の絶縁膜を除去した後、前記第４の絶縁膜をマスクと
して前記第１の単結晶シリコン半導体層を除去し、前記
第２の単結晶シリコン半導体層に至る第３の溝を形成す
る工程、前記第３の溝に電極金属を埋め込む工程とを含
むことを特徴とするものである。In order to achieve such an object, the present invention provides a first single-crystal silicon semiconductor layer having a first conductivity type and a second single-crystal silicon layer having a second conductivity type as viewed from the surface side of the first main surface. A method for manufacturing a MOS semiconductor device using a single crystal silicon semiconductor substrate having a laminated structure including a crystal silicon semiconductor layer and a third single crystal silicon semiconductor layer having a first conductivity type, the method comprising: A step of sequentially depositing a first insulating film and a second insulating film, and sequentially removing the second insulating film and the first insulating film using a resist drawn by photolithography as a mask, Forming a first U-shaped groove formed of a processed surface of a second insulating film and a surface of the first single crystal semiconductor layer, and depositing a third insulating film after removing the resist; Only the third insulating film in the flat portion is removed by anisotropic etching. Leaving a third insulating film only on the side wall of the first U-shaped groove; and using the second insulating film and the third insulating film as a mask to form the first single-crystal silicon semiconductor. Anisotropically etching the layer and the second single-crystal silicon semiconductor layer to form a second U-shaped groove deeper than the second single-crystal silicon semiconductor layer;
Removing the third insulating film and oxidizing the inner surface of the second U-shaped groove using the first insulating film as a mask to form a gate oxide film; Embedding a non-single-crystal silicon semiconductor layer in the trench, planarizing the surface of the single-crystal silicon semiconductor substrate, and selectively oxidizing a region of the first main surface which is not covered with the first insulating film. Forming a fourth insulating film, and after removing the first insulating film, removing the first single-crystal silicon semiconductor layer using the fourth insulating film as a mask; Forming a third groove reaching the single-crystal silicon semiconductor layer, and embedding an electrode metal in the third groove.
また、本発明の別の発明は、上記のものにおいて第１
のＵ字型の溝を形成した後、第２の絶縁膜をマスクとし
て該第１のＵ字型溝部に第２のＵ字型の溝を形成し、再
び第２の絶縁膜をマスクとして第１の絶縁膜の側面のみ
を等方エツチングして所望の距離だけ後退させ、その後
第２の絶縁膜を除去して、ゲート酸化以降は上記のもの
の工程と同じ工程を有することを特徴とするものであ
る。Further, another invention of the present invention relates to the above-described first aspect.
After the U-shaped groove is formed, a second U-shaped groove is formed in the first U-shaped groove portion using the second insulating film as a mask, and the second U-shaped groove is formed again using the second insulating film as a mask. (1) only the side surface of the first insulating film is isotropically etched to retreat by a desired distance, and then the second insulating film is removed, and after the gate oxidation, the same steps as those described above are performed. It is.
本発明による半導体装置の製造方法では、一導電型チ
ヤネル領域形成後、自己整合技術を用いてマスク１枚で
ゲートまわりの加工から電極のコンタクトホールの形成
まで行えるため、単位セルの微細化が可能であり、低オ
ン抵抗化をねらいとした半導体装置を形成できる。ま
た、一導電型のチヤネル領域の電極コンタクトを自己整
合プロセスを用いて縦方向に取つているため、実効ゲー
ト幅とパターン上でのゲート幅が同一となり、低オン抵
抗化が容易に達成でき、素子の高性能化が可能になる。
さらに、ゲート酸化膜形成の際、耐酸化性のマスクが溝
のコーナー部より後退しているため、溝上部のコーナー
部でのゲート酸化膜は薄くならず、ゲート酸化膜の耐圧
劣化による信頼性の低下といつた問題点を解消できる。In the method of manufacturing a semiconductor device according to the present invention, after forming a one-conductivity-type channel region, a single mask can be used to perform processing from the processing around the gate to the formation of the contact hole of the electrode using a single mask, so that the unit cell can be miniaturized. Thus, it is possible to form a semiconductor device that aims to reduce on-resistance. In addition, since the electrode contact of the one-conductivity type channel region is taken in the vertical direction using a self-alignment process, the effective gate width and the gate width on the pattern become the same, and a low on-resistance can be easily achieved. The performance of the device can be improved.
Furthermore, when forming the gate oxide film, since the oxidation-resistant mask is recessed from the corner of the groove, the gate oxide film at the corner at the upper portion of the groove is not thinned, and the reliability due to the withstand voltage degradation of the gate oxide film is reduced. Problem can be solved.
以下、本発明による半導体装置の製造方法の実施例を
図面を用いて詳細に説明する。Hereinafter, an embodiment of a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the drawings.
第１図（ａ）〜（ｇ）は本発明方法の一実施例を示す
工程断面図である。第１図において、面方位（100）で
ｎ型の低抵抗単結晶シリコン半導体基板24上にｎ型の高
抵抗単結晶シリコン半導体層25をエピタキシヤル成長し
た後、薄いシリコン酸化膜26を例えば熱酸化により形成
し、例えばボロンと燐をイオン注入した後、熱拡散によ
りｐ型のチヤネル領域27,n型のソース領域28を形成す
る。その後減圧化学気相成長法により、例えばシリコン
窒化膜29とシリコン酸化膜30を順次形成する（第１図
（ａ））。次にフォトリソグラフイにより所望の領域の
みにレジストパターンを形成した後、このレジストパタ
ーンをマスクとしてシリコン酸化膜30,シリコン窒化膜2
9,シリコン酸化膜26を例えばRIE法を用いて順次エツチ
ングしてＵ字型の溝24aを形成し、レジストを除去す
る。次いで例えば減圧化学気相成長法によりシリコン酸
化膜31を堆積した後、RIE法により平坦部のシリコン酸
化膜31をエツチングし、前記シリコン酸化膜30,シリコ
ン窒化膜29,シリコン酸化膜26からなるパターン溝24aの
側壁部にシリコン酸化膜31を残す（第１図（ｂ））。1 (a) to 1 (g) are process sectional views showing one embodiment of the method of the present invention. In FIG. 1, after an n-type high-resistance single-crystal silicon semiconductor layer 25 is epitaxially grown on an n-type low-resistance single-crystal silicon semiconductor substrate 24 with a plane orientation (100), a thin silicon oxide film 26 is formed, for example, by heat. After being formed by oxidation, for example, boron and phosphorus ions are implanted, a p-type channel region 27 and an n-type source region 28 are formed by thermal diffusion. Thereafter, for example, a silicon nitride film 29 and a silicon oxide film 30 are sequentially formed by low pressure chemical vapor deposition (FIG. 1A). Next, after forming a resist pattern only in a desired region by photolithography, the silicon oxide film 30 and the silicon nitride film 2 are formed using the resist pattern as a mask.
9. The silicon oxide film 26 is sequentially etched using, for example, the RIE method to form a U-shaped groove 24a, and the resist is removed. Next, for example, after depositing a silicon oxide film 31 by a low pressure chemical vapor deposition method, the silicon oxide film 31 in the flat portion is etched by the RIE method, and a pattern including the silicon oxide film 30, the silicon nitride film 29, and the silicon oxide film 26 is formed. The silicon oxide film 31 is left on the side wall of the groove 24a (FIG. 1B).
次に、前記シリコン酸化膜30,31をマスクとして例え
ばRIE法を用いてソース領域28とチヤネル領域27をエツ
チングし、高抵抗単結晶シリコン半導体層25に到達する
深さのＵ字型の溝24bを形成する。その後、犠牲酸化と
ウエツトエツチング等でRIE法による損傷や汚染等を除
去した後、シリコン酸化膜30と31を除去する。その後シ
リコン窒化膜29をマスクとして選択酸化によりゲート酸
化膜32を形成する（第１図（ｃ））。次いでゲート電極
として燐添加多結晶シリコン33を例えば減圧化学気相成
長法で堆積し、この燐添加多結晶シリコン33をエツチバ
ツクしシリコン窒化膜29を露出させる（第１図
（ｄ））。次に前記シリコン窒化膜29をマスクとして選
択酸化によりシリコン酸化膜34を形成した後、シリコン
窒化膜29とシリコン酸化膜26を順次除去する（第１図
（ｅ））。次に前記シリコン酸化膜34をマスクとしてｐ
型のチヤネル領域27に到達する深さの溝24cを形成する
（第１図（ｆ））。しかる後、ソース電極として例えば
Al35を堆積する。さらにフオトレジストをマスクとして
Al35をパタンニングし、ドレイン電極としてAl36を低抵
抗単結晶シリコン半導体基板の第２主面側に堆積するこ
とにより、縦型の高耐圧大電流MIS型半導体装置が完成
する（第１図（ｇ））。Next, using the silicon oxide films 30 and 31 as a mask, the source region 28 and the channel region 27 are etched using, for example, the RIE method, and a U-shaped groove 24b having a depth reaching the high-resistance single-crystal silicon semiconductor layer 25 is formed. To form Then, after removing damage and contamination by the RIE method by sacrificial oxidation and wet etching, the silicon oxide films 30 and 31 are removed. Thereafter, a gate oxide film 32 is formed by selective oxidation using the silicon nitride film 29 as a mask (FIG. 1C). Next, phosphorus-added polycrystalline silicon 33 is deposited as a gate electrode by, for example, a low pressure chemical vapor deposition method, and the phosphorus-added polycrystalline silicon 33 is etched back to expose the silicon nitride film 29 (FIG. 1 (d)). Next, after the silicon oxide film 34 is formed by selective oxidation using the silicon nitride film 29 as a mask, the silicon nitride film 29 and the silicon oxide film 26 are sequentially removed (FIG. 1 (e)). Next, using the silicon oxide film 34 as a mask, p
A groove 24c having a depth reaching the channel region 27 of the mold is formed (FIG. 1 (f)). Then, as a source electrode, for example,
Al35 is deposited. Using photoresist as a mask
By patterning Al35 and depositing Al36 as a drain electrode on the second main surface side of the low-resistance single crystal silicon semiconductor substrate, a vertical high withstand voltage and large current MIS type semiconductor device is completed (FIG. 1 (g)). )).
このように本実施例の製造方法によると、 ａ） 自己整合技術の導入により、ゲートの溝エツチン
グからソース電極コンタクトまでマスク１枚で形成が可
能であり、素子の微細化を図ることができ、単位面積当
りのゲート幅を増やすことができるため、高耐圧大電流
MIS型半導体装置の高性能化が可能である。As described above, according to the manufacturing method of the present embodiment, a) By introducing the self-alignment technique, it is possible to form a single mask from the etching of the gate groove to the contact of the source electrode, and it is possible to miniaturize the element. High withstand voltage and large current because the gate width per unit area can be increased
The performance of the MIS type semiconductor device can be improved.
ｂ） チヤネル領域の電位をソース電位に固定するため
の電極コンタクトを自己整合技術を用いて縦方向に取つ
ているため、実効ゲート幅とパターン上でのゲート幅が
一致し、単位面積当りのゲート幅を増やすことができ、
高耐圧大電流MIS型半導体装置の高性能化が可能であ
る。b) Since the electrode contact for fixing the potential of the channel region to the source potential is made in the vertical direction by using the self-alignment technique, the effective gate width matches the gate width on the pattern, and the gate per unit area You can increase the width,
It is possible to improve the performance of a high withstand voltage and large current MIS type semiconductor device.
ｃ） ゲート酸化膜形成の際、耐酸化性のマスクが溝の
コーナー部より後退しているため、溝上部のコーナー部
でゲート酸化膜が薄くなり、ゲート酸化膜の耐圧劣化に
よる信頼性の低下といつた問題点を解消することがで
き、高信頼性が得られる。c) During the formation of the gate oxide film, the oxidation-resistant mask is recessed from the corner of the groove, so that the gate oxide film becomes thinner at the upper corner of the groove, and the reliability is reduced due to deterioration of the withstand voltage of the gate oxide film. Problem can be solved, and high reliability can be obtained.
等の利点を有する。And so on.
第２図（ａ）〜（ｉ）は本発明の別の実施例を示す工
程断面図である。第２図において、面方位（100）でｎ
型の低抵抗単結晶シリコン半導体基板37上にｎ型の高抵
抗単結晶シリコン半導体層38をエピタキシヤル成長した
後、薄いシリコン酸化膜39を例えば熱酸化により形成
し、例えばボロンと燐をイオン注入した後、熱拡散によ
りｐ型のチヤネル領域40,n型のソース領域41を形成す
る。その後減圧化学気相成長法により、例えばシリコン
窒化膜42とシリコン酸化膜43を順次形成する（第２図
（ａ））。次にフオトリソグラフイにより所望の領域の
みにレジストパターンを形成した後、このレジストパタ
ーンをマスクとしてシリコン酸化膜43,シリコン窒化膜4
2,シリコン酸化膜39を例えばRIE法を用いて順次エツチ
ングしてＵ字型の溝37aを形成し、レジストを除去する
（第２図（ｂ））。次いで前記シリコン酸化膜43をマス
クとして例えばRIE法を用いて高抵抗シリコン半導体層3
8に到達する深さのＵ字型の溝37bを形成する（第２図
（ｃ））。2 (a) to 2 (i) are process sectional views showing another embodiment of the present invention. In FIG. 2, in the plane orientation (100), n
After epitaxially growing an n-type high-resistance single-crystal silicon semiconductor layer 38 on a low-resistance single-crystal silicon semiconductor substrate 37, a thin silicon oxide film 39 is formed by, for example, thermal oxidation, and boron and phosphorus are ion-implanted, for example. After that, a p-type channel region 40 and an n-type source region 41 are formed by thermal diffusion. Thereafter, for example, a silicon nitride film 42 and a silicon oxide film 43 are sequentially formed by a low pressure chemical vapor deposition method (FIG. 2A). Next, after forming a resist pattern only in a desired region by photolithography, the silicon oxide film 43 and the silicon nitride film 4 are formed using the resist pattern as a mask.
2. The silicon oxide film 39 is sequentially etched using, for example, the RIE method to form a U-shaped groove 37a, and the resist is removed (FIG. 2B). Next, using the silicon oxide film 43 as a mask, the high-resistance silicon semiconductor
A U-shaped groove 37b having a depth reaching 8 is formed (FIG. 2 (c)).
次に例えば熱燐酸を用いてシリコン窒化膜42の側面を
所望の距離だけサイドエツチングし、シリコン窒化膜42
の側面を後退させる（第２図（ｄ））。次いで犠牲酸化
とウエツトエツチング等でRIE法による損傷や汚染等を
除去した後、シリコン酸化膜43を除去する。その後シリ
コン窒化膜42をマスクとして選択酸化によりゲート酸化
膜44を形成する（第２図（ｅ））。次にゲート電極とし
て燐添加多結晶シリコン45を例えば減圧化学気相成長法
で堆積し、燐添加多結晶シリコン45をエツチバツクする
ことによりシリコン窒化膜42を露出させる（第２図
（ｆ））。続いて前記シリコン窒化膜42をマスクとして
選択酸化によりシリコン酸化膜46を形成した後、シリコ
ン窒化膜42とシリコン酸化膜39を順次除去する（第２図
（ｇ））。次に前記シリコン酸化膜46をマスクとしてｐ
型のチヤネル領域40に到達する深さの溝37cを形成する
（第２図（ｈ））。しかる後ソース電極として例えばAl
47を堆積する。さらにフオトレジストをマスクとしてAl
47をパタンニングし、ドレイン電極としてAl48を低抵抗
単結晶シリコン半導体基板の第２主面側に堆積すること
により、縦型の高耐圧大電流MIS型半導体装置が完成す
る（第２図（ｉ））。Next, the side surface of the silicon nitride film 42 is side-etched by a desired distance using, for example, hot phosphoric acid to form the silicon nitride film 42.
Is retracted (FIG. 2 (d)). Next, after removing damage, contamination, and the like by the RIE method by sacrificial oxidation and wet etching, the silicon oxide film 43 is removed. Thereafter, a gate oxide film 44 is formed by selective oxidation using the silicon nitride film 42 as a mask (FIG. 2E). Next, phosphorus-added polycrystalline silicon 45 is deposited as a gate electrode by, for example, a low pressure chemical vapor deposition method, and the silicon nitride film 42 is exposed by etching the phosphorus-added polycrystalline silicon 45 (FIG. 2 (f)). Subsequently, after the silicon oxide film 46 is formed by selective oxidation using the silicon nitride film 42 as a mask, the silicon nitride film 42 and the silicon oxide film 39 are sequentially removed (FIG. 2 (g)). Next, using the silicon oxide film 46 as a mask, p
A groove 37c having a depth reaching the channel region 40 of the mold is formed (FIG. 2 (h)). Thereafter, as a source electrode, for example, Al
Deposit 47. Furthermore, using photoresist as a mask, Al
47, and Al48 is deposited as a drain electrode on the second main surface side of the low-resistance single-crystal silicon semiconductor substrate, thereby completing a vertical high-voltage large-current MIS semiconductor device (FIG. 2 (i) )).
かかる本実施例の製造方法においても、第１図の実施
例と同様の効果が得られる。すなわち、 ａ） 自己整合技術の導入により、ゲートの溝エツチン
グからソース電極コンタクトまでマスク１枚で形成が可
能であり、素子の微細化を図ることができ、単位面積当
りのゲート幅を増やすことができるため、高耐圧大電流
MIS型半導体装置の高性能化が可能である。In the manufacturing method of this embodiment, the same effects as those of the embodiment of FIG. 1 can be obtained. A) By introducing a self-alignment technique, it is possible to form a single mask from the etching of the gate groove to the contact of the source electrode, and it is possible to miniaturize the element and increase the gate width per unit area. High voltage and high current
The performance of the MIS type semiconductor device can be improved.
ｂ） チヤネル領域の電位をソース電位に固定するため
の電極コンタクトを自己整合技術を用いて縦方向に取つ
ているため、実効ゲート幅とパターン上でのゲート幅が
一致し、単位面積当りのゲート幅を増やすことができ、
高耐圧大電流MIS型半導体装置の高性能化が可能であ
る。b) Since the electrode contact for fixing the potential of the channel region to the source potential is made in the vertical direction by using the self-alignment technique, the effective gate width matches the gate width on the pattern, and the gate per unit area You can increase the width,
It is possible to improve the performance of a high withstand voltage and large current MIS type semiconductor device.
ｃ） ゲート酸化膜形成の際、耐酸化性のマスクが溝の
コーナー部より後退しているため、溝上部のコーナー部
でゲート酸化膜が薄くなり、ゲート酸化膜の耐圧劣化に
よる信頼性の低下といつた問題点を解消することがで
き、高信頼性が得られる。c) During the formation of the gate oxide film, the oxidation-resistant mask is recessed from the corner of the groove, so that the gate oxide film becomes thinner at the upper corner of the groove, and the reliability is reduced due to deterioration of the withstand voltage of the gate oxide film. Problem can be solved, and high reliability can be obtained.
等の利点を有する。And so on.
以上説明したように、本発明に係る半導体装置の製造
方法によれば、 （１） 一導電型チヤネル領域形成後、自己整合技術を
用いてマスク１枚でゲートまわりの加工から電極のコン
タクトホールの形成まで行えるため、単位セルの微細化
が可能であり、低オン抵抗化をねらいとした半導体装置
を形成できる。As described above, according to the method of manufacturing a semiconductor device according to the present invention, (1) after forming a one-conductivity-type channel region, using a single mask, processing around a gate with a single mask to form a contact hole for an electrode. Since formation can be performed, a unit cell can be miniaturized, and a semiconductor device aimed at lowering on-resistance can be formed.
（２） 一導電型チヤネル領域の電極コンタクトを自己
整合プロセスを用いて縦方向に取つているため、実効チ
ヤネル幅とパターン上でのゲート幅が同一となり、低オ
ン抵抗化が容易に達成でき、素子の高性能化が可能にな
る。(2) Since the electrode contact in the one-conductivity-type channel region is formed in the vertical direction using a self-alignment process, the effective channel width and the gate width on the pattern become the same, and a low on-resistance can be easily achieved. The performance of the device can be improved.
（３） ゲート酸化膜形成の際、耐酸化性のマスクが溝
のコーナー部より後退しているため、溝上部のコーナー
部でのゲート酸化膜は薄くならず、ゲート酸化膜の耐圧
劣化による信頼性の低下といつた問題点を解消できる。(3) Since the oxidation-resistant mask is recessed from the corner of the groove when forming the gate oxide film, the gate oxide film at the corner at the top of the groove does not become thin, and reliability due to deterioration of the withstand voltage of the gate oxide film is reduced. It can solve the problem of deterioration of the sex.
等の効果が得られる。And the like.
第１図は本発明による半導体装置の製造方法の一実施例
を説明するための工程断面図、第２図は本発明の別の実
施例を説明するための工程断面図、第３図は従来の半導
体装置の製造方法の一例を示す工程断面図、第４図はそ
の従来の半導体装置の平面パターンを示す図、第５図は
同じく従来の半導体装置の製造方法を示す工程断面図で
ある。 24,37……ｎ型低抵抗単結晶シリコン半導体基板、24a,2
4b,24c……溝、25,38……ｎ型の高抵抗単結晶シリコン
半導体層、26,39……シリコン酸化膜、27,40……ｐ型の
チヤネル領域、28,41……ｎ型のソース領域、29,42……
シリコン窒化膜、30,43……シリコン酸化膜、31……シ
リコン酸化膜、32,44……ゲート酸化膜、33,45……燐添
加多結晶シリコン、34,46……シリコン酸化膜、35,47…
…ソース電極、36,48……ドレイン電極、37a,37b,37c…
…溝。FIG. 1 is a process sectional view for explaining one embodiment of a method of manufacturing a semiconductor device according to the present invention, FIG. 2 is a process sectional view for explaining another embodiment of the present invention, and FIG. FIG. 4 is a process sectional view showing an example of a method for manufacturing a semiconductor device of the prior art, FIG. 4 is a view showing a plane pattern of the conventional semiconductor device, and FIG. 24,37 ... n-type low-resistance single-crystal silicon semiconductor substrate, 24a, 2
4b, 24c groove, 25, 38 n-type high-resistance single-crystal silicon semiconductor layer, 26, 39 silicon oxide film, 27, 40 p-type channel region, 28, 41 n-type Source area of 29,42 ……
Silicon nitride film, 30, 43 silicon oxide film, 31 silicon oxide film, 32, 44 gate oxide film, 33, 45 phosphorous-doped polycrystalline silicon, 34, 46 silicon oxide film, 35 , 47…
… Source electrode, 36,48 …… Drain electrode, 37a, 37b, 37c…
…groove.
Claims (2)
を有する第１の単結晶シリコン半導体層，第２の導電型
を有する第２の単結晶シリコン半導体層，第１の導電型
を有する第３の単結晶シリコン半導体層から成る積層構
造の単結晶シリコン半導体基板を用いてMOS型半導体装
置を製造する方法において、 前記第１主面上に第１の絶縁膜と第２の絶縁膜を順次堆
積する工程と、 フオトリソグラフイーで描画したレジストをマスクとし
て前記第２の絶縁膜と前記第１の絶縁膜を順次除去し、
第１と第２の絶縁膜の加工面及び前記第１の単結晶半導
体層の表面からなる第１のＵ字型の溝を形成する工程
と、 前記レジスト除去後に第３の絶縁膜を堆積し、続いて異
方性エツチングにより平坦部の該第３の絶縁膜のみを除
去し、前記第１のＵ字型の溝の側壁部のみに第３の絶縁
膜を残す工程と、 前記第２の絶縁膜と第３の絶縁膜をマスクとして前記第
１の単結晶シリコン半導体層と第２の単結晶シリコン半
導体層を異方性エツチングし、前記第２の単結晶シリコ
ン半導体層よりも深い第２のＵ字型の溝を形成する工程
と、 前記第２及び第３の絶縁膜を除去し、前記第１の絶縁膜
をマスクとして前記第２のＵ字型の溝の内面を酸化して
ゲート酸化膜を形成する工程と、 前記第２のＵ字型の溝内部に非単結晶シリコン半導体層
を埋め込み前記単結晶シリコン半導体基板の表面を平坦
化する工程と、 前記第１の主面側で前記第１の絶縁膜で覆われていない
領域を選択酸化することにより第４の絶縁膜を形成する
工程と、 前記第１の絶縁膜を除去した後、前記第４の絶縁膜をマ
スクとして前記第１の単結晶シリコン半導体層を除去
し、前記第２の単結晶シリコン半導体層に至る第３の溝
を形成する工程と、 前記第３の溝に電極金属を埋め込む工程と、 を含むことを特徴とする半導体装置の製造方法。1. A first single-crystal silicon semiconductor layer having a first conductivity type, a second single-crystal silicon semiconductor layer having a second conductivity type, and a first A method of manufacturing a MOS type semiconductor device using a single crystal silicon semiconductor substrate having a stacked structure composed of a third single crystal silicon semiconductor layer having the following conductivity type, comprising: a first insulating film on the first main surface; 2) sequentially depositing an insulating film, and using the resist drawn by photolithography as a mask, the second insulating film and the first insulating film are sequentially removed;
Forming a first U-shaped groove consisting of a processed surface of the first and second insulating films and a surface of the first single crystal semiconductor layer; and depositing a third insulating film after removing the resist. Removing only the third insulating film in the flat portion by anisotropic etching, and leaving the third insulating film only on the side wall portion of the first U-shaped groove; The first single-crystal silicon semiconductor layer and the second single-crystal silicon semiconductor layer are anisotropically etched using the insulating film and the third insulating film as masks, and the second single-crystal silicon semiconductor layer is deeper than the second single-crystal silicon semiconductor layer. Forming a U-shaped groove, and removing the second and third insulating films and oxidizing an inner surface of the second U-shaped groove using the first insulating film as a mask to form a gate. Forming an oxide film; and before embedding a non-single-crystal silicon semiconductor layer inside the second U-shaped groove. Flattening the surface of the single crystal silicon semiconductor substrate; and forming a fourth insulating film by selectively oxidizing a region of the first main surface that is not covered with the first insulating film. Removing the first insulating film, removing the first single-crystal silicon semiconductor layer using the fourth insulating film as a mask, and forming a third groove reaching the second single-crystal silicon semiconductor layer. And a step of embedding an electrode metal in the third groove.
を形成した後、第２の絶縁膜をマスクとして該第１のＵ
字型溝部に前記第２のＵ字型の溝を形成し、再び前記第
２の絶縁膜をマスクとして第１の絶縁膜の側面のみを等
方エツチングして所望の距離だけ後退させ、その後前記
第２の絶縁膜を除去して、ゲート酸化以降は請求項１記
載の工程と同じ工程を有することを特徴とする半導体装
置の製造方法。2. The method according to claim 1, wherein after forming the first U-shaped groove, the first U-shaped groove is formed using the second insulating film as a mask.
The second U-shaped groove is formed in the U-shaped groove, and only the side surface of the first insulating film is isotropically etched again using the second insulating film as a mask, and is retreated by a desired distance. 2. A method for manufacturing a semiconductor device, comprising: removing the second insulating film, and performing the same steps as in claim 1 after the gate oxidation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1145464A JP2757262B2 (en) | 1989-06-09 | 1989-06-09 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1145464A JP2757262B2 (en) | 1989-06-09 | 1989-06-09 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0311765A JPH0311765A (en) | 1991-01-21 |
| JP2757262B2 true JP2757262B2 (en) | 1998-05-25 |
Family
ID=15385845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1145464A Expired - Lifetime JP2757262B2 (en) | 1989-06-09 | 1989-06-09 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2757262B2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4300806C1 (en) * | 1993-01-14 | 1993-12-23 | Siemens Ag | Vertical MOS transistor prodn. - with reduced trench spacing, without parasitic bipolar effects |
| US5648670A (en) * | 1995-06-07 | 1997-07-15 | Sgs-Thomson Microelectronics, Inc. | Trench MOS-gated device with a minimum number of masks |
| JP3502531B2 (en) | 1997-08-28 | 2004-03-02 | 株式会社ルネサステクノロジ | Method for manufacturing semiconductor device |
| US6218701B1 (en) * | 1999-04-30 | 2001-04-17 | Intersil Corporation | Power MOS device with increased channel width and process for forming same |
| KR100549950B1 (en) * | 2003-12-23 | 2006-02-07 | 삼성전자주식회사 | Method for manufacturing recess type MOS transistor and structure at the same |
| DE102004057237B4 (en) * | 2004-11-26 | 2007-02-08 | Infineon Technologies Ag | Method for producing contact holes in a semiconductor body and transistor with a vertical structure |
-
1989
- 1989-06-09 JP JP1145464A patent/JP2757262B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0311765A (en) | 1991-01-21 |
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