JPH02143178A - Voltage regulation circuit - Google Patents

Abstract

PURPOSE:To surely test all dividing voltage level in a short time by providing a switch circuit to interrupt the current made to flow in a dividing voltage circuit with the condition that an input signal voltage (VIN) is impressed to one end of the dividing voltage circuit. CONSTITUTION:When an input test signal S3 is made to be a 'H' level at the testing, a contact 202 for test operation is turned to ON condition while a contact 201 for usual operation is OFF. Then, a line between the input signal terminal I and terminal 100H at high potential side is interrupted and a bypass loop through the contact 202 for test operation is formed between the terminal 100L at low potential side instead. The current is made to flow according to the circuit passing through the input signal terminal I and the contact 202 for test operation, and no voltage drop is generated on each resistor R1-R4 as the voltage dividing circuit 100 is bypassed. As a result, the output signal voltages VOUT(=VIN) with the same values for all are disclused from each volt age dividing stage, thereby a function test can be surely performed in a short time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a voltage regulation circuit for an electronic volute, etc.
In particular, the present invention relates to a voltage regulating circuit having a configuration suitable for functional testing of the voltage regulating circuit.

2. Description of the Related Art In various electronic devices, a voltage adjustment circuit is used to arbitrarily adjust the level of a signal voltage input manually. In addition to manual voltage regulation, as electronic devices become more automated, there is a demand for automatic voltage adjustment functions that are electronically controlled.

Various tests are conducted to evaluate the performance of such voltage regulating circuits. Test items include a direct current test that tests each signal power voltage level, a transmission test that tests frequency response, and a functional test that takes a relatively short time compared to other tests. The present invention relates to a voltage regulating circuit suitable for performing this functional test.

[Conventional technology]

First, FIG. 10 shows an outline of a conventional voltage regulating circuit. The voltage adjustment circuit includes a voltage divider circuit 100 that divides the input signal voltage VIN into voltages at multiple levels, a load circuit 101 connected in series to the voltage divider circuit 100, and an output signal from each stage of the voltage divider circuit 100. A selection circuit 102 that selectively outputs one of the voltages is configured. In Figure 10, ■
is the reference voltage, and ■ is the output signal voltage.

RE F OUT The voltage dividing circuit 100 and the load circuit 101 have an input signal voltage V
A series circuit is formed between l N and the reference voltage V
REF is configured, and the voltage drop due to the current flowing through the series circuit is output as a divided voltage of each stage.

Selection circuit], 02 is composed of a transistor switching circuit using, for example, a transmission gate,
One of the levels of the output signal voltage of the voltage dividing circuit 100 is selected by the switching control signals S1 and S2. During testing, the switching control signal S
, S select the output signal voltage for each level of the voltage divider circuit 100, set the maximum amplitude value VOH and the minimum amplitude value VOL (not shown) for each individual level, and set the selected voltage. A check is made to see if the level is within the maximum amplitude value VOR and the minimum amplitude value VOL.

[Problem to be solved by the invention]

In the above-mentioned conventional voltage adjustment circuit, when performing a functional test, it is necessary to perform measurement by setting the maximum amplitude value VOH1 and the minimum amplitude value VOL for each output signal voltage of each level, which requires a lot of testing time and work effort. was necessary.

Furthermore, since the amplitude is small during low-level testing, it is difficult to set the maximum amplitude l1aVOH and the minimum amplitude value VOL, and there is a risk that measurement may become virtually impossible.

SUMMARY OF THE INVENTION An object of the present invention is to provide a voltage regulating circuit that can reliably, quickly and quickly test a circuit that responds to all levels when performing a functional test.

[Means to solve the problem]

In order to solve the above problems, the present invention provides an input signal voltage V
Voltage divider circuit 1 that divides IN into voltages at several different levels
00 and a selection circuit 102 that selectively outputs a voltage at one level of the output signal voltage of the voltage dividing circuit 100, when testing the voltage adjusting circuit, The circuit 100 is configured to include a switch circuit 200 that cuts off the current flowing through the voltage dividing circuit 100 when the input signal voltage "IN" is applied to one end of the circuit 100.

C action] According to the present invention, the switch circuit 200 interrupts the current of the voltage divider circuits 1 and 00 during the test, but the switch circuit 200 interrupts the current of the voltage divider circuits 1 and
A human power signal voltage is applied to one end of 0.

In this case, the human input signal voltage VIN is still applied to all the voltage dividing stages of the voltage dividing circuit 100, but since no current flows, there is no voltage drop at each voltage dividing stage, and all voltage from each voltage dividing stage is The output signal voltage V has the same value. ,□(-V ,N
) appears.

As a result, it is not necessary to set the maximum amplitude value VOH1 and the minimum amplitude value VOL according to the level of each voltage dividing stage, and also, if the output signal voltage V is too low, it is not necessary to set the maximum amplitude value VOH and minimum amplitude value VOL. There are no problems that would make it difficult. Therefore, a functional test can be performed reliably in a short time.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

First Embodiment (See FIGS. 2 to 6) FIG. 2 shows an outline of the first embodiment. In FIG. 2, a main circuit 103 surrounded by a broken line is the same as the conventional voltage regulating circuit shown in FIG. 10, and the same reference numerals are given and the explanation thereof will be omitted.

What is different in Fig. 2 from Fig. 10 is the input signal terminal ■
The difference is that a switch circuit 200 for switching operation modes is inserted between the voltage divider circuit 100 and the voltage divider circuit 100. Details of this switch circuit 200 are shown in FIG.

As shown in FIG. 3, the switch circuit 200 includes a normal operation contact 201 inserted between the input signal terminal I and the high potential side terminal 100t+ of the voltage dividing circuit 100, and a contact 201 for normal operation inserted between the input signal terminal I and the voltage dividing circuit 100. and a test operation contact 202 inserted between the low potential side terminal 1-00L of the circuit 100. The normal operation contact 201 is turned ON (closed) during normal operation and turned OFF (open) during testing. On the contrary, the test operation contact 202 is turned off during normal operation and turned on during testing.

A specific example of the above switch circuit 200 and circuit 103 is shown in FIG.

As shown in FIG. 4, the voltage dividing circuit 100 includes a plurality of resistors R1
.about.R4 are connected in series, and the divided voltage at each connection point is applied to the drain of each transmission gate T G t of the selection circuit 102 .

A load circuit 101 is a low potential side terminal 100 of a voltage dividing circuit 100.
, is a load resistor connected to the reference signal terminal REF. Therefore, input signal terminal ■ and reference signal terminal REF
Between them, the resistors R1 to R4 and the load circuit 101 constitute a series circuit, and the JI voltage for each portion is determined by the current flowing through this n-series circuit.

The selection circuit 102 has a drain connected to the connection point of each resistor R""" R4, and a transmission gate TG1 and an inverter INV, which perform an ON-OFF operation when a switching control signal SI is applied to the gate, and a transmission gate T. Transmission gate TG2 and Inno Niri T which receive the output from the source of G1 at the drain and perform ON-OFF operation according to the switching control signal S2 applied to the gate.
Voltage follower circuit 10 for outputting the output signal voltage of NV2 and transmission gate TG2 to the outside
It consists of 4.

The switch circuit 200 uses a transmission gate TG3 as a contact 201 for normal operation and a transmission gate TG4 as a contact 202 for test operation. Inverter INV3 outputs test input signal S
3 logic into transmission gates TG, TG4
It is intended to match.

Next, the operation will be explained.

Figure 5 shows the test input signal S1 switching control 0-small signal S in the normal operation mode and test mode.
, S and input signal voltage V, output 1 2
The relationship between IN signal voltage is shown. In the normal operation mode, the test input signal S3 is at the logic "L" level, and in the test mode, the test input signal s3 is at the logic "H" level.

Assume now that the input signal voltage vlNIJ· shown in FIG. 6(a) is given. At this time, the test input signal S3 is
When it is at the L level, the normal operation contact 201 is ON and tested (the operation contact 202 is OFF. Therefore, the current due to the input signal voltage VIN flows to the high potential side terminal 100,
, flows through the resistors R1 to R4, the low potential side terminal 100, the load circuit 101, and the reference signal pair terminal REF, and the resulting voltage drop, that is, the divided voltage, is output to each transmission gate TG. . Due to the signal logic of the switching control signal Sl and the switching control signal S2 at this time, the output signal voltage V as shown in FIG.
is selectively output OUT. This output signal voltage V is switching 0 [J
By sequentially switching the switching control signal S2 and the switching control signal S2 according to FIG.
The waveform will be as shown in Figure (b). Note that the reference voltage V
are GND potential, potential resistance -1 to R4 EP, and all have the same value. In this way, in the normal operation mode, the test input 1g signal S3 is fixed at the ``L'' level, and the UT is adjusted to any variable output signal voltage V by appropriately combining the switching control signal SI and the switching control signal 18 S2. I can do it.

On the other hand, when conducting a test, as shown in FIG. 5, the test input signal S3 is set to "H" level to enter the test mode. At this time, the switching control signal S1 and the switching control signal S2 are undefined. When test input signal S3 is set to “H” level, normal operation contact 2
01 is OFF and the test operation contact 202 is turned ON. Then, the input signal terminal I and the high potential side terminal 100,
The contact 20 for test operation is cut off between the
A bypass loop passing through 2 is formed between the low potential side terminal 100L and the low potential side terminal 100L. The current does not pass through the voltage divider circuit 100,
The signal flows through the human power signal terminal I, the test operation contact 202, the low potential side terminal 100, the load circuit 101, and the reference signal terminal REF. Since the voltage divider circuit 100 is bypassed, no voltage drop occurs across each of the resistors Ri to R4. However, the input signal voltage vIN is applied to the low potential side terminal 100, and therefore the resistors R to R1 are connected to the high potential side terminal 100.
The same potential as the input signal voltage VIN is applied to each point, and as shown in FIG. 6(C), this input signal voltage VIN is directly applied to the transmission gate T.
It will be output to G.

As a result, it is not necessary to set the maximum amplitude value VOH and the minimum amplitude value VOL for each divided voltage level in the voltage dividing circuit 100, and the health of the circuit 103 can be tested. Further, since the output signal voltage V does not fall below the input signal voltage vIN, the problem that the voltage is too low to set the maximum amplitude value VOH1 and the minimum amplitude value VOL is solved.

Second Embodiment (Refer to FIGS. 7 to 9) In contrast to the first embodiment, the switch circuit 200 is inserted between the input signal terminal I and the voltage dividing circuit 100. , a switch circuit 300 is inserted between the load circuit 101 and the reference signal terminal REF. In this second embodiment, the same parts as in FIG. 10 and the first embodiment are given the same reference numerals, and the explanation thereof will be omitted.

FIG. 7 shows an outline of the second embodiment. As can be seen from FIG. 7, the switch circuit 300 is inserted between the load circuit 101 and the reference signal terminal REF. Details of this switch circuit 300 are shown in FIG.

As shown in FIG. 8, the switch circuit 300 is a voltage divider circuit 1
00 is a contact inserted in series in the series circuit of the load circuit 101 and the reference signal terminal REF, and is turned off in normal operation mode.
N, can be turned OFF in test mode.

Specific examples of the above switch circuit 300 and circuit 103 are shown in the ninth section.
As shown in the figure. As shown in FIG. 9, the switch circuit 30
0 is established by a transmission gate TG5 which is ON-OFF controlled by a test input signal S3 and an inverter INV4 for gate logic adjustment. circuit 10
3 has been explained previously, so its explanation will be omitted.

Next, the operation will be briefly explained.

Press to normal operation mode, test input signal S3 is L'
At this time, the switch circuit 300 is ON, current flows through the series circuit, and an output signal voltage V 1 is generated as shown in FIG.

In the UT test mode, the test input signal S3 is set to "H level", and since the switch circuit 300 is OFF at this time, the current is cut off and no divided voltage is generated in the voltage dividing circuit 100. However, the high potential side terminal 100, , is still applied with the input signal voltage vIN, therefore, 1 is applied to each point of the resistor RH and the low potential side terminal 100L.
．． 4, the input signal voltage VIN appears as is.

As a result, the maximum amplitude value VOH1 for each divided voltage level
Tests can be performed without setting the minimum amplitude value VOL. Also, since the output signal voltage V does not decrease as much as the input signal voltage V1 - the maximum amplitude value VOH
，! The problem of not being able to set a small amplitude value VOL is solved.

〔Effect of the invention〕

As described above, according to the present invention, when performing a functional test,
It becomes possible to test all divided voltage levels reliably and in a short time.

[Brief explanation of the drawing]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram of the first embodiment, Fig. 3 is a detailed block diagram of the first embodiment, and Fig. 4 is a block diagram showing a specific example of the first embodiment. Figure 5 is an explanatory diagram of signal relationships in each operation mode, Figure 6 is an explanatory diagram showing each signal waveform, Figure ff17 is a block diagram of the second embodiment, and Figure 8 is a detailed block diagram of the second embodiment. FIG. 9 is a block diagram showing a specific example of the second embodiment, and FIG. 10 is a block diagram of a conventional voltage adjustment circuit. 100... Voltage dividing circuit i o o,... High potential side terminal 100,... Low potential side terminal 101... Load circuit 102... Selection circuit 103... Main circuit 104... Voltage follower circuit 200...Switch circuit 201...Normal operation contact 202...Test operation contact 300...Switch circuit ■...Input terminal 0...Output terminal REF...Reference terminal VIN...Human signal voltage V...Output signal voltage UT ■...Basic voltage REF Sl, S2...Switching control signal S3.
...Tess] Human power signal An explanatory diagram of the principle of the present invention. Fig. 1. An explanatory diagram of each operation mode (No. 8). Fig. 5. An explanatory diagram showing each signal waveform. Fig. 6. Figure 9 shows the diagram of a conventional voltage regulator circuit. Figure 10 is a scrap.

Claims (1)

[Claims] A voltage dividing circuit (100) that divides an input signal voltage (V_I_N) into voltages at a plurality of different levels, and this voltage dividing circuit (100).
A selection circuit (102) that selectively outputs a voltage at one level of the output signal voltages (00), wherein the voltage dividing circuit (100)
A voltage regulating circuit comprising a switch circuit (200, 300) that cuts off a current flowing through the voltage dividing circuit (100) when the input signal voltage (V_I_N) is applied to one end of the voltage regulator circuit.