JP3490273B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a plurality of functional blocks.

[0002]

2. Description of the Related Art Generally, a semiconductor integrated circuit device has a plurality of functional blocks such as a mega cell block and a random block. Here, the mega cell block is a general-purpose circuit that has already been designed.
U, a memory (RAM, ROM), a multiplier, and the like. The random block is a circuit designed according to the product (integrated circuit), and is, for example, programmable I.D. O
(I / O device), serial I.D. O, DMA (Direct Mem
ory Access) controller or the like.

FIG. 5 shows an example of the configuration of a conventional semiconductor integrated circuit device having such a plurality of functional blocks. This conventional semiconductor integrated circuit device 50 has three functional blocks 8 ₁ , 8 ₂ , 8 ₃ . A signal is externally input to the functional block 8 ₁ via the pad 2 and the input buffer 3, and other functional blocks 8 ₂ and 8 ₃
A signal is also input from. Then, the predetermined processing is performed,
The processing result is output to the function block 8 ₂ or the function block 8 ₃ .

Similarly, a signal is externally input to the functional block 8 ₃ via the pad and the input buffer 3, and a signal is also input from another functional block 8 ₁ . Then, predetermined processing is performed, and the processing result is output to the function block 8 ₁ or output to the outside via the system path S, the output buffer 7, and the pad P. In addition,
The system path S is a signal line during normal operation and is not used for testing the semiconductor integrated circuit device 50.

Further, the function block 8 ₂ is the function block 8
_When the signal from _{1 is} received, predetermined processing is performed, and the processing result is output to the outside via the output buffer 7 and the pad 2.

In a semiconductor integrated circuit device having such a plurality of functional blocks, a test circuit is generally provided. The test circuit includes a separation circuit for separating the functional blocks in the test mode in order to easily perform the test. A multiplexer is generally used as this separation circuit. For example, a configuration in which a test circuit is provided in the conventional semiconductor integrated circuit device 50 shown in FIG. 5 is shown in FIG.
Shown in. The test circuit provided in the semiconductor integrated circuit device 60 shown in FIG. 6 includes a multiplexer 62 and a bidirectional buffer, and controls the bidirectional signal line N between the functional block 8 ₁ and the functional block 8 _2. , Is configured to observe.

The multiplexer 62 selects one of the system path and the bidirectional signal line N based on the control signal T1 and connects it to the bidirectional buffer 64. The bidirectional buffer 64 operates based on the control signals T2 and T3.

The control signals are T1 = 0, T2 = 1, T3 = 0.
When is, it is the mode in which the system operates and the test is not performed. At this time, the output of the terminal C of the functional block 8 ₃ is selected by the multiplexer 62 and sent to the pad 9a via the bidirectional buffer 64.

On the other hand, when performing function block ₈₁ of the test terminal A (that is, the control and observation), the control signal T
By setting 1 = 1 and controlling the control signals T2 and T3 in accordance with the input / output mode of the terminal A, the pad P is connected to the terminal A.
Apply the input to and observe the output. The control method may be an external terminal or an enable output for controlling the input / output direction of the terminal A of the functional block 8 ₁ . When the terminal A is being tested, the terminal B of the functional block 8 ₂ is controlled to a high impedance state. Although this control method will not be described in detail, it is performed by controlling the chip enable terminal of the functional block 8 ₁ in this test mode.

Further functional block 8 _second test (control, observation) of the terminal B likewise when performing the control signal T1 T1
= 1 and controlling the control signals T2 and T3 in accordance with the input / output mode of the terminal B to apply an input from the pad P to the terminal B and observe the output.

[0011]

In such a conventional semiconductor integrated circuit device, the terminal A of the functional block 8 ₁ is used.
And the terminal B of the functional block 8 ₂ can be tested. However, the multiplexer 6 is added to the system path S.
Since 2 is added, there is a problem that a signal delay increases during system operation.

In the example shown in FIG. 6, one connection signal line N
However, in practice, it is necessary to use the pad P also for a larger number of connection signal lines. If multiple connection signal lines are also used, there is a problem that the number of inserted tests becomes considerably complicated.

The present invention has been made in consideration of the above circumstances, and an object of the present invention is to provide a semiconductor integrated circuit device including a test circuit capable of preventing an increase in signal delay as much as possible. To do.

[0014]

A semiconductor integrated circuit device according to the present invention has a first pad to which a power source is applied and at least one second pad to which a signal is applied, each having a predetermined processing function. connecting at least two functional blocks, the system path connecting the at least one functional block of said second pad and the at least two functional blocks, between the at least two functional blocks having A first multiplexer circuit added on the unidirectional signal line, an OR gate for receiving a first control signal and an enable signal, and a second multiplexer provided between the second pad and the system path. A first buffer circuit having an input buffer that receives a signal from a pad and an output buffer that operates based on the output of the OR gate; and the second buffer circuit. A second buffer circuit that is connected to the second pad and has an input buffer that receives a signal from the second pad and an output buffer that operates based on a second control signal and sends an output to the second pad; One of the bidirectional signal lines connecting the at least two functional blocks is selected based on a third control signal, and the selected bidirectional signal line is connected to the output of the input buffer of the second buffer circuit. When observing the selection circuit for transmission and the signal flowing through the bidirectional signal line, one of the bidirectional signal lines is selected based on the fourth control signal, and the signal flowing through the selected signal line is selected. To the output buffer of the second buffer circuit and observing the output of the functional block,
A second output terminal for selecting one output terminal from the output terminals of the functional block or the output terminal of the first multiplexer and transmitting the output from the selected output terminal to the output buffer of the second buffer circuit. Of the second buffer circuit, and the output of the input buffer of the second buffer circuit is sent to the input terminal of the functional block via the first multiplexer.

Further, when the second pad is used only for input, it is preferable that the enable signal for the output buffer is set so that the output buffer of the first buffer circuit is always turned off.

Further, when the second pad is used only for output, it is preferable that the enable signal for the output buffer is set so that the output buffer of the first buffer circuit is always turned on.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor integrated circuit device according to the present invention will be described with reference to FIGS.

FIG. 1 is a circuit diagram showing the configuration of a specific example of a test circuit provided in the semiconductor integrated circuit device of this embodiment, and FIG. 2 is a block diagram showing the configuration of the semiconductor integrated circuit device of this embodiment. It is a figure.

The semiconductor integrated circuit device 1 of this embodiment
Is a plurality of functional blocks 8 ₁ ,
8 ₂ and 8 ₃ , a multiplexer 5 provided in a path between the functional blocks, and a test circuit 10 provided for each pad 2 except the power supply pad.

The test circuit 10, as shown in FIG.
The gate 11, the bidirectional buffer 12, the bidirectional buffer 14, the tristate gate 16, and the multiplexer 18 are provided.

The OR gate 11 is turned on based on the enable signal of the system (semiconductor integrated circuit device) and the control signal T4.
The R calculation is performed and the calculation result is sent to the bidirectional buffer 12. The bidirectional buffer 12 has an input buffer and an output buffer whose operation is controlled according to the output of the OR gate, and is provided between the pad 2 and the system path S. Then, it functions as an input buffer, an output buffer, or a bidirectional buffer according to the output of the OR gate 11.

The bidirectional buffer 14 is connected to the pad 2 and operates based on the control signal T3. The bidirectional buffer 14 sends the test input signal input via the pad 2 to the tri-state gate 16 and at the same time n
The signal is sent to (≧ 1) signal lines IN ₁ , ... IN _n . These signal lines IN ₁ , ... IN _n are signal lines for supplying signals to the input terminals of the functional blocks, and the multiplexer 5 provided in the path between the functional blocks as shown in FIG.
Connected to the input terminal of the functional block via.

The tri-state gate 16 selects one signal line from the _k signal lines BI ₁ , ... BI _k based on the k (≧ 1) control signals T2 ₁ , ... T2 _k . Then, the test input signal sent through the bidirectional buffer 14 is sent to the selected signal line. Signal lines BI ₁ , ... BI _k are signal lines for observing a bidirectional signal flowing in a bidirectional path between the functional blocks, and are shown in FIG.
It is connected to a bidirectional path between the functional blocks as shown in.

The multiplexer 18 operates on the m signal lines OP based on the j (≧ 1) control signals T1 ₁ , ... T1 _j.
1 , ... OP _m and one signal line from the _k signal lines BI ₁ , ... BI _k are selected, and the signal flowing through the selected signal line is sent to the pad 2 via the bidirectional buffer 14. To do. Note that the signal lines OP ₁ , ... OP _m are signal lines for observing the output of the functional block and are connected to the output terminal of the functional block or the output terminal of the multiplexer as shown in FIG.

Next, the operation of the test circuit 10 will be described. First, when the bidirectional buffer 12 is used only as an input, the enable signal of the buffer 12 is fixed to the power supply voltage V _{DD as shown} in FIG. Further, when the bidirectional buffer 12 is used only for output, FIG.
The system enable signal is connected to the ground power GN
Fix to D. When the bidirectional buffer 12 is used as a tri-state buffer or a bidirectional buffer, FIG.
It is configured as it is as shown in (c).

In the test mode, the control signal T4 is set to "1". Then, the output buffer of the bidirectional buffer 12 is brought into a high impedance state. As a result, the test signal can be input / output from / to the pad 2 through the bidirectional buffer 14 dedicated to the test.

In this state (control signal T4 = 1), the control signal T3 is set to "1" and the control signal T
When 2 ₁ , ... T2 _k are all set to "1", the output buffer of the bidirectional buffer 14 and the tri-state gate 16 are set.
Also becomes a high impedance state, and a test signal can be supplied from the pad 2 to the signal lines IN ₁ , ... IN _n via the bidirectional buffer 14.

On the other hand, when observing the output of the functional block 8, the control signal T3 is set to "0" and the control signal T4 is set to "1".
And the control signals T2 ₁ , ..., T2 _k are all set to "1". Then, the output buffer of the bidirectional buffer 12 and the tri-state gate 16 are brought to a high impedance state, and the output buffer of the bidirectional buffer 14 is turned on. At this time, the control signal T
By selecting one signal line from the signal lines OP ₁ , ... OP _m on the basis of 1 ₁ , ... T 1 _j by the multiplexer, the signal flowing through the selected signal line can be observed at the pad 2. it can.

When observing the bidirectional signal of the functional block 8, the control signal T4 is set to "1" and the control signal T4 is set.
3 is controlled by an enable terminal that determines the signal direction of the bidirectional terminal of the functional block 8 or by an external terminal. Further, k control signals T2 ₁ ,
One control signal of T2 _k is controlled by an enable terminal that determines the signal direction of the bidirectional terminal of the functional block 8 or by controlling the signal direction by an external terminal, and the remaining k-1 All the control signals are set to "1". As a result, only one of the k buffers forming the tri-state gate 16 is turned on, and all the remaining buffers are in a high impedance state. At this time, using the control signals T1 ₁ , ... T1 _j , the k signal lines BI ₁ ,.
By selecting one signal line from _k , the signal flowing through the selected signal line can be observed at the pad 2. In addition, the test signal can be sent from the pad 2 to the functional block via the selected signal line.

In the normal operation mode other than the test mode, if the pad 2 is for input only, as shown in FIG.
If the enable signal terminal of the bidirectional buffer 12 is connected to the power supply as shown in (a) and the pad 2 is for output only, the enable signal terminal of the bidirectional buffer 12 is connected to the ground power supply as shown in FIG. 3 (b). Connected to. Also pad 2
If is for bidirectional, the system enable signal and the control signal T4 are both set to "0", so that the buffer 12 functions as a bidirectional buffer. As a result, the signal input from the pad 2 is sent to the functional block 8 via the buffer 12 and the system path S, and the output from the functional block 8 is sent to the pad 2 via the system path S and the buffer 12. Become.

As described above, according to the semiconductor integrated circuit device of the present embodiment, a signal can be supplied to the input terminal of the functional block to easily observe the output of the functional block, and the bidirectional terminals of the functional block can be connected. It is possible to easily input a signal and output a signal from the bidirectional terminal.

Further, unlike the conventional case, since the multiplexer is not added to the system path S, the signal delay can be made smaller than in the conventional case. It should be noted that although the signal delay also increases in response to the increase in load capacity due to the connection of the bidirectional buffer 14 to the system path S, the increase does not occur to the extent that a multiplexer is added to the system path S.

Further, although the multiplexer 18 is added in the present embodiment, it is in a high impedance state in the normal operation mode, and the signal delay due to the addition of the multiplexer 18 hardly occurs.

Since the signal delay during the normal operation can be reduced as compared with the conventional case, it is possible to prevent the performance deterioration of the semiconductor integrated circuit device due to the provision of the test circuit.

[0035]

As described above, according to the present invention, it is possible to prevent the increase of the signal delay due to the provision of the test circuit as much as possible, thereby preventing the deterioration of the performance of the semiconductor integrated circuit device. It becomes possible to prevent it.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a specific example of a test circuit according to an embodiment of a semiconductor integrated circuit device of the present invention.

FIG. 2 is a configuration diagram showing a schematic configuration of an embodiment of a semiconductor integrated circuit device according to the present invention.

FIG. 3 is a circuit diagram illustrating how the bidirectional buffer of the test circuit shown in FIG. 1 is used.

FIG. 4 is a schematic diagram illustrating a connection of a signal line to which the test circuit illustrated in FIG. 1 is connected to a functional block.

FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit device having no test circuit.

FIG. 6 is a block diagram showing a configuration of a conventional semiconductor integrated circuit device having a test circuit.

[Explanation of symbols]

1 Semiconductor Integrated Circuit Device 2 Pad 5 Multiplexer 8 ₁ , 8 ₂ , 8 ₃ Functional Block 10 Test Circuit 11 OR Gate 12 Bidirectional Buffer 14 Bidirectional Buffer 16 Tristate Gate 18 Multiplexer

─────────────────────────────────────────────────── ─── Continuation of the front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G01R 31/28-31/3193 H01L 21/822 H01L 27/04 H03K 19/00

Claims (3)

(57) [Claims] 1. A first pad to which a power source is applied, at least one second pad to which a signal is applied, at least two functional blocks each having a predetermined processing function, and the second pad. At least a system path that connects the one functional block, the first multiplexer the appended on the direction signal line connecting between at least two functional blocks of the pad and of the at least two functional blocks A circuit, an OR gate for receiving a first control signal and an enable signal, an input buffer provided between the second pad and the system path for receiving a signal from the second pad, and the OR gate. A first buffer circuit having an output buffer that operates based on an output; and a signal connected to the second pad and receiving a signal from the second pad. A second buffer circuit having an input buffer and an output buffer that operates based on a second control signal and sends an output to the second pad; and a bidirectional connection between the at least two functional blocks. A selection circuit that selects one of the signal lines based on a third control signal and transmits the output of the input buffer of the second buffer circuit to the selected bidirectional signal line, and flows through the bidirectional signal line. When observing a signal, one of the bidirectional signal lines is selected based on the fourth control signal, and the signal flowing through the selected signal line is transmitted to the output buffer of the second buffer circuit. , When observing the output of the functional block, select one output terminal from the output terminals of the functional block or the output terminal of the first multiplexer, and select from the selected output terminal. A second multiplexer for transmitting the output to the output buffer of the second buffer circuit, and the output of the input buffer of the second buffer circuit to the input terminal of the functional block via the first multiplexer. A semiconductor integrated circuit device characterized by being transmitted. 2. The enable signal to the output buffer is set so that the output buffer of the first buffer circuit is always turned off when the second pad is used only as an input. The semiconductor integrated circuit device according to claim 1. 3. The enable signal to the output buffer is set so that when the second pad is used only for output, the output buffer of the first buffer circuit is always turned on. The semiconductor integrated circuit device according to claim 1.