JPH02142187A - Insulated gate type field effect transistor - Google Patents
Insulated gate type field effect transistorInfo
- Publication number
- JPH02142187A JPH02142187A JP29567488A JP29567488A JPH02142187A JP H02142187 A JPH02142187 A JP H02142187A JP 29567488 A JP29567488 A JP 29567488A JP 29567488 A JP29567488 A JP 29567488A JP H02142187 A JPH02142187 A JP H02142187A
- Authority
- JP
- Japan
- Prior art keywords
- inp
- gate
- semiconductor
- misfet
- field effect
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 239000012212 insulator Substances 0.000 claims abstract description 10
- 239000013078 crystal Substances 0.000 claims abstract description 8
- 150000001875 compounds Chemical class 0.000 claims description 13
- 229910052738 indium Inorganic materials 0.000 claims description 4
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 4
- 239000000470 constituent Substances 0.000 claims description 3
- 239000000758 substrate Substances 0.000 abstract description 16
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 abstract description 4
- 238000000151 deposition Methods 0.000 abstract description 3
- 238000000137 annealing Methods 0.000 abstract description 2
- 238000005530 etching Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 238000002955 isolation Methods 0.000 abstract description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 239000000956 alloy Substances 0.000 abstract 1
- 229910045601 alloy Inorganic materials 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 17
- 239000007789 gas Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 239000005360 phosphosilicate glass Substances 0.000 description 5
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- BLBNEWYCYZMDEK-UHFFFAOYSA-N $l^{1}-indiganyloxyindium Chemical compound [In]O[In] BLBNEWYCYZMDEK-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 239000010407 anodic oxide Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔発明の目的〕
（産業上の利用分野）
本発明は化合物半導体を用いた絶縁ゲート型電界効果ト
ランジスタに関し、特にその構成元素に少なくともイン
ジウムを含む化合物半導体、とりわけＩｎＰを用いた高
周波、高出力動作に好適な絶縁ゲート型電界効果１ヘラ
ンジスタ（以下ＭＩＳＦＥＴと略す）に関する。Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to an insulated gate field effect transistor using a compound semiconductor, and particularly to a compound semiconductor containing at least indium as a constituent element, particularly InP. The present invention relates to an insulated gate field effect transistor (hereinafter abbreviated as MISFET) suitable for high frequency, high output operation.
（従来の技術）
ＩｎＰは、現在マイクロ波半導体素子用材料の主流を占
めているＧａＡｓに比べても、電子飽和速度が大きく、
また熱伝導率が大きい等の特性を有しているため、 Ｇ
ａＡｓを上回る高周波動作が期待される半導体素子用材
料として注目を集めている。(Prior art) InP has a higher electron saturation speed than GaAs, which is currently the mainstream material for microwave semiconductor devices.
Also, because it has characteristics such as high thermal conductivity, G
It is attracting attention as a material for semiconductor devices, which is expected to have higher frequency operation than aAs.
ＩｎＰでは、ＧａＡｓのように逆方向リーク電流の小さ
い良好なショットキ接合を形成することが難しいため、
金属／絶縁体／半導体構造（以下ＭＩＳと略す）をゲー
トとするＭＩＳＦＩＥＴが中心に開発されてきた。With InP, it is difficult to form a good Schottky junction with low reverse leakage current as with GaAs.
MISFIETs having a metal/insulator/semiconductor structure (hereinafter abbreviated as MIS) as a gate have been mainly developed.
ＩｎＰ ＭＩＳＩ・”ＥＴを実用化するにあたっての最
も大きな問題点の一つは、ドレイン電流が時間と共に変
動する所謂電流ドリフトが生ずることであった。電流ド
リフトの〃ｘ囚については現在のところ不明な点も多い
が、絶Ｒｎ ／ ＩｎＰ （ＩＳ界面）に存在する界面
準位への電子の充放電により、動作チャンネルが時間と
共に変調を受けることが主な原因の一つと考えられる。One of the biggest problems in putting InP MISI・ET into practical use was the occurrence of so-called current drift, in which the drain current fluctuates over time.The problem with current drift is currently unknown. Although there are many points, one of the main causes is considered to be that the operating channel is modulated over time due to charging and discharging of electrons to the interface level existing at the absolute Rn/InP (IS interface).
従ってＩｓ界面の界面準位を極力低減させることが、電
流ドリフトを低減させるための必要条件となる。Therefore, reducing the interface state of the Is interface as much as possible is a necessary condition for reducing current drift.
従来、化合物半導体のＭＩＳＦ訂開発は半導体結晶の（
１００）面を用いてなされてきた６しかしながら、従来
のように（１００）面に形成されたＩＳ界面では。Conventionally, MISF revision development of compound semiconductors has been carried out using semiconductor crystal (
However, the IS interface formed on the (100) plane as in the past.
種々の絶縁膜形成方法１例えば熱酸化法、陽極酸化法、
化学的気相堆積法（ＣＶＤ）法、光ＣＶＤ法などにより
１例えば、Ｉｎ２Ｏ，膜、陽極酸化膜、Ｓｉｎ。Various insulating film forming methods 1 For example, thermal oxidation method, anodic oxidation method,
For example, an In2O film, an anodic oxide film, a Sin film, etc. by a chemical vapor deposition (CVD) method, a photo-CVD method, or the like.
膜、 Ｓｉ３Ｎ４膜など種々の絶縁膜を形成することが
試みられてきたにもかかわらず、未だに、界面準位密度
を満足なレベルにまで低下させ得るＭＩＳ界面は見いだ
されていない、このため、 ＩｎＰ等の化合物半導体で
は、電流ドリフトが生じないＭＩＳＦＥＴも実用化され
ていないのが実情であった゛。Although attempts have been made to form various insulating films such as InP film and Si3N4 film, no MIS interface has been found that can reduce the interface state density to a satisfactory level. The reality is that MISFETs that do not cause current drift have not been put into practical use with compound semiconductors such as the above.
（発明が解決しようとする課題）
以上述べたように、ＩｎＰのような化合物半導体では２
従来のように（１００）面を用いた場合、界面準位密度
の小さな、良好な特性を有するＩｓ界面を形成し得る絶
縁膜、及びその堆積方法が見出せていなかった。このた
め、電流ドリフトを生じない化合物半導体の阿ｌ５ＦＩ
ＥＴ 、例えば、 ＩｎＰ ＭＩＳＦＥＴは実用化され
ていなかった。(Problem to be solved by the invention) As stated above, in compound semiconductors such as InP, 2
When a (100) plane is used as in the past, an insulating film capable of forming an Is interface with a small interface state density and good characteristics, and a method for depositing the same, have not been found. Therefore, Al5FI, a compound semiconductor that does not cause current drift,
ET, for example, InP MISFET, had not been put into practical use.
本発明は、上記問題点を解決すべくなされたもので、化
合物半導体を用いた電流ドリフトを生じないＭＩＳＦＥ
Ｔに関し、特にインジウム（Ｉｎ）を少なくともその構
成元素として含む化合物半導体、とりわけＩｎＰを用い
た高周波、高出力動作に好適なＭＩＳＦＩＥＴを堤供す
ることを目的とする。The present invention has been made to solve the above problems, and is a MISFE that uses a compound semiconductor and does not cause current drift.
Regarding T, an object of the present invention is to provide a MISFIET suitable for high-frequency, high-output operation using a compound semiconductor, especially InP, containing at least indium (In) as a constituent element.
（課題を解決するための手段）
上記目的を達成するために本発明では、化合物半導体結
晶層を動作層とするＭＩＳＦＥＴにおいて、ゲート絶縁
体に接し絶縁体／半導体界面を形成する半導体結晶の面
方位を（１１１） とするものであり、トランジスタの
動作層を形成する化合物半導体が、インジウム（Ｉｎ）
を少なくともその構造元素として含むこと、あるいは、
ゲート絶縁体に接する半導体層が、ＩｎＰであることを
実施態様としている。(Means for Solving the Problems) In order to achieve the above object, in the present invention, in a MISFET having a compound semiconductor crystal layer as an active layer, the plane orientation of the semiconductor crystal that is in contact with the gate insulator and forms the insulator/semiconductor interface is (111), and the compound semiconductor forming the active layer of the transistor is indium (In).
contains as at least its structural element, or
In this embodiment, the semiconductor layer in contact with the gate insulator is made of InP.
尚、動作層を形成する半導体層と、ゲート絶縁体に接す
る半導体層は同一の半導体で形成されていても、あるい
は異なる半導体で形成されていてもよい。Note that the semiconductor layer forming the active layer and the semiconductor layer in contact with the gate insulator may be formed of the same semiconductor, or may be formed of different semiconductors.
（作 用）
本発明は、種々実験、検討を重ねた結果、ｍ＋）面など
の（１１１）面に形成したＩＳ界面のほうが、（１１１
）面に形成したＩＳ界面よりも界面準位密度が低減され
るという事実を見出してなされたものであり、界面準位
に付随したｌＭＩＳＦＥＴのドレイン電流ドリフトを抑
えることが出来る。(Function) As a result of various experiments and studies, the present invention has found that IS interfaces formed on (111) planes such as m+) planes are better than (111) planes.
This was done based on the discovery of the fact that the interface state density is lower than that of an IS interface formed on the ) surface, and it is possible to suppress the drain current drift of the IMISFET accompanying the interface state.
（実施例）
以下、本発明の一つの実施例を図面を参照して説明する
。(Example) Hereinafter, one example of the present invention will be described with reference to the drawings.
第１図は、この発明に係るデイブレジョン型ＩｎＰ Ｍ
ＩＳＦＥＴの概略の断面図である。この第１図において
、１は半絶縁性（ＩＩＩ）ＩｎＰ基板、２はｎ型ＩｎＰ
動作層、３は燐珪酸ガラス（ｐｓｃ）ゲート絶縁膜。FIG. 1 shows a day-length InP M according to the present invention.
FIG. 2 is a schematic cross-sectional view of an ISFET. In FIG. 1, 1 is a semi-insulating (III) InP substrate, 2 is an n-type InP substrate, and 2 is an n-type InP substrate.
The active layer 3 is a phosphosilicate glass (PSC) gate insulating film.
４Ｓ、 ４Ｄはｎ型動作層にオーム性接触となるＡｕＧ
ｅがらなり、それぞれソース電極、トレインｉｌｌであ
り、４ＧはＡ１のゲート電極である。4S and 4D are AuG that makes ohmic contact with the n-type active layer.
4G is the gate electrode of A1, and 4G is the gate electrode of A1.
以下に上記実施例に示したＩｎＰ ＭＩＳＦＥＴの製造
方法の一例を工程順に第２図〜第４図によって説明する
。先ず、第２図に示すように（１１１）面方位を有する
半絶縁性基板ＩｎＰ（１）にＳｉイオンを加速エネルギ
７０ｋｃＶでドースｊｉ ４ Ｘ ＬＯ”／ｃｄ注入し
た後、ホスフィン（Ｐｌ＋、）を約５ Ｔｏｒｒ含んだ
Ａｒ雰囲気中で１３０℃１０分間のアニールを行なって
注入Ｓｊを活性化させ、キャリア濃度が概略２．５ Ｘ
（０１７／ｄのｎ型動作層２を形成する。続いて、素
子分離のためのメサエッチングを行なった後（図示せず
）、後に説明する第５図に示すように、プラズマ発生部
と、膜を堆積する反応部を空間的に分離し構成されたイ
ンダイレクトプラズマｃｖｎ装置を用い、基板温度３０
０℃にてＰＳＧ膜３を６０ｎｍ堆積する。次に、第４図
に示すように、通常のＰＥＰ法、蒸着法、およびリフト
オフ法によって、ＡｕＧｅ−Ｎｉ を形成し合金化熱処
理を施して、ソースｊ１ｉ極、ドレインｆｆ１ｔｉ４ｓ
、 ４Ｄを形成する。続いて、ゲート形成用ＰＥＰ工程
、蒸着。An example of a method for manufacturing the InP MISFET shown in the above embodiment will be explained below in the order of steps with reference to FIGS. 2 to 4. First, as shown in FIG. 2, Si ions are implanted into a semi-insulating substrate InP (1) having a (111) plane orientation at a dose of ji 4 The implantation Sj was activated by annealing at 130°C for 10 minutes in an Ar atmosphere containing about 5 Torr, and the carrier concentration was approximately 2.5X.
(An n-type active layer 2 of 017/d is formed. Subsequently, after performing mesa etching for element isolation (not shown), as shown in FIG. Using an indirect plasma CVN system in which the reaction section for film deposition is spatially separated, the substrate temperature is 30°C.
A 60 nm thick PSG film 3 is deposited at 0°C. Next, as shown in FIG. 4, AuGe-Ni is formed by the usual PEP method, vapor deposition method, and lift-off method, and alloying heat treatment is performed to form the source j1i electrode and the drain ff1ti4s.
, forming 4D. Next, PEP process for gate formation and vapor deposition.
リフトオフ工程を経てＡｌでゲート電極６が形成され、
第１図に示すようなデイブレジョン型ＩｎＰＭＩＳＦＥ
Ｔが完成する。A gate electrode 6 is formed of Al through a lift-off process,
Daybreak type InPMISFE as shown in Figure 1
T is completed.
第５図において、５１はマイクロ波励起のプラズマ生成
器、５２は反応容器、５３は第２図にて説明した工程を
経た（１１０）ＩｎＰ基板、５４はこれを保持するため
のサセプタであり、このサセプタ中にはヒータが埋め込
まれており、前記基板を所望の温度に加熱できるように
なっている。前記プラズマ生成器にはガス導入管が、窒
素用５５と酸素用５Ｇの二系統設けられており、切り替
えコック５７により切り替え可能となっている。生成さ
れたプラズマは。In FIG. 5, 51 is a microwave-excited plasma generator, 52 is a reaction vessel, 53 is an InP substrate (110) that has undergone the process explained in FIG. 2, and 54 is a susceptor for holding this. A heater is embedded in this susceptor so that the substrate can be heated to a desired temperature. The plasma generator is provided with two gas introduction pipes, one for nitrogen 55 and one for oxygen 5G, which can be switched by a switching cock 57. The generated plasma.
導入管５８を通じて反応容器５２に導入される。この反
応容器５２にはシラン（Ｓｉｌ１４）及びホスフィン（
ＰＨ３）等の原料ガスを導入するための２本の導入管５
９゜６０が設けられている。さらに、反応容Ｉ＠５２の
下方にはガス排出口６１が設けられ、その先は排気ポン
プ（図示せず）に連なり、反応容器５２中を１Ｏ−３Ｔ
ｏｒｒ程度の減圧状態にすることが可能な構成になって
いる。It is introduced into the reaction vessel 52 through the introduction pipe 58. This reaction vessel 52 contains silane (Sil14) and phosphine (
Two introduction pipes 5 for introducing raw material gas such as PH3)
9°60 is provided. Further, a gas exhaust port 61 is provided below the reaction volume I@52, and the end thereof is connected to an exhaust pump (not shown), and the gas discharge port 61 is connected to an exhaust pump (not shown), and the gas discharge port 61 is connected to the exhaust pump (not shown), and the gas discharge port 61 is connected to the exhaust pump (not shown).
The structure is such that it is possible to create a reduced pressure state of about orr.
尚、上記実施例ではプレーナ型のＭＩＳＦＥＴについて
説明したが、本発明のＭＩＳＦＥＴは何らこれらに限定
されるものではなく、例えば、ゲート部がリセス構造を
とっていてもよいことは勿論である。また、上記実施例
では本発明のＭＩＳＦＥＴを製造する方法において、動
作層２を半絶縁性（１１１）ＩｎＰ基板にイオン注入法
によって形成する場合を説明したが。Incidentally, in the above embodiment, a planar type MISFET has been described, but the MISFET of the present invention is not limited thereto, and it goes without saying that, for example, the gate portion may have a recessed structure. Further, in the above embodiment, in the method of manufacturing a MISFET of the present invention, the case where the active layer 2 is formed on a semi-insulating (111) InP substrate by ion implantation has been described.
例えば、（１１１）面基板を用い、分子線結晶成長（Ｍ
ＢＥ）法などのエピタキシャル成長技術を使って形成す
ることも出来る。For example, using a (111) plane substrate, molecular beam crystal growth (M
It can also be formed using an epitaxial growth technique such as BE) method.
尚、上記実施例に於ては、（１１１）面の場合のみにつ
いて説明したが（１１１，）面に属する面であれば他の
面方位、例えば（１１１）面等であっても良い。In the above embodiment, only the case of the (111) plane has been described, but other plane orientations may be used as long as the plane belongs to the (111,) plane, for example, the (111) plane.
また、 （１１１）面から数度のオフアングルを有す
る面であっても本発明の効果は変らない。Further, even if the surface has an off angle of several degrees from the (111) plane, the effects of the present invention will not change.
上記実施例で説明したのと同様の方法で、キャリア濃度
５ Ｘ １０”／ｃＪのｎ型（１１１）基板に約６０ｎ
ａ＋のＰＳＧ膜を堆積してＭＩＳダイオードを形成し、
周波数ＩＭＩＩｚにおいて容量−電圧（Ｃ−Ｖ）特性を
ｉｌｌ’ｌ定したところ（バイアスは、 ＋１０−４０
−＋−ＩＱ−＋ ０−＋＋ｔｏｖと掃引した）、第６図
実線に示すごとく、ヒステリシスがほとんどなく、８祉
の電圧に対する変化も急峻な、良好な結果が得られた。Approximately 60 nm was applied to an n-type (111) substrate with a carrier concentration of 5
Deposit an a+ PSG film to form a MIS diode,
Ill'l determined the capacitance-voltage (C-V) characteristics at frequency IMIIz (bias is +10-40
-+-IQ-+ 0-++tov), as shown by the solid line in Figure 6, good results were obtained with almost no hysteresis and a steep change in voltage.
本発明の効果を明確にするために、同一のキャリア濃度
を有する（１００） ｎ型基板に、同一の方法で形成し
たＭＩＳダイオードのＣ−■特性も図中点線で併せて示
しである。In order to clarify the effects of the present invention, the C-■ characteristics of MIS diodes formed by the same method on (100) n-type substrates having the same carrier concentration are also shown by dotted lines in the figure.
（１，１＋、 ）面に形成したＭＩＳ界面は、（１００
）面に形成したものに比較し、容量（Ｃ）の変化が急峻
で、界面準位が低下していることが示されている。The MIS interface formed on the (1,1+, ) plane is (100
) It is shown that the change in capacitance (C) is steeper than that formed on the surface, and the interface state is lowered.
」二連の方法で製造された本発明のＩｎＰ ＭＩＳＦＥ
Ｔのトレイン電流ドリフトを測定したところ、第７図に
実線で示すごとく、ドリフト量は１ｍＡ以内と極めて小
さなものであった。尚、第７図はソース、ドレイン間に
５ｖの電圧を印加し、ゲートバイアス電圧を時刻（ｔ）
＝ＯでＯｖから一２ｖまでステップ状に変化させた場合
のドレイン電流の時間変化を示したものである。本発明
の効果を明確にするために、同一形状のにｌ５ＦＥＴを
（１００）基板上に同一方法で形成して同様の８１ｑ定
を行なった結果を図中破線で合せて示しである。ドリフ
ト特性が大幅に向上したことが分かる。” InP MISFE of the present invention manufactured by a duplicate method
When the train current drift of T was measured, the amount of drift was extremely small, within 1 mA, as shown by the solid line in FIG. In addition, in Fig. 7, a voltage of 5V is applied between the source and drain, and the gate bias voltage is changed at time (t).
It shows the time change of the drain current when it is changed stepwise from Ov to -2V at =O. In order to clarify the effects of the present invention, the results of similar 81q determinations made by forming 15FETs of the same shape on a (100) substrate by the same method are also shown in the figure with broken lines. It can be seen that the drift characteristics have been significantly improved.
以上は半導体動作層がＩｎＰの場合について説明したが
、例えばＩｎＧａＡｓなどのＩｎを含む混晶半導体を動
作層とした場合にも適用できる。また、第８図に示すご
と＜ 、 ＩｎＧａＡｓを動作層とし、ＩｎＰをその上
に積層した構造のＦＥＴにも適用できることは」二連の
説明から明らかである。上記第８図に示したような構造
において、ゲート電極下のＩｎＰは不純物がドープされ
ていてもいなくても本発明の効果に影響はない。なお、
第８図において、８１は（１１１）半絶縁性ＩｎＰ基板
、８２はｎ型Ｉ ｎ Ｇ ａ Ａ ｓ動作層、８２ａは
ＩｎＰ層、８３はＰＳＧゲート絶縁層、８４Ｇはグート
′１１！極、８４Ｓ、８４Ｄはそれぞれソース電極、ド
レイン電極である。Although the above description has been made for the case where the semiconductor active layer is InP, the present invention can also be applied to a case where the active layer is a mixed crystal semiconductor containing In, such as InGaAs. Furthermore, it is clear from the two series of explanations that the present invention can also be applied to an FET having a structure in which InGaAs is used as the active layer and InP is laminated thereon, as shown in FIG. In the structure shown in FIG. 8, whether or not the InP under the gate electrode is doped with impurities does not affect the effects of the present invention. In addition,
In FIG. 8, 81 is a (111) semi-insulating InP substrate, 82 is an n-type InGaAs active layer, 82a is an InP layer, 83 is a PSG gate insulating layer, and 84G is a GUT'11! The poles 84S and 84D are a source electrode and a drain electrode, respectively.
以上述べたように、本発明によれば、絶縁ゲート部ＭＩ
Ｓ界面の界面準位密度を大幅に減少させ、ドレイン電流
の時間ドリフト量を、従来のＭＩＳＦＥＴに比べて大幅
に低減させ得る化合物半導体ＭＩＳＦＥＴを提供するこ
とが可能となった。As described above, according to the present invention, the insulated gate portion MI
It has become possible to provide a compound semiconductor MISFET that can significantly reduce the interface state density at the S interface and significantly reduce the amount of time drift of drain current compared to conventional MISFETs.
第１図は、本発明に係るＩｎＰ ＭＩＳＦＥＴを示す概
略の断面図、第２図及至第４図は本発明に係るＩｎＰＭ
ＩＳＦＥＴの製造方法の一例を工程順に説明する断面図
、第５図はインダイレクトプラズマＣＶＤ装置を示す図
、第６図は本発明のゲートＭＩＳ構造と同一の構造を有
するＭＩＳダイオードのＣ−Ｖ特性を、従来のＭＩＳダ
イオードのＣ−ｖ特性と比較して示す線図、第７図は本
発明の実施例につきＩｎＰ ＭＩＳＦＥＴのドレイン電
流の時間変化を、従来のＭＩＳＦＥＴと比較して示す線
図、第８図は本発明の他の実施例を示す断面図である。
１、 ８１＝４ｎＰ基板
２．８２・・・動作層
３．８３・・・ゲート絶縁膜
４Ｓ、８４Ｓ・・・ソース電極
４Ｄ、８４Ｄ・・・ドレイン電極
４Ｇ、 ８４Ｇ・・・ゲート電極
８２ａ・・・・・・・・・ＩｎＰ層
代理人 弁理士 大 胡 典 夫
Ｓ
＋Ｄ
コ
図
電圧−
第
（ｖ）
（ｒｒＬＡン
ｆ３０ト
０Ｏ
ＦＲＰ：ｉ（ｔ＞
１０００ （ＳｅＣ）FIG. 1 is a schematic cross-sectional view showing an InP MISFET according to the present invention, and FIGS.
A cross-sectional view explaining an example of an ISFET manufacturing method step by step, FIG. 5 is a diagram showing an indirect plasma CVD apparatus, and FIG. 6 is a CV characteristic of a MIS diode having the same structure as the gate MIS structure of the present invention. FIG. 7 is a diagram showing the time change of the drain current of an InP MISFET according to an embodiment of the present invention in comparison with that of a conventional MISFET. FIG. 8 is a sectional view showing another embodiment of the present invention. 1, 81=4nP substrate 2.82...Active layer 3.83...Gate insulating film 4S, 84S...Source electrode 4D, 84D...Drain electrode 4G, 84G...Gate electrode 82a...・・・・・・InP layer agent Patent attorney Norio Ogo S +D Figure voltage - No. (v) (rrLAnf30to0O FRP:i(t>1000 (SeC)
Claims (3)
ト型電界効果トランジスタにおいて、ゲート絶縁体に接
し絶縁体／半導体界面を形成する半導体結晶の面方位が
（１１１）であることを特徴とする絶縁ゲート型電界効
果トランジスタ。(1) An insulated gate field effect transistor whose active layer is a compound semiconductor crystal layer is characterized in that the plane orientation of the semiconductor crystal in contact with the gate insulator and forming an insulator/semiconductor interface is (111). Insulated gate field effect transistor.
構成元素にインジウムを含むことを特徴とする請求項１
に記載の絶縁ゲート型電界効果トランジスタ。(2) Claim 1, wherein the compound semiconductor forming the active layer contains indium at least as a constituent element.
The insulated gate field effect transistor described in .
とを特徴とする請求項１、または請求項２に記載の絶縁
ゲート型電界効果トランジスタ。(3) The insulated gate field effect transistor according to claim 1 or 2, wherein the semiconductor layer in contact with the gate insulator is made of InP.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29567488A JPH02142187A (en) | 1988-11-22 | 1988-11-22 | Insulated gate type field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP29567488A JPH02142187A (en) | 1988-11-22 | 1988-11-22 | Insulated gate type field effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02142187A true JPH02142187A (en) | 1990-05-31 |
Family
ID=17823720
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP29567488A Pending JPH02142187A (en) | 1988-11-22 | 1988-11-22 | Insulated gate type field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02142187A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2654984C1 (en) * | 2017-07-05 | 2018-05-23 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Чеченский государственный университет" | Method for manufacturing doped regions |
-
1988
- 1988-11-22 JP JP29567488A patent/JPH02142187A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2654984C1 (en) * | 2017-07-05 | 2018-05-23 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Чеченский государственный университет" | Method for manufacturing doped regions |
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