JPH04352330A - Manufacture of mis semiconductor device - Google Patents

Manufacture of mis semiconductor device

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Publication number
JPH04352330A
JPH04352330A JP12631191A JP12631191A JPH04352330A JP H04352330 A JPH04352330 A JP H04352330A JP 12631191 A JP12631191 A JP 12631191A JP 12631191 A JP12631191 A JP 12631191A JP H04352330 A JPH04352330 A JP H04352330A
Authority
JP
Japan
Prior art keywords
gaas substrate
gaas
gas
substrate
high temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12631191A
Other languages
Japanese (ja)
Inventor
Akiyoshi Tamura
彰良 田村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP12631191A priority Critical patent/JPH04352330A/en
Publication of JPH04352330A publication Critical patent/JPH04352330A/en
Pending legal-status Critical Current

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

PURPOSE:To make the surface of a GaAs substrate nitride and to form efficiently a GaN film by a method wherein As atoms are made to evaporate from the surface of the GaAs substrate to make the surface rich in Ga by annealing first the GaAs substrate surface at a high temperature for a short time in an H2 gas atmosphere and thereafter, the GaAs substrate surface is annealed in an NH3 gas atmosphere. CONSTITUTION:A GaAs substrate 1 is mounted on a carbon boat 3 provide with a thermocouple monitor 2 in an infrared ray lamp annealing device, with the substrate surface up. The substrate 1 surface is annealed at a high temperature for a short time in an H2 gas atmosphere. Whereby As atoms are made to evaporate from the surface of the GaAs substrate and the surface becomes rich in Ga. Moreover, the H2 gas is changed to NH3 gas keeping the substrate 1 intact and the substrate 1 surface is annealed at a high temperature for a short time. Thereby, GaAs substrate surface is efficiently nitrided and a GaN film 9 is formed on the surface in a thickness of about 50nm.

Description

【発明の詳細な説明】[Detailed description of the invention]

【0001】0001

【産業上の利用分野】本発明は化合物半導体GaAs(
ひ化ガリウム)を用いた金属−絶縁膜−半導体(MIS
)型素子の製造方法に関するものである。
[Industrial Application Field] The present invention relates to compound semiconductor GaAs (
Metal-insulating film-semiconductor (MIS) using gallium arsenide
) type element manufacturing method.

【0002】0002

【従来の技術】化合物半導体GaAsを用いたMIS型
素子として、現在までに様々なものが報告されている。 絶縁膜としてSiO2 、SiN、AlN、GaAsの
プラズマ酸化膜、またAlGaAsなどの半導体層が報
告されている。
2. Description of the Related Art Various MIS type devices using compound semiconductor GaAs have been reported to date. As insulating films, plasma oxide films of SiO2, SiN, AlN, GaAs, and semiconductor layers such as AlGaAs have been reported.

【0003】0003

【発明が解決しようとする課題】しかし、こうした従来
の絶縁膜を用いたMIS型素子では界面準位密度が10
12cm−2eV−1以上と多く、反転層の形成も難し
かった。これはGaAs表面にはGa格子位置のAs原
子(AsGa)によるドナーとAs格子位置のGa原子
(GaAs)によるアクセプターなどの多数の表面準位
が存在するためである。一方、AlGaAsなどの半導
体を用いたMIS型素子では、界面準位密度はSiのM
OS素子並みに少ないが、エネルギーギャップが最大で
約2eVしかなく、バイアス電圧が大きくなるとリーク
電流が増大し、バイアスの余裕度が少なかった。
[Problem to be Solved by the Invention] However, in MIS type devices using such conventional insulating films, the interface state density is 10.
It was often 12 cm-2 eV-1 or more, and it was difficult to form an inversion layer. This is because a large number of surface levels exist on the GaAs surface, such as donors due to As atoms (AsGa) at Ga lattice positions and acceptors due to Ga atoms (GaAs) at As lattice positions. On the other hand, in MIS type devices using semiconductors such as AlGaAs, the interface state density is
Although it is as small as an OS element, the maximum energy gap is only about 2 eV, and as the bias voltage increases, the leakage current increases and the bias margin is small.

【0004】0004

【課題を解決するための手段】請求項1に記載のMIS
型半導体装置の製造方法は、水素ガス雰囲気中でGaA
s基板の少なくとも一主面を高温、短時間アニールした
後、アンモニアガス雰囲気中で前記GaAs基板の一主
面を高温で短時間アニールする工程を含むことを特徴と
する。
[Means for solving the problem] MIS according to claim 1
The method for manufacturing a type semiconductor device is to manufacture a GaA type semiconductor device in a hydrogen gas atmosphere.
The method is characterized by including a step of annealing at least one main surface of the GaAs substrate at high temperature for a short time in an ammonia gas atmosphere, and then annealing one main surface of the GaAs substrate at high temperature for a short time in an ammonia gas atmosphere.

【0005】請求項2に記載のMIS型半導体装置の製
造方法は、酸素を含むガスを用いてプラズマを発生させ
、前記プラズマガス中でGaAs基板の少なくとも一主
面をさらして処理した後、前記GaAs基板の一主面を
アンモニアガス雰囲気中で高温で短時間アニールする工
程を含むことを特徴とする。
The method for manufacturing an MIS type semiconductor device according to the second aspect includes generating plasma using a gas containing oxygen, exposing at least one principal surface of a GaAs substrate in the plasma gas, and then processing the GaAs substrate. It is characterized by including a step of annealing one main surface of the GaAs substrate at high temperature in an ammonia gas atmosphere for a short time.

【0006】請求項4に記載のMIS型半導体装置の製
造方法は、三フッ化窒素を含むガスを用いてプラズマを
発生させ、前記プラズマガス中でGaAs基板の少なく
とも一主面をさらして処理する工程を含むことを特徴と
する。
[0006] In the method for manufacturing an MIS type semiconductor device according to claim 4, plasma is generated using a gas containing nitrogen trifluoride, and at least one main surface of a GaAs substrate is exposed and processed in the plasma gas. It is characterized by including a process.

【0007】[0007]

【作用】請求項1に記載の第1の方法では、最初の水素
ガス中の高温で短時間のアニールによりGaAs基板表
面のAs原子を蒸発させて表面をGaリッチにし、次の
アンモニアガス中の高温で短時間のアニールにより効率
良く窒化ガリウム(GaN)層が形成される。
[Operation] In the first method as claimed in claim 1, the As atoms on the surface of the GaAs substrate are evaporated by first short-time annealing at high temperature in hydrogen gas to make the surface Ga-rich, and then the surface is made Ga-rich. A gallium nitride (GaN) layer is efficiently formed by annealing at a high temperature for a short time.

【0008】請求項2に記載の第2の方法では、最初の
酸素を含むガスプラズマ処理により、GaAs表面に酸
化ガリウム(Ga2 O3 )層を形成し、次のアンニ
モアガス中の高温で短時間のアニールにより酸化ガリウ
ム層を効率良く窒化して窒化ガリウム(GaN)層が形
成される。
In the second method described in claim 2, a gallium oxide (Ga2 O3) layer is formed on the GaAs surface by a first oxygen-containing gas plasma treatment, and then a short time annealing at a high temperature in annimore gas is performed. The gallium oxide layer is efficiently nitrided to form a gallium nitride (GaN) layer.

【0009】請求項4に記載の第3の方法では、GaA
s基板表面の三フッ化窒素(NF3)ガスのプラズマ処
理によりGaAsをフッ化および窒化してGaFN膜が
形成される。
In the third method according to claim 4, GaA
A GaFN film is formed by fluoridating and nitriding GaAs by plasma treatment of nitrogen trifluoride (NF3) gas on the surface of the s-substrate.

【0010】第1および第2の方法で形成したGaNは
エネルギーギャップが約 3.4eVと大きく絶縁膜と
して十分の役目を果たす。また第3の方法で形成したG
aFN膜は同様にエネルギーギャップが 3.4〜 9
.6eVの間で同様に絶縁膜として十分の役目を果たす
。また、これらの絶縁膜とGaAsの界面はGaAsの
内部に形成されるためGaAs表面の影響を受けず、界
面準位密度はたいへん少なく良好なMIS型素子を得る
ことができる。
GaN formed by the first and second methods has a large energy gap of approximately 3.4 eV, and thus plays a sufficient role as an insulating film. Also, G formed by the third method
Similarly, the aFN film has an energy gap of 3.4 to 9.
.. Similarly, the film sufficiently functions as an insulating film between 6 eV and 6 eV. Furthermore, since the interface between these insulating films and GaAs is formed inside the GaAs, it is not affected by the GaAs surface, and the interface state density is very low, making it possible to obtain a good MIS type element.

【0011】[0011]

【実施例】以下、本発明のMIS型半導体装置の製造方
法を具体的な実施例に基づいて説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method of manufacturing an MIS type semiconductor device according to the present invention will be explained below based on specific examples.

【0012】図1の(a)〜(d)は請求項1に記載の
第1の製造方法の実施例を示す。図1の(a)に示すよ
うに、n型(キャリア濃度は約1×1017cm−3)
 GaAs基板1は、赤外線ランプアニール装置内の熱
電対モニター2を配したカーボンボート3の上に基板表
面を上にして配置され、H2 ガス雰囲気中で高温短時
間のアニールを受ける。高温とは約 700℃〜 85
0℃で、短時間とは約5秒〜10秒の範囲で、この実施
例では 750℃の雰囲気で5秒間アニールした。
FIGS. 1A to 1D show an embodiment of the first manufacturing method according to claim 1. As shown in Figure 1(a), n-type (carrier concentration is approximately 1 x 1017 cm-3)
A GaAs substrate 1 is placed with the substrate surface upward on a carbon boat 3 equipped with a thermocouple monitor 2 in an infrared lamp annealing apparatus, and is annealed at a high temperature and for a short time in an H2 gas atmosphere. High temperature is approximately 700℃ ~ 85
At 0°C, the short time is in the range of about 5 seconds to 10 seconds, and in this example, annealing was performed in an atmosphere of 750°C for 5 seconds.

【0013】これによりGaAs表面からAs原子が蒸
発し表面がGaリッチになる。この製造装置において4
は赤外線ランプ、5は反射板、6は石英ガラス製のサセ
プター、7,8はそれぞれガス導入口、流出口を示す。
As a result, As atoms evaporate from the GaAs surface, making the surface rich in Ga. In this manufacturing equipment, 4
5 is an infrared lamp, 5 is a reflector, 6 is a susceptor made of quartz glass, and 7 and 8 are a gas inlet and an outlet, respectively.

【0014】さらに、図1の(b)に示すように、Ga
As基板1はそのままの配置でNH3 ガスに切り替え
て高温短時間のアニールを受ける。高温とは約 700
℃〜 850℃で、短時間とは約5秒〜15秒の範囲で
、この実施例では 800℃、5秒間アニールした。
Furthermore, as shown in FIG. 1(b), Ga
The As substrate 1 is subjected to high-temperature, short-time annealing by switching to NH3 gas while maintaining its position. High temperature is about 700
C to 850 C, and the short time ranges from about 5 seconds to 15 seconds, and in this example, it was annealed at 800 C for 5 seconds.

【0015】これにより、GaAs基板表面は効率良く
窒化され表面にGaN層9が約50nm形成される。さ
らに、図1の(c)に示すように、GaAs基板の裏面
にAuGeを蒸着し450℃で30秒間、アルゴン(A
r)ガス中でシンターしてオーミック電極10を形成し
、次に図1の(d)に示すように、GaN層の所定の領
域にリフトオフ法を用いてアルミニウム(Al)金属か
らなるゲート電極11を形成してMISダイオードを完
成する。
As a result, the surface of the GaAs substrate is efficiently nitrided, and a GaN layer 9 of about 50 nm is formed on the surface. Furthermore, as shown in FIG. 1(c), AuGe was evaporated on the back surface of the GaAs substrate and argon (A
r) Form an ohmic electrode 10 by sintering in a gas, and then apply a lift-off method to a predetermined region of the GaN layer to form a gate electrode 11 made of aluminum (Al) metal, as shown in FIG. 1(d). is formed to complete the MIS diode.

【0016】図2の(a)〜(d)は請求項2に記載の
第2の製造方法の実施例を示す。図2の(a)に示すよ
うにn形GaAs基板1がプラズマCVD装置内のヒー
タ12の上に配置され、亜酸化窒素(N2 O)ガスを
チャンバー13に導入し、高周波電源14から周波数 
13.56MHz,高周波出力 100Wを電極14a
,14bの間に印加してプラズマを発生し、GaAs基
板表面をプラズマ処理する。プラズマ条件としては、N
2 Oガス流量20sccm、真空度40Pa、基板温
度 300℃、処理時間5分間を用いた。
FIGS. 2A to 2D show an embodiment of the second manufacturing method according to claim 2. As shown in FIG. 2(a), an n-type GaAs substrate 1 is placed on a heater 12 in a plasma CVD apparatus, nitrous oxide (N2O) gas is introduced into a chamber 13, and a high frequency power source 14 is used to
13.56MHz, high frequency output 100W to electrode 14a
, 14b to generate plasma and plasma-treat the surface of the GaAs substrate. The plasma conditions are N
2 O gas flow rate of 20 sccm, vacuum degree of 40 Pa, substrate temperature of 300° C., and processing time of 5 minutes were used.

【0017】これにより、GaAs表面に酸化ガリウム
(Ga2 O3 )を主成分とGaAs酸化膜15(厚
さ約40nm)が形成される。  同図において、16
、17はそれぞれガス導入口、排気口を示す。
As a result, a GaAs oxide film 15 (about 40 nm thick) containing gallium oxide (Ga2 O3) as a main component is formed on the GaAs surface. In the same figure, 16
, 17 indicate a gas inlet port and an exhaust port, respectively.

【0018】このGaAs酸化膜15は不安定であるが
、次に図2の(b)に示すように、GaAs基板1を赤
外線ランプアニール装置内に配置し、NH3 ガス雰囲
気中で高温短時間のアニールを受ける。高温とは約 7
00℃〜 850℃で、短時間とは約5秒〜15秒の範
囲で、この実施例では 800℃、5秒間アニールした
Although this GaAs oxide film 15 is unstable, next, as shown in FIG. 2(b), the GaAs substrate 1 is placed in an infrared lamp annealing device and subjected to high-temperature and short-time annealing in an NH3 gas atmosphere. undergo annealing. High temperature is about 7
The short time ranges from about 5 seconds to 15 seconds, and in this example, it was annealed at 800 degrees Celsius for 5 seconds.

【0019】これにより、GaAs表面の酸化膜15は
効率良く窒化され、より安定なGaN層9(厚さ約50
nm)に変換形成される。次に図2の(c)に示すよう
に、GaAs基板の裏面にAuGeを蒸着し 450℃
、30秒間、アルゴン(Ar)ガス中でシンターしてオ
ーミック電極10を形成する。さらに、図2の(d)に
示すように、GaN層の所定の領域にリフトオフ法を用
いてアルミニウム(Al)金属からなるゲート電極11
を形成してMISダイオードを完成する。
As a result, the oxide film 15 on the GaAs surface is efficiently nitrided, and a more stable GaN layer 9 (with a thickness of about 50 mm) is formed.
nm). Next, as shown in FIG. 2(c), AuGe was deposited on the back surface of the GaAs substrate at 450°C.
The ohmic electrode 10 is formed by sintering in argon (Ar) gas for 30 seconds. Furthermore, as shown in FIG. 2(d), a gate electrode 11 made of aluminum (Al) metal is applied to a predetermined region of the GaN layer using a lift-off method.
is formed to complete the MIS diode.

【0020】この実施例では酸素を含むガスとしてN2
 Oを使用したが、これはNO2 ガスやNOガスなど
を使用することもできる。図3の(a)〜(c)は請求
項4に記載の第3の製造方法の実施例を示す。
In this example, N2 is used as the oxygen-containing gas.
Although O was used, NO2 gas or NO gas may also be used. FIGS. 3A to 3C show an embodiment of the third manufacturing method according to claim 4.

【0021】図3の(a)に示すように、n形GaAs
基板1がプラズマCVD装置内のヒータ12の上に配置
され、三フッ化窒素(NF3 )ガスをチャンバー13
に導入し、高周波電源14から周波数 13.56MH
z,高周波出力 100Wを電極14a,14bの間に
印加してプラズマを発生し、GaAs基板表面をプラズ
マ処理する。プラズマ条件としては、NF3 ガス流量
20sccm、真空度40Pa、基板温度 300℃、
処理時間15分間を用いた。
As shown in FIG. 3(a), n-type GaAs
A substrate 1 is placed on a heater 12 in a plasma CVD apparatus, and nitrogen trifluoride (NF3) gas is injected into a chamber 13.
The frequency is 13.56MH from the high frequency power supply 14.
z, high-frequency power of 100 W is applied between the electrodes 14a and 14b to generate plasma, and the surface of the GaAs substrate is plasma-treated. The plasma conditions were: NF3 gas flow rate 20 sccm, vacuum degree 40 Pa, substrate temperature 300°C,
A treatment time of 15 minutes was used.

【0022】これにより、GaAs表面をフッ化および
窒化してGaFN膜18を厚さ約50nm形成した。次
に図3の(b)に示すように、GaAs基板の裏面にA
uGeを蒸着し 450℃、30秒間、アルゴン(Ar
)ガス中でシンターしてオーミック電極10を形成し、
さらに、図3の(c)に示すように、GaFN層の所定
の領域にリフトオフ法を用いてアルミニウム(Al)金
属からなるゲート電極11を形成してMISダイーオー
ドを完成する。
As a result, the GaAs surface was fluoridated and nitrided to form a GaFN film 18 with a thickness of about 50 nm. Next, as shown in FIG. 3(b), A
uGe was evaporated and heated at 450°C for 30 seconds using argon (Ar).
) sintering in a gas to form an ohmic electrode 10;
Furthermore, as shown in FIG. 3C, a gate electrode 11 made of aluminum (Al) metal is formed in a predetermined region of the GaFN layer using a lift-off method to complete the MIS diode.

【0023】図1〜図3に示した各製造方法で作成した
3種類のMISダイオードの高周波(1MHz)および
低周波(10Hz)でのC−V(容量−電圧)特性を図
4に示す。縦軸は絶縁膜容量Ciで規格化したものであ
る。
FIG. 4 shows the C-V (capacitance-voltage) characteristics at high frequency (1 MHz) and low frequency (10 Hz) of three types of MIS diodes manufactured by each of the manufacturing methods shown in FIGS. 1 to 3. The vertical axis is normalized by the insulating film capacitance Ci.

【0024】この図4より明らかなように、いずれのサ
ンプルもバイアス電圧は±5Vまで耐圧があり、反転層
の形成も認められ、蓄積領域から空乏領域への遷移も急
峻である。
As is clear from FIG. 4, all samples have a withstand voltage of up to ±5 V, the formation of an inversion layer is observed, and the transition from the accumulation region to the depletion region is steep.

【0025】図5は図4の3つのサンプルについて求め
た界面準位密度分布を示し、最低界面準位はどちらも1
010cm−2eV−1オーダーとたいへん低い値を示
しており、良好な界面特性が得られていることが分かる
FIG. 5 shows the interface state density distribution obtained for the three samples shown in FIG. 4, and the lowest interface state is 1 for both samples.
It shows a very low value of the order of 0.010 cm-2 eV-1, indicating that good interfacial properties are obtained.

【0026】上記の各実施例では基板1としてn型Ga
As基板について述べたが、p型GaAs基板について
も同様であることは言うまでもない。また、MIS型ダ
イオードについて説明したが、MIS型FETについて
も同様であることは言うまでもない。
In each of the above embodiments, the substrate 1 is made of n-type Ga.
Although the As substrate has been described, it goes without saying that the same applies to a p-type GaAs substrate. Moreover, although the MIS type diode has been described, it goes without saying that the same applies to the MIS type FET.

【0027】[0027]

【発明の効果】請求項1に記載の第1の製造方法によれ
ば、GaAs表面をまずH2 ガス雰囲気中で高温、短
時間アニールすることにより、GaAs表面からAs原
子を蒸発させ表面をGaリッチにし、その後NH3 ガ
ス雰囲気中でアニールすることによりGaAs表面を窒
化させGaN膜を効率良く形成することができる。
According to the first manufacturing method described in claim 1, the GaAs surface is first annealed at high temperature in an H2 gas atmosphere for a short time, thereby evaporating As atoms from the GaAs surface and making the surface rich in Ga. By subsequently annealing in an NH3 gas atmosphere, the GaAs surface can be nitrided and a GaN film can be efficiently formed.

【0028】請求項2に記載の第2の製造方法によれば
、GaAs表面を酸素(O2 )を含むガスのプラズマ
処理によりGaAs酸化膜を形成し、その後NH3 ガ
ス雰囲気中でアニールすることによりGaAs酸化膜を
安定なGaN膜に効率良く変換形成させることができる
According to the second manufacturing method described in claim 2, a GaAs oxide film is formed on the GaAs surface by plasma treatment with a gas containing oxygen (O2), and then annealing is performed in an NH3 gas atmosphere to form a GaAs oxide film. An oxide film can be efficiently converted into a stable GaN film.

【0029】請求項4に記載の第3の製造方法によれば
、GaAs表面をNF3 ガスのプラズマ処理をするこ
とにより、GaAs表面をフッ化および窒化してGaF
N膜を形成することができる。
According to the third manufacturing method described in claim 4, the GaAs surface is subjected to plasma treatment with NF3 gas, thereby fluoridating and nitriding the GaAs surface to form GaF.
An N film can be formed.

【0030】これらの製造方法で形成したGaNおよび
GaFN膜はエネルギーギャップが大きく、絶縁膜とし
ての役目を十分果たし、かつGaAsとの界面はGaA
s内部に形成されるため、GaAs表面の影響がなく界
面準位密度の少ないMIS型素子が作成できる。これら
のGaN、GaFN膜の厚さは、アニール条件、プラズ
マ条件などにより調節することができる。
The GaN and GaFN films formed by these manufacturing methods have a large energy gap and sufficiently serve as an insulating film, and the interface with GaAs has a large energy gap.
Since it is formed inside the GaAs surface, a MIS type element with a low density of interface states can be created without being affected by the GaAs surface. The thickness of these GaN and GaFN films can be adjusted by adjusting annealing conditions, plasma conditions, and the like.

【図面の簡単な説明】[Brief explanation of drawings]

【図1】本発明の第1の実施例のMIS型素子の製造方
法の工程図を示す。
FIG. 1 shows a process diagram of a method for manufacturing an MIS type element according to a first embodiment of the present invention.

【図2】本発明の第2の実施例のMIS型素子の製造方
法の工程図を示す。
FIG. 2 shows a process diagram of a method for manufacturing an MIS type element according to a second embodiment of the present invention.

【図3】本発明の第3の実施例のMIS型素子の製造方
法の工程図を示す。
FIG. 3 shows a process diagram of a method for manufacturing an MIS type element according to a third embodiment of the present invention.

【図4】本発明の第1〜第3の実施例の各MIS型素子
の容量−電圧特性図を示す。
FIG. 4 shows a capacitance-voltage characteristic diagram of each MIS type element of the first to third embodiments of the present invention.

【図5】本発明の第1〜第3の実施例の各MIS型素子
の界面準位密度分布特性図を示す。
FIG. 5 shows an interface state density distribution characteristic diagram of each MIS type device according to the first to third embodiments of the present invention.

【符号の説明】[Explanation of symbols]

1    n型GaAs基板 2    熱電対モニター 3    カーボンボート 4    赤外線ランプ 5    反射板 6    石英ガラス製のサセプター 7    ガス導入口 8    ガス流出口 9    GaN層 10    オーミック電極 11    ゲート電極 12    ヒータ 13    チャンバー 14    高周波電源 15    GaAs酸化膜 16    ガス導入口 17    ガス排気口 18    GaFN膜 1 N-type GaAs substrate 2 Thermocouple monitor 3 Carbon boat 4 Infrared lamp 5 Reflector plate 6. Quartz glass susceptor 7 Gas inlet 8 Gas outlet 9 GaN layer 10 Ohmic electrode 11 Gate electrode 12 Heater 13 Chamber 14 High frequency power supply 15 GaAs oxide film 16 Gas inlet 17 Gas exhaust port 18 GaFN film

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】  水素ガス雰囲気中でGaAs基板の少
なくとも一主面を高温、短時間アニールした後、アンモ
ニアガス雰囲気中で前記GaAs基板の一主面を高温で
短時間アニールする工程を含むことを特徴とするMIS
型半導体装置の製造方法。
1. The method includes the step of annealing at least one main surface of the GaAs substrate at high temperature for a short time in a hydrogen gas atmosphere, and then annealing one main surface of the GaAs substrate at high temperature for a short time in an ammonia gas atmosphere. Featured MIS
A method for manufacturing a type semiconductor device.
【請求項2】  酸素を含むガスを用いてプラズマを発
生させ、前記プラズマガス中でGaAs基板の少なくと
も一主面をさらして処理した後、前記GaAs基板の一
主面をアンモニアガス雰囲気中で高温で短時間アニール
する工程を含むことを特徴とするMIS型半導体装置の
製造方法。
2. After generating plasma using a gas containing oxygen and exposing at least one main surface of the GaAs substrate in the plasma gas, one main surface of the GaAs substrate is exposed to high temperature in an ammonia gas atmosphere. 1. A method for manufacturing an MIS type semiconductor device, comprising a step of annealing for a short time.
【請求項3】  酸素を含むガスがN2 O、NO2 
、NOのいずれかであることを特徴とする請求項2記載
のMIS型半導体装置の製造方法。
[Claim 3] The gas containing oxygen is N2O, NO2
, NO.
【請求項4】  三フッ化窒素を含むガスを用いてプラ
ズマを発生させ、前記プラズマガス中でGaAs基板の
少なくとも一主面をさらして処理する工程を含むことを
特徴とするMIS型半導体装置の製造方法。
4. A MIS type semiconductor device, comprising the step of generating plasma using a gas containing nitrogen trifluoride, and exposing and processing at least one principal surface of a GaAs substrate in the plasma gas. Production method.
JP12631191A 1991-05-30 1991-05-30 Manufacture of mis semiconductor device Pending JPH04352330A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12631191A JPH04352330A (en) 1991-05-30 1991-05-30 Manufacture of mis semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12631191A JPH04352330A (en) 1991-05-30 1991-05-30 Manufacture of mis semiconductor device

Publications (1)

Publication Number Publication Date
JPH04352330A true JPH04352330A (en) 1992-12-07

Family

ID=14932047

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12631191A Pending JPH04352330A (en) 1991-05-30 1991-05-30 Manufacture of mis semiconductor device

Country Status (1)

Country Link
JP (1) JPH04352330A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5616947A (en) * 1994-02-01 1997-04-01 Matsushita Electric Industrial Co., Ltd. Semiconductor device having an MIS structure
JP2016111295A (en) * 2014-12-10 2016-06-20 住友電気工業株式会社 Method for manufacturing semiconductor light-receiving element, and semiconductor light-receiving element

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5616947A (en) * 1994-02-01 1997-04-01 Matsushita Electric Industrial Co., Ltd. Semiconductor device having an MIS structure
JP2016111295A (en) * 2014-12-10 2016-06-20 住友電気工業株式会社 Method for manufacturing semiconductor light-receiving element, and semiconductor light-receiving element

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