JPH02140379U

JPH02140379U -

Info

Publication number: JPH02140379U
Application number: JP4702489U
Authority: JP
Priority date: 1989-04-21
Filing date: 1989-04-21
Publication date: 1990-11-22

Description

[Brief explanation of drawings]

第１図は本考案の一実施例のブロツク図、第２
図は第１図の実施例を用いてＢＴを行うＢＴ用基
板の平面図、第３図は従来の半導体集積回路の一
例を用いてＢＴを行うＢＴ用基板の平面図、第４
図は第３図のＢＴ用基板を用いてＢＴを行うＢＴ
装置の平面図、第５図は第４図のクロツク信号発
生器の出力の外部クロツク信号の波形図である。１，１ａ……半導体集積回路、２……入力端子
、３……選択信号入力端子、４……無安定マルチ
バイブレータ、５……選択回路、６……電源端子
、７……接地端子、８……内部回路、１０，１０
ａ……ＢＴ用基板、１１……外部クロツク信号入
力端子、１３……電源供給端子、１４……接地接
続端子、１５……恒温槽、１６……クロツク信号
発生器、１７……電源装置、１８……外部クロツ
ク信号入力端子、１９……電源供給端子、２０…
…接地接続端子、４１……抵抗素子、４２，４３
……インバータ、４４……コンデンサ、５１……
インバータ、５２，５３……トランスフアゲート
。 Fig. 1 is a block diagram of an embodiment of the present invention;
The figures are a plan view of a BT substrate that performs BT using the embodiment shown in FIG. 1, FIG. 3 is a plan view of a BT substrate that performs BT using an example of a conventional semiconductor integrated circuit, and FIG.
The figure shows a BT that performs BT using the BT substrate shown in Figure 3.
FIG. 5, a plan view of the apparatus, is a waveform diagram of the external clock signal output from the clock signal generator of FIG. 1, 1a... Semiconductor integrated circuit, 2... Input terminal, 3... Selection signal input terminal, 4... Astable multivibrator, 5... Selection circuit, 6... Power supply terminal, 7... Ground terminal, 8 ...internal circuit, 10,10
a... BT board, 11... External clock signal input terminal, 13... Power supply terminal, 14... Ground connection terminal, 15... Constant temperature chamber, 16... Clock signal generator, 17... Power supply device, 18...External clock signal input terminal, 19...Power supply terminal, 20...
...Ground connection terminal, 41...Resistance element, 42, 43
...Inverter, 44...Capacitor, 51...
Inverter, 52, 53...transfer gate.

Claims

[Scope of utility model registration request]

an input terminal into which a first clock signal can be input from the outside; an astable multivibrator that generates a second clock signal; and an input terminal that can input the first clock signal and the second clock signal in response to an external clock selection signal. A selection circuit for selecting one of the following.