JPH02137245A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a current, which crosses the interior of an epitaxial layer and is made to flow to isolation regions, from generating by a method wherein first and second dummy islands, in which depletion layers are respectively formed, are provided between first and second blocks. CONSTITUTION:A dummy island 13 and a dummy island 14 are connected to a power line VCC and isolation regions 15 are respectively connected to ground ing lines GND 22 and 23. Therefore, the region 15 and the island 13, and the region 15 and the island 14 are reverse-biased. As a result, depletion layers are respectively formed in the junction region between the region 15 and the island 13 and the junction region between the region 15 and the island 14. A current, which is made to flow from a first block 11 in the direction shown by (a), is inhibited by the depletion layer and a current, which is made to flow from 8 second block 2 to the direction shown by (b), is inhibited by the depletion layer. Therefore, as no current is made to flow to the regions 15, the voltage increase of the regions 15 is inhibited. Accordingly, the regions 15 can absorb completely a leakage current to flow in the adjacent blocks in a semiconductor substrate 2 as shown by (c) and (d).

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit that prevents signal interference.

(Example) Conventional technology Generally speaking, as a technology for preventing mutual interference between semiconductor chips, there is, for example, Japanese Patent Laid-Open No. 59-84542.

The semiconductor integrated circuit (51) described in this publication is
A plurality of circuit blocks are integrated, each handling different frequencies and signal levels.

As shown in FIG. 4, there is a P- type semiconductor substrate (52), and an N-type region (53), for example an epitaxial layer, is formed on this semiconductor substrate (52).

In this epitaxial layer (53), for example, transistors, diodes, capacitors, resistors, etc. are integrated, and the above-mentioned circuit block is configured.

Around this circuit block, there is a highly concentrated P1 type region (5
4), and this P" type region (54) is electrically connected to the ground line (57) through the opening (56) of the insulating film (55) provided on the N type region (53). was connected.

In FIG. 4, the leftmost N-type region (53) is the first circuit block (58), and the rightmost N-type region (53) is the first circuit block (58).
This is a circuit block (59). Therefore, the current flows as shown by the arrow, preventing mutual interference.

(c) Problems to be Solved by the Invention In the above-described configuration, the leakage current that causes mutual interference cannot be absorbed completely, and for example, the leakage current flows from the first circuit block (58) to the second circuit block (59). The problem of current infiltration and mutual interference still remained.

This is due to the P" type region (54) when the amount of leakage current increases.
This is because the amount of current flowing through the ground line increases, and as a result, the potential of the P-type region increases due to the impedance of the ground line.

If the number 1 rises, the leakage current cannot be completely absorbed, and for example, the second circuit block (52) cannot absorb the leakage current through the semiconductor substrate (52).
9).

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems, and includes a first dummy island (13) surrounding the first block (11) and the second block (12), respectively. Second dummy island (
14), and connect the first dummy island (13) and the second dummy island (14) to the power supply voltage (VCC).
And so. Furthermore, a separation region (14) is provided between the first dummy island (13) and the second dummy island (14).
5), and this isolation region (15) is connected to the ground voltage (G
The problem can be solved by setting ND).

(f) Operation The isolation region (15) is connected to GND-, and the first dummy island (13) and the second dummy island (14) are connected to V. By setting it to 0, the first dummy island (13
) and the second dummy island 14), a depletion layer is formed around them.

This depletion layer extends across the first dummy island (13) and the second dummy island (14) into the isolation region (
15) Suppressing the occurrence of leakage current that is absorbed.

Therefore, the amount of leakage absorbed by the separation region (15) is reduced by this amount, and an increase in potential can be prevented.

Therefore, the second block (12
) and the current that enters the first block (11) can be efficiently absorbed in the separation region <15).

(F) EXAMPLE The semiconductor integrated circuit (1) of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a first embodiment, and shows a region in a semiconductor IC in a plan view, and FIG. 2 is a diagram taken along A-A in FIG.
FIG.

First, from FIG. 2, there is a P-type semiconductor substrate (2), and on this semiconductor substrate (2) there is an N-type epitaxial layer (3) that has been epitaxially grown.

There is an N+ type buried layer (4>) formed between this epitaxial layer (3) and the semiconductor substrate (2), and around this buried layer (4), the epitaxial layer (3) is formed.
) There is a P" type isolation region <5) formed so as to reach the semiconductor substrate (2) from the surface. A plurality of island regions (6) are formed by this isolation region (5).

The island region (6) includes transistors, diodes, capacitors, resistors, etc. manufactured by a normal semiconductor manufacturing method, and the transistors, diodes, etc. are formed through the insulating film (7) on the surface of the epitaxial layer (3). , a wiring that is electrically connected to a capacitor, a resistor, and the like.

Here, the metal electrodes forming the wiring have a two-layer structure, and the wiring connecting the transistors, diodes, capacitors, resistors, etc. is substantially formed in the first layer, and only the areas where crosses occur are formed. is formed in the second layer. Further, as will be described later, the shield electrode is formed in the second layer.

This semiconductor integrated circuit (1) is formed with the above structure, and a plan view of this is shown in FIG.

First, the rectangular area surrounded by the broken line is the first block (1
1) and the second block (12).

In these blocks <11) and (12), semiconductor elements are integrated as described above, and wiring that electrically connects these semiconductor elements and diffusion regions formed when forming the semiconductor elements are included. Although it should be depicted, it has been omitted here.

Next, this first block (11) and second block (1
2), there are N-type dummy islands (13) and (14) provided between the two broken lines, and in detail, the first dummy island (11) is located in the first block (11). 13), but the second block (12) has a second
There are dummy islands (14).

Next, the first dummy island 13) and the second dummy
There is a P0 type isolation region (15) between the dummy island (14) and the dummy island (14).

Next, on the first dummy island (<13), a first power supply line (16) is electrically connected to the first dummy island (13) through the contact hole of the insulating film (7). ). Furthermore, on the second dummy island (14), there is a second 'wL source line (
17).

This first power line (16) and second power line (1
7) extends to a power supply pad (18) provided around the semiconductor chip (1). Power is supplied to each block through separate wiring extending from the pad.

Next, on the isolation region (15), there is a first ground line (19) electrically connected to the isolation region (<15) via a contact hole in the insulating film (7).

This ground line (19) extends to a first ground pad (20) provided around the semiconductor chip (1).

Next, the ground lines (22) and (23) extending from the second ground pad (21) provided around the semiconductor chip (1) are connected to the first block (11).
It is provided on the left side of the second block (12) and on the right side of the second block (12), and functions as a ground line for the circuit.

Here, the ground line (23) extending to the second block (12) is connected to the first ground line (1
9), so the contact hole (24
), (25) is avoided in the second layer.

Furthermore, the first block (11) and the second block (12)
There is a first shield electrode (26) and a second shield electrode (27) covering the entire top.

Here, the first shield electrode (26) and the second shield electrode (<27) are shown by solid lines in FIG. 1 and are formed in the second layer. This first shield electrode (26)
and a second shield electrode (27) extend from the lower side and are electrically connected to the first ground pad (20).

Here, since the shield electrodes (26) and (27) are formed in the second layer, they are connected to the electrodes in the first layer through the contact holes (28) indicated by X marks. .

The desks that characterize the present invention are located in the first dummy island (13), the second dummy island (14), and the separation area (15>).

The first dummy island (13) and the second dummy island (14) are connected to the power supply line V. 0 and the isolation region (15) is connected to the ground line GND, the isolation region (15) and the first dummy island
3), isolation region (15) and second dummy island (1
4) is reverse biased.

As a result, depletion layers are formed in the junction region between the isolation region (15) and the first dummy island (13) and in the junction region between the isolation region (15) and the second dummy island (14).

The current flowing from the first block L1 (11) in the direction of arrow A in FIG. 2 is suppressed by the depletion layer. Further, the current flowing from the second block 12) in the direction of arrow A in FIG. 2 is suppressed by the depletion layer. Therefore, the current mentioned here does not flow to the separation region (15), so the current described here does not flow to the separation region (15).
5) The voltage increase can be suppressed.

Therefore, the isolation region (15) that suppresses the rise in potential can completely suck out the leakage current flowing into the adjacent block in the semiconductor substrate (2) as shown by the arrow.

On the other hand, the shield electrodes (26) and (27) can prevent unnecessary radiation, make ohmink contact with the isolation region within the block, prevent potential rise, and further prevent mutual interference.

Further, the circuit pad (21) and the leakage absorbing pad (20) of the block are separated to prevent feedback of leakage current.

FIG. 3 shows a second embodiment of the present invention, and since it is basically the same as FIG. 1, the sectional view is omitted.

First power line (16) and second power line (17)
are connected to separate pads, a first power pad (31) and a second IE source pad (32).

Also, on the left side of the first block (11), the second block (
Ground line (22>) provided on the right side of 12).

(23) with separate ground pads (33), (3
4) is connected.

Here, the first block <11) and the second block (
12) Since the power supply line and the ground line are separated, the structure is such that fluctuations in the first block and the second block are not transmitted to other blocks.

(G) Effect of the invention As is clear from the above explanation, the first block (11
) and the second block <12), by providing a first dummy island (13) and a second dummy island (14) in which a depletion layer is formed, the inside of the epitaxial layer can be moved laterally. This prevents current from flowing to the cross separation region (15).

Therefore, leakage current within the semiconductor substrate (3) that causes mutual interference can be completely absorbed before flowing to the opposing block.

Therefore, by incorporating this configuration between blocks that cause mutual interference among multiple blocks formed in a semiconductor chip, it becomes possible to integrate high-frequency circuits etc. that are susceptible to mutual interference into one chip. .

Furthermore, this method can be applied to any block, top, bottom, left, or right, and has a wide range of applications.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a semiconductor integrated circuit according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view taken along line AA' in FIG. 1.
FIG. 3 is a plan view of a semiconductor integrated circuit according to a second embodiment of the present invention, and FIG. 4 is a sectional view of a conventional semiconductor integrated circuit.

Claims (3)

[Claims] (1) A first block and a second block integrated adjacently in a semiconductor substrate, and a first dummy island and a second dummy island surrounding the first block and second block. and a first power supply line electrically connected to a first dummy island provided between the first block and the second block, and a first power supply line provided between the first block and the second block. a second power supply line electrically connected to the second dummy island; and a first ground line electrically connected to the isolation region provided between the first dummy island and the second dummy island. A semiconductor integrated circuit characterized by comprising: (2) The ground line of the first block and the second block is provided on a side opposite to the side of the adjacent first block and second block. Semiconductor integrated circuit described in Section 1. (3) the pad of the first ground line and the pad of the first ground line;
2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is provided separately from the ground line pads of the first block and the second block.