JPH02136901A - Data processor - Google Patents

Abstract

PURPOSE:To realize the highly accurate output control by carrying out a process according to the process form information supplied previously without performing the saving processes of the PC and the PSW in case an interruption process request is received. CONSTITUTION:A data memory 213 stores the process form information which designates a prescribed data process form. A prescribed data process request is given to a CPU 200 from an interruption controller INTC 211 when an interruption request signal is received from a 1st comparing register 101. Then the CPU 200 interrupts an instruction executing process after detecting that a form designating signal 220 points a prescribed data process. Thus the CPU 200 operates a 2nd comparing register 102 and a data memory 213 based on the process form information in order to control the generation of pulses to output ports P0 - P3. As a result, the output control is attained with high accuracy.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a pulse generator that continuously outputs a plurality of pulses in pulse output e in mechanical control. [Prior Art] Recently, In mechanical control, microcontrollers (
A microcomputer (hereinafter referred to as a microcomputer) is used, and basically, the PWM output pulse output from the microcomputer is used to directly open and close valves, drive motors, etc.8 Fig. 6 shows examples of pulse output patterns when four pulses are output. - Numerically, pulse output control activates pulses after a certain time delay from the generation of some reference signal. The mechanism is driven during the period when the pulse output is active (high level).In this case, a certain time delay means the timing to output the pulse, and the pulse output is active (high level). The period during which the output is active (that is, the active pulse width) refers to the amount of control in itself.
The gas generating device will be explained below. FIG. 7 is a block diagram of a conventional pulse generator, and FIG. 8 is a block diagram of conventional peripheral hardware.

FIG. 7 shows the CPU 250, address bus 214, data bus 205, INTC 240, and Norogram memory 2.
12, data memory 213. Surrounding Birdow, r-'72
It consists of 22. The CPU 250 includes an arithmetic and logic operation unit (hereinafter referred to as A, T, and U) 201,
/volatile register 202, M register 203,
Address buffer 204 (represented by AB in the figure 5), microatto L/S (hereinafter referred to as μ address) generation unit 206, μROM 209, PC 207, PSW 20
8. An evening/timing control section 230 is also configured. Also I
The NTC (interrupt controller) 240 has an interrupt request flag register 215 that is set when an external input signal 260 is received, and outputs an interrupt request signal 821B to the timing control section 230.

The evening/timing control unit 230 outputs a 5 interrupt request clear signal 217 to the 1:NTC 240.

The INTC 240 accepts a number of interrupt signals from external hardware and assigns side inputs to each interrupt source. The interrupt source with the highest priority is selected 17, and the interrupt request 7 lag L register corresponding to that interrupt source is set. Interrupt request flag register (e) When there are n interrupt requests, n values are set, but only one is shown in the figure.

In addition, interrupt signals from external hardware, a priority order determining unit, and the like are not particularly shown in the figures.

Conventional interrupt processing is usually called vectored interrupt, and a vector table space is set in advance in memory 9, and in these 9 spaces there is a program corresponding to each interrupt source. The ntriadotos is stored λ′r−
There is C. When a vectored interrupt occurs, the address corresponding to the interrupt source is...
F)5 Next, using FIG. Get started. Periphery,...-Dware 222 (,
, l, clock as bar and 1. Tadownpu! Tsu、・′
It consists of registers 800-803, a port register 809, and output capos -1, PO to P3. The down counters 800 to 803 start decrement operation by writing the count value from the data bus 205, and when a borrow occurs due to the decrement from all 0, ]:NTC
Generates a 12 interrupt request to 240.

At the same time, each borrow causes down counters 800 to 803.
stops the decritane l- operation. Further, the control of the output signal is carried out from the data bus 205 to the port nozzle 80.
This is done by directly inputting the output level into 9 and 1F.

Below, we will focus on PO (Boat) and discuss the pulse output control in Boat 0.
In normal instruction processing, the CP
A = program address stored in U207 is transferred to the address buffer 204, the address bus 214 is moved, and the next instruction to be executed is fetched from the program memory 212.

The fetched instruction is transferred to the μ address generation unit 206 via the data bus 205. μ address generation section 2
-06 generates the address of μROM 209 from the instruction food. Thereafter, according to the instructions of the μ program for the instruction stored in the μROM 209, the general-purpose register 2
03, instructions are processed by operating the ALU 201, temporary register 202, etc.

: [NTC 240 independently of the processing of CPU 250,
It constantly samples whether or not an interrupt request is generated from peripheral hardware, and if a request is generated, the request is set to 1.
select one and set the interrupt request flag register corresponding to that source.

Here, the reference signal 0 is input to the external interrupt signal 260, and the reference signal 0 generates an interrupt request to the INTC 240. When the INTO 240 accepts the request and the interrupt request flag 215 is set, an interrupt request signal 218 is output to the timing control section 230.

The last command of the μ program is a command for detecting whether an interrupt has occurred or not. When this command is issued, the timing control unit 230 sends an interrupt request signal 21
Sample the presence or absence of 8. If the interrupt request signal 218 is active, the interrupt request clear signal 217 is
Output to NTC240, interrupt request flag 215
Clear.

Next, connect the PC 207 and PSW 208 to the stack pointer (C
It is saved in the stack space pointed to by a register (not shown) set in the PU 250, and corresponds to the interrupt source stored in the vector table set at a specific address in the data memory 213. The entry address of the interrupt processing program is read and set in the PC 207 via the data bus 205. PC
The reading processing program starts execution from the program address newly set in 207.

The interrupt processing program based on the reference signal O is
In the interrupt processing for setting the pulse output start timing from port PO, the CPU 250 writes data corresponding to the period from the generation of the reference signal 0 to the activation of the pulse output of the port PO to the down counter 800.

In the processing of the instruction to end the interrupt processing program, the PC value and psw value saved in the stack space are restored to the PC 207 and PSW 208, respectively, and processing is restarted from the next instruction at the time when the interrupt occurred.

Furthermore, when the above-described data is written by the CPU 250, the down counter 800 starts counting down in synchronization with this.

Next, during normal instruction execution, a pollo occurs from the down counter 800 indicating the pulse output start timing, and the INT
If the C240 accepts the interrupt, the CPU 250
Interrupt processing by polling from down counter 800 is performed. The period from when the INTC 240 accepts the poll from down counter 0 as an interrupt signal to when the execution of the interrupt processing program starts, and the operation of each hardware when the execution of the interrupt processing program is finished, is based on the above-mentioned standards. Since this is the same as the interrupt caused by signal O, the explanation will be omitted, and the contents of the interrupt processing program will be explained.

This interrupt processing program starts with port register 8.
Since the contents of port register 8090 are read and bit 0 of port register 8090 is "0", the CPU 250 sets bit 0 of port register 809 to "1". , baud) Set the PO color output pulse to high level,
Start pulse output. At the same time, down counter 800
Set the data corresponding to the pulse width to .

Furthermore, when the down counter 800 counts the pulse width set in the above-mentioned interrupt processing, pollow occurs again and an interrupt is generated to the INTC 240.

The interrupt processing program executed at this time first reads the contents of the port register 809, and since bit 0 of the port register 8090 is "1", the interrupt processing program executes at this time.
This is an interrupt process that lowers the pulse output at
Every time bit 0 of the boat register 809 is set to "0", the output pulse from the boat I/PO is set to low 1.
-bell, and end the pulse output 'Jb.

Similar processing is performed from Baud 1-P-1 to Baud) P3.
C has the same batting power. Examples of various pulse output control force methods have been shown above, but basically the same processing force method' control is performed.

Investigation solved the problem 1. Problems to be solved〕 Above 1. The conventional bus/L bus system ('1) transfers pulse train data by executing an interrupt processing program, so that interrupts can be generated when a reference signal is generated, when pulse output starts, and when pulse output ends. P every time processing starts
C.PSW.

After saving the general-purpose register and processing the interrupt, return to P.
Since it requires processing to restore C and PSW, CP
CP used for processing performed by U in addition to pulse output control
The U time decreases, reducing the execution efficiency of the CPU.

(2) The execution efficiency of the CPU described above deteriorates as the number of pulse outputs from the pulse generator increases and the number of output ports increases.

■ Method C, in which the pulse output is controlled solely by software processing using the interrupt processing function 1. There is a time delay between the start of the processing program and the start of the processing program.

Delays such as 2 steps occur due to the data write time, and highly accurate control is not possible.

■ Since an interrupt request is made for each down counter, the number of registers increases with the increase in the number of pulse output ports, so the interrupt in INTC),,), request flag also increases17, and the interrupt As the number of required signal lines increases, the wiring area between the INTC and peripheral hardware also increases, and the amount of hardware for the whole system increases, raising product costs.

It has the following drawbacks.

[Means for solving the problem] The present invention provides a PC, a PSW, a general-purpose v-, s-star, and a μROM.
Including the CPU and asynchronous processing requests to the CPU? In a processing device having a generating I NTC, a program memory, a data memory, and a peripheral circuit, the peripheral circuit includes a timer, a first register,
a second conveyor register, a capture 1 register,
a plurality of output ports for generating pulses, and means for selectively emitting set pulses to the output ports;
In addition to generating a conventional interrupt request, the INTC also includes means for generating a request for predetermined data processing in addition to generating a conventional interrupt request; comprising a mode specifying means for identifying a conventional interrupt request and a request for the predetermined data processing, and processing mode information for specifying a processing mode of the data geography given θj is stored in the data memory,
I) When a request for the predetermined data processing is issued from the INTC to the CPU due to the occurrence of an interrupt request, the CPU performs the processing according to the form. Detecting that the instructing stage is instructing the predetermined data processing; 1. ? In this case, the instruction execution process is interrupted and the one conveyor I/register and the r-ta memory are operated according to the processing mode information. :: and ff1f have the feature of controlling pulse generation from a plurality of output boards.

Therefore, in the present invention, (1) When an interrupt processing request that gives pulse output start timing is generated, the PC and PSW are not saved;
Processing according to the processing type information connected in advance? By executing this, it is possible to realize highly accurate pulse output control for a plurality of output capacitors.

■ By providing separate hardware for providing pulse output start timing and hardware for providing pulse output end timing, increase the output port of the pulse generator 1. If 1...=, the number of interrupt request signals to INTC does not increase.

This brings about this effect.

〔Example〕

The present invention will be explained in detail below using drawings! ``'B), 1 A first embodiment based on the present invention will be explained with reference to FIGS. 1 and 2. FIG. 1 is a block diagram of peripheral hardware of the first embodiment, and FIG. 2 is a block diagram of peripheral hardware of the first embodiment. 1 is a block diagram of a pulse generator showing a first embodiment; FIG.

In FIG. 2, the pulse generator of the present invention has a CPU 2
00, address bus 214, data bus 205, IN
TC211, program memory 212, data memory 2
13 and peripheral hardware 211.

The CPU 200 has an ALU 201 and a temporary register 2.
02, general-purpose register 203, address buffer 204,
μ address generation unit 206, μROM 209, PC 207
, PSW 208, and timing control section 210. The INTC 211 also includes an interrupt request flag register 215 and a format designation flag register 216, and outputs an interrupt request signal 218 and a format designation signal 220 to the timing control section 210. Timing control section 210 outputs interrupt request clear signal 217 and form change signal 219 to INTC 211 .

The INTC 211 accepts several interrupt signals from external hardware (only the match signal 106 is shown in the diagram), determines the priority assigned to each interrupt source, and determines which interrupt source has the highest priority. Select one interrupt source and set the interrupt request flag register corresponding to that interrupt source. Although n interrupt request flag registers and mode designation flag registers are each set when there are n interrupt requests, only one set is shown in the figure. Further, interrupt signals from external hardware, a priority order determining section, and the like are not particularly illustrated because they are not directly related to the gist of the present invention.

The CPU 200 can process interrupt requests from the INTC 211 in a second-order format.

One is traditional vectored interrupt processing, and the other is
In the processing mode that is the gist of the present invention, when an interrupt occurs, the vector table is not referenced and the data memory 2 is
This is a mode in which predetermined data processing is executed based on processing mode information preset to a specific address in 13.

Hereinafter, this predetermined data processing will be referred to as a macro service.

A vectored interrupt or a macro service is specified by the type specification flag register 216. When the CPU 200 sets the type specification flag register 216 to On, it is specified as a vectored interrupt, and when it is set to "1," it is specified as a macro service. Ru.

The dedicated node hardware configuration and the flow of Mac4 service processing in pulse output control according to the present invention will be described below. First, the structure of the peripheral hardware 221 will be explained using FIG.

The peripheral hardware 221 includes a free running timer 100 (denoted as FRT in the figure) whose pace is clock φ.
Conveyor register 101 (written as GOMPIO in the figure) and 102, 103, 104°105 (C0MP in the figure)
2O, 21, 22, 23), capture register 120 (described as 0APT10 in the figure), bit selection register 125, first external input signal 130, output capo)
Consists of PO-P3. The match signal 106 is output from the conveyor register 101 and also supplied to the INTC 211 . In addition, the coincidence signals 107, 108, 109, 11
0 is conveyor register 102, 103, 104, 105
It is output from. In addition, the first external input signal 130
The above-mentioned reference signal is input to .

Next, processing type information that specifies the processing type of the macro service of the present invention will be explained. FIG. 3 shows the structure of processing mode information. The processing mode information is placed at a specific address in the data memory 213, and the processing mode information in this example is composed of a 1-byte header section having a channel pointer and an 8-byte macro service channel pointed to by the channel pointer. Ru.

The macro service channel in this example has a configuration assuming four pulse output control, and is composed of a word buffer (for PO to P3) that specifies the pulse output width.

In the conveyor register 101, t data indicating the displacement from the reference signal to the pulse output start timing in pulse output control is set by the CPU 200t. When the reference signal is generated, the capture register 120 stores the value of FRTloo according to the reference signal. At the same time, the reference signal generates an interrupt, and the CPU 200 outputs the FL signal stored in the cabcha 1 Fujistar 120 at the time of generation of the disease standard signal.
Based on the count value of T100, data is set in the conveyor register 101 by the interrupt processing program. In the present invention: Book conveyor register〕01
Seven pulses of output started for multiple output boats in the evening (i
:, /gun give/, -me, I am performing the selection of basic single words tg.

In this example, the watch is activated by a signal δ 106 from the conveyor registers 101.

I: Before the I service is activated, the CP
U200 is a 1-bit selection register that performs initialization for novice channels and bar software; and 25 specifies that the 5F port that should output the pulse first is PO. 〜ri “Lotome, Bo) PO
Compatible with ] ° Rubi,.

Set only 1 and 7 to 0 except for 11c.

Figure 4 shows the macro ``' service of this example as
As shown in Figure 7, it is actually (Maμs 1-1 gram control. Below, refer to Figures 1 to 4, 1-5s, and Figure 6.1). A detailed explanation will be provided.

First, when the -i signal 106 from the compen 1/register 10 is generated, from the initial value of the bit selection 1 register 125, the RS flip r! of baud +-po is generated. The output pulse from PO becomes high level, and the pulse output from PO starts.
At the same time, the match signal 106 generates an interrupt request for 1NTc21].

When the INTC 211 accepts the match signal 1060 interrupt request, the interrupt request flag register 215 corresponding to this source is set to - Sera I 12, interrupt request signal 2.
Activate 18.

Timing control unit 2]0 samples an interrupt request at the end of instruction processing. Here Q interrupt 9 request signal 218
is acte, eve, -me, form specification signal 220
sample. When it is detected that the format designation signal 220 is "1" indicating Mac1"-Chi-Vis, C1,"
U2O5 starts macro service processing unit generation t2 and macro service of μTtOM209 while holding PC207 and PSW208.

Hereinafter, the explanation of the processing flow according to the μB 11gram command of MacroSevis will be explained along the lines shown in F4-1-1 of FIG.

First, read the macro service ladder using the match signal 106 as an interrupt source from a specific address in the data memory 213.1.2 Detect the position of the macro service channel; Bit selection 1. /Jista 12
Please refer to 5 and refer to 1.
Read the seed buffer in the macro service channel corresponding to.

Furthermore, the contents of the conveyor register 101 and the readout 1-
The second seed buffer is added using the ALU 201 as flJ, and the result W is stored in the conveyor register 102.

Next, left shift processing of the bit selection register 125 is executed, and only the bit corresponding to 111 (1.5, baud) is set to 1. The timing control unit 210 outputs interrupt request clear signals 2J and 7 to the INTC 211,
The interrupt request flag registers 2 and 5 are reset and the macro service processing ends.

When the macro service processing is completed, the CPU 200 holds t, "Ci'7'jPC207, PSW:?, O8(
7) Resume normal instruction processing from the value.

Figure 6 l) t, r; In the case of a pulse pattern,
When the match signal 107 is generated from the conveyor register 102, the match signal 106 is generated again from the conveyor register 101.

At this time, only the RS flip-flop of Bo) Pl is
- The output pulse from Pi becomes high level, the boat P1 starts to output pulses, and both boats PO and Pl output pulses.

The above processing is repeated in the same manner from PO to P3. The macro service that is activated by the timing of the pulse output to boat P3 performs similar macro service processing, but in the fourth macro service processing, when the left shift processing of the bit selection register 125 is executed, the bit selection A shift out occurs from the register 125, and the timing control unit 210 receives a command from the μ program.
outputs the format change signal 219 to the INTC 211 and resets the format designation flag register 216.

INTC211 interrupt request flag register 215
is in the set state and the format specification flag register 216 is in the reset state, this time a normal vector interrupt request is generated to the CPU 200, and the CPU 200 executes the following vector interrupt processing.

The interrupt processing program is started after completing one cycle from baud)PO to P3, and the CPU 200 resets the bit selection register 125 to the initial state, updates the word buffer in the macro service channel, and executes the update of the word buffer in the macro service channel.
Prepare for pulse output from.

As described above, the pulse output device of this embodiment can realize the output of the Nahals pattern as shown in FIG. 6 by applying the present macro service processing.

Next, a second embodiment of the present invention will be described using FIG. 5. FIG. 5 is a block diagram of peripheral hardware of the second embodiment. The overall configuration of the system and the configuration of macro service processing form information are the same as those in the first embodiment, so their explanations will be omitted.

The configuration of the peripheral hardware 221 in this embodiment is as follows.
The 0 peripheral hardware 221, which will be explained using the diagram, is the second
Event counter 500 . Conveyor registers 501-505. Capture register 520° Bit selection register 525. 1st
It is composed of an external input signal 530 and output signals PO to P3.

A match signal 506 is output from the conveyor register 501, and similarly match signals 507 to 510 are output from the conveyor register 5.
It is output from 02 to 505. event counter 5
00 performs a counting operation every time a pulse occurs in the second external input signal 531.

In this embodiment, by inputting a pulse generated each time the rotating body rotates by a certain angle to the external input signal 530, highly accurate pulse output control for each angle of the rotating body is possible. Since the detailed operation is exactly the same as the first embodiment, detailed explanation will be omitted.

〔Effect of the invention〕

As explained above, in the present invention, the interrupt at the pulse output start timing is processed by the macro service and no vectored interrupt request is generated.
, psw to the stack, or when returning from the interrupt processing program to main processing, the contents of the stack are saved to the PC2P.
Processing to return to SW does not occupy CPU time.

In addition, in recent mechanical controls that require high-speed, high-precision control, highly accurate pulse output control has become necessary.
By directly controlling the port and generating output pulses using the match signal from the conveyor register that gives the pulse output end timing, the time delay from the occurrence of an interrupt factor to the start of the interrupt processing program, and the time delay to the port. Since the output pulse width can be controlled with a minimum error without any delay due to the data writing time, the output pulse width can be adjusted with high precision.

In addition, the pulse generator of the present invention employs a system in which a specific single conveyor register gives the pulse output start timing for each port, and a plurality of conveyor registers gives the pulse output end timing for each port. Even if the number of output ports increases to 6 or 8, exactly the same control can be achieved by simply increasing the number of conveyor registers that provide pulse output end timing and the number of word buffers in the macro service channel. Furthermore, since the interrupt request signal for INTO is always generated by only a single conveyor register, the interrupt request flag in INTC, INT
Therefore, there is no increase in hardware such as C and peripheral hardware and wiring area.

The pulse generator of the present invention can accommodate an increase in the number of pulse output ports with minimal addition of hardware.
This will create an economically very advantageous system.
It is possible to integrate the CPU and peripheral circuits on a single board, making it suitable for single chips.
I can do a lot of things.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of peripheral/1-doware in the first embodiment of the present invention, and FIG. 2 is a block diagram of the first embodiment of the present invention.
Pal;
) Embodiment 1 (〆1゛() McCrory screw processing flow chart 1, Figure 5 is the second 5J of the present invention: Absolutely ζ・)Program diagram of peripheral hardware , Fig. 6 shows the pulse output 1:l ['l baba-n from bo. is block N of peripheral hardware in the conventional example. 100...Free runnisog timer, 101.
〜105.501・-505・・・・・・ko]/Bear I
/JISTA, 106・110.5 (] to 6・510・・
... Match signal, 120.520 ... Capture 1. - Register, 125525...Bit selection register, 130,530...First external input signal, 200,250...CP TJ, 2
01...ALU, 202...Temperature, 2nd disk, 203...General purpose register, 2
04...Ato 1/Subatuhua, 205...
・・Data bus, 206・・・・μ at 1-・Succeeding part, 207・・・・PC1208・・・・P
SW, 209...μP, OM, 210°2
3(]...timing control section, 2]], 240
...INT(":, 212...)r7
Durham memory, 213... Data 2 Simory, 2
14...Address bus, 2]5...Interrupt request flag l, = Jime, Ri, 216...Form specification flag 1/Jister, 217...Interrupt Insert request clear signal, 2; 18... Interrupt request value No. 5, 219... Form change signal, :220...
...Shadow status designation signal, 221.222...Peripheral bar, ): I'T air, 260...External interrupt fast input signal, 500...Event h Unta, 5
31...2nd suspension 1 part input signal, 800 = -8
0:3...down counter/evening, 809...
Boat register. 1 Hara Susumu θ・0I
6) % Q, ,-to I\ 1 C--,,-=j de・kube9 ξmi5≧ Mutsut broom

Claims (1)

[Claims] A central processing unit that includes a program counter that holds the execution address of an instruction, a means for holding the execution state of the program, a general-purpose register as a high-speed storage means, and a microprogram ROM, and an interrupt that asynchronously issues a processing request to the central processing unit. In a data processing device including a request generation circuit, a program memory, a data memory, and a peripheral circuit, the peripheral circuit includes a timer, a first conveyor register that performs a comparison with the timer, and a plurality of second conveyor registers. a conveyor register, a capture register for storing the value of the timer at a predetermined timing, a plurality of output ports for generating pulses, means for selectively generating set pulses for the output ports, and the first an interrupt request signal from a conveyor register to the interrupt request generation circuit; the interrupt request generation circuit includes means for generating a request for predetermined data processing; and means for specifying a form for identifying the request for predetermined data processing. Processing mode information specifying a processing mode of the predetermined data processing is stored in the data memory, and when an interrupt request signal is generated from the first conveyor register, the interrupt request generation circuit outputs the processing mode information. When a request for predetermined data processing is issued to the central processing unit, the central processing unit executes command execution processing if it detects that the format instruction means is instructing the predetermined data processing. The data processing apparatus is characterized in that the pulse generation from the plurality of output ports is controlled by interrupting the processing and operating the second conveyor register and the data memory according to the processing mode information.