JPH02132876A - Manufacture of hybrid integrated circuit device - Google Patents

Manufacture of hybrid integrated circuit device

Info

Publication number
JPH02132876A
JPH02132876A JP28578488A JP28578488A JPH02132876A JP H02132876 A JPH02132876 A JP H02132876A JP 28578488 A JP28578488 A JP 28578488A JP 28578488 A JP28578488 A JP 28578488A JP H02132876 A JPH02132876 A JP H02132876A
Authority
JP
Japan
Prior art keywords
circuit
board
substrates
integrated circuit
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28578488A
Other languages
Japanese (ja)
Inventor
Jiro Hagiwara
萩原 次朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiyo Yuden Co Ltd
Original Assignee
Taiyo Yuden Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiyo Yuden Co Ltd filed Critical Taiyo Yuden Co Ltd
Priority to JP28578488A priority Critical patent/JPH02132876A/en
Publication of JPH02132876A publication Critical patent/JPH02132876A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/16Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits

Abstract

PURPOSE:To make an overall circuit, which is composed of circuit substrates heaped up, precise in electrical characteristics by a method wherein two or more substrates are connected together through deformable connecting pieces, resistors are trimmed, and then the circuit substrates are heaped up by bending the connecting pieces. CONSTITUTION:Circuit substrates 21 and 22 and circuit substrates 22 and 23 are electrically and mechanically connected with each other through connecting pieces 24a and 24b respectively. Then, thick film resistors 22a and 22b of the circuit substrate 22 are trimmed measuring an overall circuit characteristic of the circuit substrates 21-23 combined in one and the overall circuit characteristic is adjusted to a specified value. After the adjustment has been finished, the circuit substrates 21-23 are heaped up bending the connecting pieces 24a and 24b. By this constitution, the characteristics of an overall circuit can be made equal to those of the over all circuit of the substrates 21-23 precisely trimmed before heaped up.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、混成集禎回路装置の全体の電気特性値の精度
を向上させるようにした混成集積回路装置の製造方法に
関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a hybrid integrated circuit device that improves the accuracy of the overall electrical characteristic values of the hybrid integrated circuit device.

従来の技術 電子供給の小型化、高性能化に伴い、混成集積回路装置
の小型化や多機能化が要求されている。
BACKGROUND OF THE INVENTION As electronic supplies become smaller and more sophisticated, hybrid integrated circuit devices are required to be smaller and more functional.

これに応えるものとして、回路の配線を基板の内部で行
う多層基板が開発された。
In response to this, multilayer boards have been developed in which circuit wiring is done inside the board.

しかしながら、さらに高度な多機能化が要求されるよう
になって、回路基板に実装される電子gB品の総数が増
加し、多層基板の内部回路に必要な電子部品の全てを表
面に実装できない場合が起こっている。
However, as more advanced multi-functionality is required, the total number of electronic GB products mounted on a circuit board increases, and in some cases, it is not possible to mount all of the electronic components necessary for the internal circuit of a multilayer board on the surface. is happening.

これに対しては、電子部品を実装するスペースを多くす
る技術的工夫がなされ、多層基板内にコンデンサを内蔵
するものや、基板を重ねてその間に抵抗体を設けるなど
のことがなされている。
To address this, technological innovations have been made to increase the space for mounting electronic components, such as embedding a capacitor in a multilayer board, or stacking boards and installing a resistor between them.

例えば、第4図に示すように、基板1にチ,プ部品1a
、基板2に厚膜抵抗体2a、基板3に厚膜抵抗体3aを
実装するとともに、スルーホールの接続部を基板1に1
b、1c、ld,基板2に2b、基板3には3b, 3
cをそれぞれ設け、基板1のスルーホールの接続部1b
と基板2、基板2のスルーホールの接続部2bと基板1
のスルーホールの接続部1d,基坂2と基板3のスルホ
ールの接続部3bのそれぞれをスベーサー兼用の接続体
4a、4b、4Cで電気的かつ機械的に接続した構造が
知られている。
For example, as shown in FIG.
, the thick film resistor 2a is mounted on the substrate 2, the thick film resistor 3a is mounted on the substrate 3, and the connection portion of the through hole is mounted on the substrate 1.
b, 1c, ld, 2b on board 2, 3b, 3 on board 3
c are respectively provided, and the connection portion 1b of the through hole of the substrate 1 is provided.
and the board 2, and the connection part 2b of the through hole of the board 2 and the board 1
A structure is known in which the through-hole connecting portion 1d of the substrate 2 and the through-hole connecting portion 3b of the substrate 3 are electrically and mechanically connected by connecting bodies 4a, 4b, and 4C that also serve as spacers.

また、第5図に示すように、基板11にチップ部品11
a、基板12に厚膜抵抗体12a 、12b 、基板1
3にチップ部品13aをそれぞれ実装し、これらをそれ
ぞれの基板の両端の一方の接続部1lb , 12c 
,13bに断面コ字状嵌合部を嵌合しかつ半田付けする
ことにより接続片14aを接続.し、他方の接続部11
c 、12a 、13cに接続片14aと同様の接続片
14bを接続し、それぞれの接続片14ab、14bの
下端にリードピン15a 、15bを形成した構造も知
られている。
Further, as shown in FIG. 5, a chip component 11 is mounted on the substrate 11.
a, thick film resistors 12a, 12b on the substrate 12, substrate 1
Chip components 13a are mounted on the board 3, and these are connected to one connection part 1lb, 12c at both ends of each board.
, 13b, and connect the connecting piece 14a by fitting the fitting portion with a U-shaped cross section and soldering. and the other connection part 11
A structure is also known in which a connecting piece 14b similar to the connecting piece 14a is connected to the connecting pieces 14b, 12a, and 13c, and lead pins 15a and 15b are formed at the lower ends of the respective connecting pieces 14ab and 14b.

発明が解決しようとする課題 しかしながら、このように回路の高密度化が可能になっ
ても、各基板の回路を組み合わせた全体の回路の電気特
性値を調整するときは、各回路基坂を第4図、第5図の
ように組み立てた後では第4図の厚膜抵抗体2a、3a
や、第4図の厚膜抵抗体12a 12bは内部に組み込
まれているので、そのトリミングを行うことができない
。そのため、その組み立て前の個々の回路基板のそれぞ
れの厚膜抵抗体についてトリミングを行う以外に方法が
ない。
Problems to be Solved by the Invention However, even if it becomes possible to increase the density of circuits in this way, when adjusting the electrical characteristic values of the entire circuit that combines the circuits of each board, it is difficult to adjust the electrical characteristics of each circuit board. After assembling as shown in FIGS. 4 and 5, the thick film resistors 2a and 3a in FIG.
Also, since the thick film resistors 12a and 12b shown in FIG. 4 are built inside, they cannot be trimmed. Therefore, there is no other way than to trim each thick film resistor of each circuit board before assembly.

しかし、、このようにするときは、個々の回路基板の回
路を組み合わせたときには全体回路の電気特性値につい
て所定の正確な値が得られず、その精度も良《ない。
However, when doing this, when the circuits of the individual circuit boards are combined, it is not possible to obtain a predetermined accurate value for the electrical characteristic value of the entire circuit, and the accuracy is also poor.

特に各基板の接続が半田で行われるときは、その半田付
けのときの熱により基板が歪みを生じ易く、これにより
電子部品の取付け状態が変化したり、厚膜抵抗体の抵抗
値も異なることがある。
In particular, when each board is connected by soldering, the board is likely to become distorted due to the heat generated during soldering, which may change the mounting condition of electronic components or cause a difference in the resistance value of thick film resistors. There is.

本発明の目的は、複数の回路基坂を組み合わせた全体回
路の電気特性値を所定の値に精度良く得られるようにし
た混成集積回路装置の製造方法を提供するものである。
SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a hybrid integrated circuit device, which allows the electrical characteristic values of the entire circuit, which is a combination of a plurality of circuit boards, to be accurately obtained to predetermined values.

課題を解決するための手段 本発明は、上記課題を解決するために、複数の回路基板
を接続して電子回路を構成する混成集積回路装置の製造
方法において、上記複数の回路基板を変形可能な接続片
により電気的かつ機械的に接続する工程と、上記回路基
板に設けた抵抗体のトリミングにより上記混成集積回路
装置の全体回路の電気的特性値を調整する工程と、上記
複数の回路基板を上記接続片の折り曲げにより積み重ね
る工程を有することを特徴とする混成集積回路装置の製
造方法を提供するものである。
Means for Solving the Problems In order to solve the above problems, the present invention provides a method for manufacturing a hybrid integrated circuit device in which a plurality of circuit boards are connected to form an electronic circuit, in which the plurality of circuit boards are deformable. a step of electrically and mechanically connecting the plurality of circuit boards with a connecting piece; a step of adjusting electrical characteristic values of the entire circuit of the hybrid integrated circuit device by trimming a resistor provided on the circuit board; The present invention provides a method for manufacturing a hybrid integrated circuit device, which comprises a step of stacking the connecting pieces by bending them.

作用 複数の回路基板を変形可能な接続片により電気的かつ機
械的に接続し、この状態で抵抗体に対してトリミングを
行ってから、各回路基板を接続片の折曲により積み重ね
るようにしたので、装置の全体回路の特性値を回路基板
を重ねる前の正確なトリミングを行なった特性値と同じ
にできる。
Function: Multiple circuit boards are connected electrically and mechanically using deformable connection pieces, and after trimming the resistor in this state, each circuit board is stacked by bending the connection pieces. , the characteristic value of the entire circuit of the device can be made the same as the characteristic value obtained by performing accurate trimming before stacking the circuit boards.

実施例 次に本発明の一実施例を第1図及び第2図に基づいて説
明する。
Embodiment Next, an embodiment of the present invention will be explained based on FIGS. 1 and 2.

2L22、23は回路基板である。回路基板21にはチ
ップ部品21aが実装され、その両端に基板接続部2l
b 、21Cが形成され、それぞれの接続部には断面コ
の字状嵌合部を半田付けすることによりリード端子21
d 、21eが取付けられている。回路基板22も同様
に厚膜抵抗体22a 、22bがその表裏に実装され、
その両端に基板接続部22c 、22dが形成され、回
路基板23も同様にチップ部品23aが実装され、その
一端に基板接続部23bが設けられている。
2L22, 23 are circuit boards. A chip component 21a is mounted on the circuit board 21, and board connecting portions 2l are provided at both ends of the chip component 21a.
b, 21C are formed, and a lead terminal 21 is formed by soldering a U-shaped fitting portion in cross section to each connection portion.
d, 21e are attached. Similarly, thick film resistors 22a and 22b are mounted on the front and back sides of the circuit board 22.
Board connecting portions 22c and 22d are formed at both ends thereof, and a chip component 23a is similarly mounted on the circuit board 23, and a board connecting portion 23b is provided at one end thereof.

このように設けられた各回路基板は、回路基坂21と2
2が基板接続部21cのリード端子21eの嵌合部と基
板接続部22cに嵌合され半田付けされた嵌合部の上側
面が導電性かつ変形可能な接続片24aにより接続され
、また、回路基板22と23が基板接続部22dと23
bのそれぞれに嵌合され半田付けされた嵌合部の下側面
が導電性かつ変形可能な接続片24bにより電気的かつ
機械的に接続される。なお、各嵌合部と接続片は一体の
部材を用いる。
Each circuit board provided in this way is connected to the circuit board slopes 21 and 2.
2, the fitting part of the lead terminal 21e of the board connecting part 21c and the upper surface of the fitting part fitted and soldered to the board connecting part 22c are connected by a conductive and deformable connecting piece 24a, and the circuit The boards 22 and 23 are connected to the board connection parts 22d and 23.
The lower surfaces of the fitting portions fitted and soldered to each of the portions b are electrically and mechanically connected by a conductive and deformable connecting piece 24b. Note that each fitting portion and the connecting piece are made of an integral member.

この後、リード端子21d 、21eに図示省略した電
気回路特性値測定回路を接続し、回路基坂21、22、
23を組み合わせた全体の回路特性を測定しながら、回
路基板22の厚膜抵抗体22a 、22bをレーザ等に
より切り溝を入れてトリミングを行う、いわゆるファン
クショントリミングを行い、全体回路の特性値を所定の
値に調整する。
After that, an electrical circuit characteristic value measuring circuit (not shown) is connected to the lead terminals 21d and 21e, and the circuit boards 21, 22,
While measuring the overall circuit characteristics of the circuit board 23, so-called function trimming is performed, in which the thick film resistors 22a and 22b of the circuit board 22 are trimmed by cutting grooves using a laser or the like, and the characteristic values of the entire circuit are determined by predetermined values. Adjust to the value of

この調整が終わった後、接続片24a 、24bを折り
曲げて第2図のように各回路基板を槓み重ねる。
After this adjustment is completed, the connecting pieces 24a and 24b are bent and the circuit boards are pressed together as shown in FIG.

このようにすると、その全体回路の特性値はこの積み重
ね前の正確にトリミングを行った特性値と同じにするこ
とができる。
In this way, the characteristic value of the entire circuit can be made the same as the characteristic value obtained by precisely trimming before stacking.

上記は各回路基板を平面に接続して全体回路の調整を行
うようにトリミングを行ったが、第3図に示すように回
路基板31に厚膜抵抗体31aを実装するとともに、回
路基板32にチップ部品32aを実装し、回路基板32
の一端に基板接続部32bを形成し、他端にダミーリー
ド32cを取付ける。そして基板接続部32bを回路基
板31に接続片33により半田付け等により両基坂が直
角になるように接続し、この状態で両回路基板の回路を
組み合わせた全体回路の調整を厚膜抵抗体31aのトリ
ミングにより行い、この後回路基坂32の他端のダミー
リード32cを回路基坂31に設けたダミーランド3l
bに半田付けし、機械的に接続し固定するようにしても
良い。この場合は、回路基板32が回路基坂31より小
さい場合に適している。
In the above, trimming was performed so that each circuit board was connected to a plane to adjust the entire circuit, but as shown in FIG. The chip component 32a is mounted and the circuit board 32
A board connecting portion 32b is formed at one end, and a dummy lead 32c is attached to the other end. Then, connect the board connecting portion 32b to the circuit board 31 by soldering or the like using the connecting piece 33 so that the two base slopes are at right angles, and in this state, adjust the entire circuit combining the circuits of both circuit boards using the thick film resistor. After that, the dummy lead 32c at the other end of the circuit board slope 32 is trimmed on the circuit board slope 31 by trimming the dummy land 3l.
b may be soldered to mechanically connect and fix. This case is suitable when the circuit board 32 is smaller than the circuit board slope 31.

発明の効果 本発明によれば、複数の回路基板を組み合わせて構成さ
れる混成集積回路装置の全体回路の電気特性値の調整を
各回路基板を変形可能な接続片により接続して抵抗体の
トリミングにより行い、この後各回路基板を接続片の変
形により積み重ねるようにしたので、その積み重ね前に
全体回路の電気特性値を所定の値に調整することができ
、したがってこの積み重ね後の全体回路の電気特性値も
正確かつ精度良く所定の値にすることができる。
Effects of the Invention According to the present invention, the electrical characteristic values of the entire circuit of a hybrid integrated circuit device constructed by combining a plurality of circuit boards can be adjusted by connecting each circuit board with a deformable connection piece and trimming the resistor. After that, each circuit board is stacked by deforming the connection piece, so the electrical characteristic value of the entire circuit can be adjusted to a predetermined value before stacking, and therefore the electrical characteristics of the entire circuit after stacking can be adjusted to a predetermined value. Characteristic values can also be set to predetermined values with accuracy and precision.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の方法の一工程を示す側面図
、第2図はその完成状態を示す側面図、第3図は他の実
施例の方法の一工程を示す側面図、第4図は従来の混成
集積回路装置の断面図、第5図は従来の他の混成集積回
路装置の側面図である。 図中、21、22、23、31、32と回路基板、22
a、22b , 31aは厚膜抵抗体、24a 、24
b 、33は接続片である。 第1図 第51
FIG. 1 is a side view showing one step of a method according to an embodiment of the present invention, FIG. 2 is a side view showing its completed state, and FIG. 3 is a side view showing one step of a method according to another embodiment. FIG. 4 is a sectional view of a conventional hybrid integrated circuit device, and FIG. 5 is a side view of another conventional hybrid integrated circuit device. In the figure, 21, 22, 23, 31, 32 and a circuit board, 22
a, 22b, 31a are thick film resistors, 24a, 24
b, 33 is a connecting piece. Figure 1 51

Claims (1)

【特許請求の範囲】[Claims] (1)複数の回路基板を接続して電子回路を構成する混
成集積回路装置の製造方法において、上記複数の回路基
板を変形可能な接続片により電気的かつ機械的に接続す
る工程と、上記回路基板に設けた抵抗体のトリミングに
より上記混成集積回路装置の全体回路の電気的特性値を
調整する工程と、上記複数の回路基板を上記接続片の折
り曲げにより積み重ねる工程を有することを特徴とする
混成集積回路装置の製造方法。
(1) A method for manufacturing a hybrid integrated circuit device in which a plurality of circuit boards are connected to form an electronic circuit, including the step of electrically and mechanically connecting the plurality of circuit boards with a deformable connecting piece; A hybrid integrated circuit device comprising: adjusting electrical characteristic values of the entire circuit of the hybrid integrated circuit device by trimming a resistor provided on the substrate; and stacking the plurality of circuit boards by bending the connecting pieces. A method of manufacturing an integrated circuit device.
JP28578488A 1988-11-14 1988-11-14 Manufacture of hybrid integrated circuit device Pending JPH02132876A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28578488A JPH02132876A (en) 1988-11-14 1988-11-14 Manufacture of hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28578488A JPH02132876A (en) 1988-11-14 1988-11-14 Manufacture of hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPH02132876A true JPH02132876A (en) 1990-05-22

Family

ID=17696024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28578488A Pending JPH02132876A (en) 1988-11-14 1988-11-14 Manufacture of hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPH02132876A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02189992A (en) * 1989-01-18 1990-07-25 Mitsubishi Electric Corp Method for assembling boards
US5267126A (en) * 1991-03-28 1993-11-30 The Whitaker, Corporation Electrical interconnection system
US9228576B2 (en) 2012-11-05 2016-01-05 Kabushiki Kaisha Toyota Jidoshokki Swash plate type variable displacement compressor
US9228577B2 (en) 2012-11-05 2016-01-05 Kabushiki Kaisha Toyota Jidoshokki Swash plate type variable displacement compressor
US9309875B2 (en) 2012-11-05 2016-04-12 Kabushiki Kaisha Toyota Jidoshokki Swash plate type variable displacement compressor
US9309874B2 (en) 2012-11-05 2016-04-12 Kabushiki Kaisha Toyota Jidoshokki Swash plate type variable displacement compressor
US9316217B2 (en) 2012-11-05 2016-04-19 Kabushiki Kaisha Toyota Jidoshokki Swash plate type variable displacement compressor
US9903352B2 (en) 2012-11-05 2018-02-27 Kabushiki Kaisha Toyota Jidoshokki Swash plate type variable displacement compressor

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02189992A (en) * 1989-01-18 1990-07-25 Mitsubishi Electric Corp Method for assembling boards
US5267126A (en) * 1991-03-28 1993-11-30 The Whitaker, Corporation Electrical interconnection system
US9228576B2 (en) 2012-11-05 2016-01-05 Kabushiki Kaisha Toyota Jidoshokki Swash plate type variable displacement compressor
US9228577B2 (en) 2012-11-05 2016-01-05 Kabushiki Kaisha Toyota Jidoshokki Swash plate type variable displacement compressor
US9309875B2 (en) 2012-11-05 2016-04-12 Kabushiki Kaisha Toyota Jidoshokki Swash plate type variable displacement compressor
US9309874B2 (en) 2012-11-05 2016-04-12 Kabushiki Kaisha Toyota Jidoshokki Swash plate type variable displacement compressor
US9316217B2 (en) 2012-11-05 2016-04-19 Kabushiki Kaisha Toyota Jidoshokki Swash plate type variable displacement compressor
US9903352B2 (en) 2012-11-05 2018-02-27 Kabushiki Kaisha Toyota Jidoshokki Swash plate type variable displacement compressor

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