JPH06350233A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JPH06350233A JPH06350233A JP16390093A JP16390093A JPH06350233A JP H06350233 A JPH06350233 A JP H06350233A JP 16390093 A JP16390093 A JP 16390093A JP 16390093 A JP16390093 A JP 16390093A JP H06350233 A JPH06350233 A JP H06350233A
- Authority
- JP
- Japan
- Prior art keywords
- circuit pattern
- circuit board
- conductive paste
- embedding
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 238000010304 firing Methods 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000005476 soldering Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、絶縁基板の表面に複数
の所望の素子を実装する回路基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board on which a plurality of desired elements are mounted on the surface of an insulating board.
【０００２】[0002]
【従来の技術】各種電子機器の組み立てには、必要とす
る回路構成に応じて絶縁基板の表面に抵抗、コンデンサ
ー、ＩＣ、トランジスター等の複数の所望の素子を半田
付けにより実装した回路基板が用いられる。図１２はこ
のような回路基板の一部を示す上面図で、基板３１の表
面の所望位置には複数の所望の素子２３，２４…２６，
２７が搭載されて、各素子は導電性材料からなる配線パ
ターン２８によって必要な回路構成となるように電気的
に接続されている。図１３は図１２の一つの素子の詳細
な断面図を示すもので、３１は鉄等の基板、３２はこの
基板３１上に形成された絶縁層、２８はこの絶縁層３２
上に形成された銅等の配線パターン、３４はこの配線パ
ターン２８上に形成されたレジスト、３５は両端の電極
３５Ａ，３５Ｂが半田３６によって配線パターン２８に
接続された抵抗等の素子である。2. Description of the Related Art For assembling various electronic devices, a circuit board is used in which a plurality of desired elements such as resistors, capacitors, ICs, and transistors are mounted on the surface of an insulating substrate by soldering according to the required circuit configuration. To be FIG. 12 is a top view showing a part of such a circuit board, and a plurality of desired elements 23, 24 ...
27 is mounted and each element is electrically connected by a wiring pattern 28 made of a conductive material so as to have a necessary circuit configuration. FIG. 13 is a detailed sectional view of one element of FIG. 12, 31 is a substrate made of iron or the like, 32 is an insulating layer formed on the substrate 31, and 28 is an insulating layer 32.
A wiring pattern made of copper or the like formed above, 34 is a resist formed on this wiring pattern 28, and 35 is an element such as a resistor in which electrodes 35A and 35B at both ends are connected to the wiring pattern 28 by solder 36.
【０００３】図１４は他の例の回路基板の一部を示す上
面図で、金属材料からなる導電部４２（前記配線パター
ンに相当）をプレス加工によって形成すると共に、導電
部４２以外の部分に樹脂部４３を成型することにより絶
縁基板４１を形成し、予め設けた挿入孔に所望の素子４
４，４５，４６，…のリードを挿入することにより各リ
ードを半田付けして、図１５に示すように各素子を各導
電部４２間に接続するようにしたものである。FIG. 14 is a top view showing a part of a circuit board of another example. A conductive portion 42 (corresponding to the wiring pattern) made of a metal material is formed by press working, and a portion other than the conductive portion 42 is formed. The insulating substrate 41 is formed by molding the resin portion 43, and the desired element 4 is inserted into the insertion hole provided in advance.
The leads are soldered by inserting the leads 4, 45, 46, ..., And each element is connected between the conductive portions 42 as shown in FIG.
【０００４】[0004]
【発明が解決しようとする課題】ところで従来の回路基
板には次のような問題が存在している。 （１）図１２乃至図１５のいずれの回路基板において
も、各素子を配線パターン及び導電部に半田付けによっ
て接続しているので、信頼性が低い。 （２）回路基板を製造する段階と、この製造された回路
基板に各素子を搭載する段階との２つの段階（工程）が
必要になるので、コストアップが避けられない。 （３）図１２及び図１３の回路基板では、基板３１上に
複数の各層を繰り返して形成しなければならないので、
工程が増加するためコストアップが避けられない。 （４）各素子を半田付けするランド（配線パターンまた
は導電部）のピッチに限度があるので、高密度実装が困
難となる。 （５）図１４及び図１５の回路基板では、各導電部をプ
レス加工によって形成しているので、強度的に問題があ
るため、高密度実装が困難である。The conventional circuit board has the following problems. (1) In each of the circuit boards of FIGS. 12 to 15, since each element is connected to the wiring pattern and the conductive portion by soldering, the reliability is low. (2) Since two steps (processes) of manufacturing a circuit board and mounting each element on the manufactured circuit board are required, cost increase cannot be avoided. (3) In the circuit boards of FIGS. 12 and 13, since a plurality of layers must be repeatedly formed on the board 31,
Since the number of processes is increased, cost increase cannot be avoided. (4) Since there is a limit to the pitch of the land (wiring pattern or conductive portion) to which each element is soldered, high-density mounting becomes difficult. (5) In the circuit boards of FIGS. 14 and 15, since each conductive portion is formed by press working, there is a problem in strength, so that high-density mounting is difficult.
【０００５】本発明は以上のような問題に対処してなさ
れたもので、回路基板の製造と同時に各素子を搭載して
半田付けを行わないで実装することにより、従来の各問
題を解決するようにした回路基板を提供することを目的
とするものである。The present invention has been made to solve the above problems, and solves each of the conventional problems by mounting each element at the same time as the manufacture of a circuit board without soldering. It is an object of the present invention to provide a circuit board as described above.
【０００６】[0006]
【課題を解決するための手段】上記目的を達成するため
に本発明は、絶縁基板の表面に回路パターン用溝及びこ
の回路パターン用溝に連通する素子埋め込み用凹部が形
成され、上記回路パターン用溝には導電性ペーストが充
填されると共に上記素子埋め込み用凹部には所望の素子
が搭載され、焼成によって上記導電性ペーストと上記素
子の電極とを電気的に接続してなることを特徴とするも
のである。To achieve the above object, the present invention provides a circuit pattern groove and an element-embedding recess communicating with the circuit pattern groove on the surface of an insulating substrate. The groove is filled with a conductive paste, the desired element is mounted in the recess for embedding the element, and the conductive paste and the electrode of the element are electrically connected by firing. It is a thing.
【０００７】[0007]
【作用】予め表面に回路パターン用溝及びこの回路パタ
ーン用溝に連通する素子埋め込み用凹部を形成した絶縁
基板を用意して、上記回路パターン用溝及び素子埋め込
み用凹部にそれぞれ導電性ペーストを充填すると共に所
望の素子を搭載した後に、絶縁基板を焼成することによ
って上記導電性ペーストと上記素子の電極とを接続す
る。An insulating substrate having a circuit pattern groove and an element embedding recess communicating with the circuit pattern groove is prepared in advance on the surface, and the circuit pattern groove and the element embedding recess are respectively filled with a conductive paste. After mounting the desired element, the insulating paste is fired to connect the conductive paste to the electrode of the element.
【０００８】[0008]
【実施例】以下図面を参照して本発明の実施例を説明す
る。図１は本発明の回路基板の実施例を示す斜視図で、
本実施例の回路基板１は、樹脂等の絶縁基板２の表面に
回路パターン用溝３及びこの回路パターン用溝３に連通
する素子埋め込み用凹部４が形成されて、これら回路パ
ターン用溝３には銅ペースト、銀ペースト等の導電性ペ
ーストが充填されると共に、素子埋め込み用凹部４には
所望の素子５，６，…８，９が搭載されて、この状態で
絶縁基板２の全体が焼成されることにより導電性ペース
トが回路パターン１１とされて、この回路パターン１１
と各素子５，６，…の両端の電極とが電気的に接続され
て、必要な回路が構成されている。例えば素子５に一例
をとると、この素子５の両端の電極５Ａ，５Ｂがそれぞ
れ回路パターン１１に電気的に接続されている。このよ
うに、本実施例においては回路基板の製造と同時に各素
子の実装が行われており、しかも各素子の実装に際して
半田は用いられていないことが特徴となっている。Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a perspective view showing an embodiment of a circuit board of the present invention.
In the circuit board 1 of this embodiment, a circuit pattern groove 3 and an element-embedding recess 4 communicating with the circuit pattern groove 3 are formed on the surface of an insulating substrate 2 made of resin or the like. Is filled with a conductive paste such as copper paste or silver paste, and desired elements 5, 6, ... 8, 9 are mounted in the element embedding recesses 4, and the entire insulating substrate 2 is baked in this state. By doing so, the conductive paste becomes the circuit pattern 11, and the circuit pattern 11
, And the electrodes on both ends of each element 5, 6, ... Are electrically connected to form a necessary circuit. For example, taking the element 5 as an example, the electrodes 5A and 5B on both ends of the element 5 are electrically connected to the circuit pattern 11, respectively. As described above, this embodiment is characterized in that each element is mounted at the same time as the circuit board is manufactured, and solder is not used when mounting each element.
【０００９】図２乃至図４は図１における一つの素子例
えば素子５を拡大して示す上面図、断面図及び斜視図で
ある。素子埋め込み用凹部４はこれに埋め込む素子５の
形状にほぼ合わせた形状に形成されており、素子５の形
状が方形状または円柱状であるとすると、この外周を完
全に収容可能な方形状に形成されている。また、この素
子埋め込み用凹部４の底面には直接に素子５を支持する
ための突起部４Ａと共に、この突起部４Ａの周囲部分に
低下部４Ｂが設けられている。特にこの低下部４Ｂを設
けたことにより、焼成によって導電性ペーストが回路パ
ターン１１となる際に、流動状態の導電性ペーストが素
子５の周囲部に回り込んで両端の電極５Ａと５Ｂとを短
絡するのを防止している。2 to 4 are an enlarged top view, a sectional view and a perspective view showing one element, for example, the element 5 in FIG. The recess 4 for embedding the element is formed in a shape that substantially matches the shape of the element 5 to be embedded therein. If the shape of the element 5 is a square or a column, the outer periphery is formed into a square that can be completely accommodated. Has been formed. In addition, a protrusion 4A for directly supporting the element 5 is provided on the bottom surface of the recess 4 for embedding the element, and a lower portion 4B is provided around the protrusion 4A. In particular, by providing the lowered portion 4B, when the conductive paste becomes the circuit pattern 11 by firing, the conductive paste in a flowing state wraps around the element 5 and shorts the electrodes 5A and 5B at both ends. To prevent it.
【００１０】図５は本実施例の回路基板１の製造方法を
示している。まず、工程Ａのように、予め表面に回路パ
ターン用溝３及びこの回路パターン用溝３に連通する素
子埋め込み用凹部４を形成した絶縁基板２を用意する。
次に、工程Ｂのように、回路パターン用溝３に銅ペース
ト、銀ペースト等の導電性ペースト１０を充填したり、
或いは印刷もしくは注入する。続いて、工程Ｃのよう
に、両端に電極５Ａ，５Ｂを有する素子５を素子埋め込
み用凹部４に搭載し、この後に絶縁基板２の全体を焼成
すると、導電性ペースト１０は流動状態となって素子５
の両端の電極５Ａ，５Ｂに流れ出して付着する。これに
よって、素子５の両電極５Ａ，５Ｂと導電性ペースト１
０すなわちこれによって形成された回路パターン１１と
が電気的に接続され、所望の素子５は絶縁基板２の素子
埋め込み用凹部４に埋め込まれたことになる。なお、こ
の際素子５の中間部は突起部４Ａによって安定に支持さ
れると共に、余分な導電性ペースト１０は低下部４Ｂに
流れ込むので、両電極５Ａ，５Ｂの短絡は防止される。FIG. 5 shows a method of manufacturing the circuit board 1 of this embodiment. First, as in step A, an insulating substrate 2 having a circuit pattern groove 3 and an element-embedding recess 4 communicating with the circuit pattern groove 3 formed in advance on the surface is prepared.
Next, as in step B, the circuit pattern groove 3 is filled with a conductive paste 10 such as a copper paste or a silver paste,
Alternatively, print or inject. Subsequently, as in the step C, the element 5 having the electrodes 5A and 5B on both ends is mounted in the element-embedding concave portion 4, and then the entire insulating substrate 2 is baked, so that the conductive paste 10 becomes a fluid state. Element 5
Flow out and adhere to the electrodes 5A, 5B on both ends of the. As a result, both electrodes 5A and 5B of the element 5 and the conductive paste 1
0, that is, the circuit pattern 11 formed thereby is electrically connected, and the desired element 5 is embedded in the element embedding recess 4 of the insulating substrate 2. At this time, the intermediate portion of the element 5 is stably supported by the protrusion 4A, and the excess conductive paste 10 flows into the lower portion 4B, so that a short circuit between both electrodes 5A and 5B is prevented.
【００１１】図６のＡ，Ｂ，Ｃはそれぞれ導電性ペース
ト１０を充填する回路パターン用溝３の断面構造の例を
示すもので、Ａは表面から底面の深さ方向に向かって徐
々に広がり部３Ａを設けた構造、Ｂは底面に広がり部３
Ａを設けた構造、Ｃは深さ方向の途中位置に広がり部３
Ａを設けた構造を示している。いずれの構造において
も、どこかの位置に広がり部３Ａを設けたことにより導
電性ペーストを確実に回路パターン用溝３内に充填させ
た剥離防止構造が図られている。また、図７及び図８は
素子を搭載する素子埋め込み用凹部４の例を示すもの
で、図７は幅方向に大めに設けた構造、図８は断面方向
に大めに設けた構造を示している。いずれも搭載すべき
素子の形状に応じて任意の設定が可能である。6A, 6B, 6C and 6C show examples of the sectional structure of the circuit pattern groove 3 filled with the conductive paste 10. A gradually expands from the surface toward the depth direction of the bottom surface. A structure provided with a portion 3A, B is a spread portion 3 on the bottom surface.
The structure with A is provided, and C is the expanded portion 3 at an intermediate position in the depth direction.
The structure which provided A is shown. In any of the structures, the peeling prevention structure in which the conductive paste is reliably filled in the circuit pattern groove 3 by providing the spread portion 3A at some position is achieved. 7 and 8 show an example of a recess 4 for embedding an element in which an element is mounted. FIG. 7 shows a structure provided largely in the width direction, and FIG. 8 shows a structure provided largely in the cross-sectional direction. Shows. Any of these can be set arbitrarily according to the shape of the element to be mounted.
【００１２】図９は本発明の他の実施例を示すもので、
素子埋め込み用凹部として貫通孔１３を形成し、この貫
通孔１３に裏面から素子５を搭載すると共に、表面に形
成した回路パターン１１を素子５の両電極５Ａ，５Ｂに
電気的に接続するようにした例を示すものである。貫通
孔１３への素子５の搭載は圧入や接着材等を用いて行わ
れる。FIG. 9 shows another embodiment of the present invention.
A through hole 13 is formed as a recess for embedding the element, the element 5 is mounted on the through hole 13 from the back surface, and the circuit pattern 11 formed on the front surface is electrically connected to both electrodes 5A and 5B of the element 5. The following shows an example. The element 5 is mounted on the through hole 13 by press fitting or an adhesive material.
【００１３】図１０は本発明のその他の実施例を示すも
ので、素子として両端にリード１４Ａ，１４Ｂを有する
素子１４に対して適用して、これら各リード１４Ａ，１
４Ｂに回路パターン１１を電気的に接続するようにした
例を示すものである。さらに、図１１は本発明のその他
の実施例を示すもので、先に絶縁基板２の素子埋め込み
用凹部４に素子５を搭載して、この後に絶縁基板２の表
面に導電ペーストを充填し回路パターン１１を形成する
ようにした例を示すものである。これによって、素子５
はほぼ全面が絶縁基板２に埋め込まれた状態となってい
る。FIG. 10 shows another embodiment of the present invention, which is applied to an element 14 having leads 14A and 14B at both ends as an element, and each of these leads 14A and 1B.
4B shows an example in which the circuit pattern 11 is electrically connected to 4B. Further, FIG. 11 shows another embodiment of the present invention. First, the element 5 is mounted in the recess 4 for embedding the element in the insulating substrate 2, and then the surface of the insulating substrate 2 is filled with a conductive paste to form a circuit. It shows an example in which the pattern 11 is formed. As a result, the element 5
Is almost entirely embedded in the insulating substrate 2.
【００１４】このような本発明の各実施例によれば次の
ような効果が得られる。 （１）いずれの回路基板においても、各素子を半田を用
いずに回路パターン１１に電気的に接続しているので、
信頼性が高い。 （２）回路基板の製造と同時に各素子を搭載して半田を
用いずに実装するので、コストダウンを図ることができ
る。 （３）回路基板の構造が簡素化されるので、工程が少な
くなるためコストアップが避けられる。 （４）各素子を接続するランドが不要になるので、高密
度実装が容易となり、小形化と薄形化を計ることができ
る。According to each of the embodiments of the present invention, the following effects can be obtained. (1) In each circuit board, since each element is electrically connected to the circuit pattern 11 without using solder,
Highly reliable. (2) Since each element is mounted and mounted without using solder at the same time as the circuit board is manufactured, the cost can be reduced. (3) Since the structure of the circuit board is simplified, the number of steps is reduced, and the cost increase is avoided. (4) Since lands for connecting the respective elements are unnecessary, high-density mounting becomes easy, and miniaturization and thinning can be achieved.
【００１５】[0015]
【発明の効果】以上述べたように本発明によれば、予め
表面に回路パターン用溝及びこの回路パターン用溝に連
通する素子埋め込み用凹部を形成した絶縁基板を用意し
て、上記回路パターン用溝及び素子埋め込み用凹部にそ
れぞれ導電性ペーストを充填すると共に所望の素子を搭
載した後に、絶縁基板を焼成することによって上記導電
性ペーストと上記素子の電極とを接続するようにしたの
で、回路基板の製造と同時に各素子を搭載して半田付け
を行わないで実装することができるため、信頼性を高
め、コストアップを避けると共に高密度実装を容易にす
ることができる。As described above, according to the present invention, an insulating substrate having a groove for a circuit pattern and a recess for embedding an element communicating with the groove for the circuit pattern is prepared on the surface, and the insulating substrate for the circuit pattern is prepared. Since the groove and the recess for embedding the element are respectively filled with the conductive paste and the desired element is mounted, the insulating paste is baked to connect the conductive paste and the electrode of the element to each other. Since it is possible to mount each element at the same time as manufacturing, and mount without soldering, it is possible to improve reliability, avoid cost increase, and facilitate high-density mounting.
【図１】本発明の回路基板の実施例を示す斜視図であ
る。FIG. 1 is a perspective view showing an embodiment of a circuit board of the present invention.
【図２】図１の一部を示す上面図である。FIG. 2 is a top view showing a part of FIG.
【図３】図１の一部を示す断面図である。FIG. 3 is a cross-sectional view showing a part of FIG.
【図４】図１の一部を示す斜視図である。FIG. 4 is a perspective view showing a part of FIG.
【図５】本実施例の回路基板の製造工程を示す断面図で
ある。FIG. 5 is a cross-sectional view showing the manufacturing process of the circuit board of this embodiment.
【図６】本発明の各実施例に用いられる回路パターン用
溝の例を示す断面図である。FIG. 6 is a cross-sectional view showing an example of a circuit pattern groove used in each embodiment of the present invention.
【図７】本発明の各実施例に用いられる素子埋め込み用
凹部の例を示す上面図である。FIG. 7 is a top view showing an example of a recess for embedding an element used in each embodiment of the present invention.
【図８】本発明の各実施例に用いられる素子埋め込み用
凹部の例を示す断面図である。FIG. 8 is a sectional view showing an example of a recess for embedding an element used in each embodiment of the present invention.
【図９】本発明の他の実施例を示す断面図である。FIG. 9 is a cross-sectional view showing another embodiment of the present invention.
【図１０】本発明のその他の実施例を示す断面図であ
る。FIG. 10 is a cross-sectional view showing another embodiment of the present invention.
【図１１】本発明のその他の実施例を示す断面図であ
る。FIG. 11 is a cross-sectional view showing another embodiment of the present invention.
【図１２】従来例を示す上面図である。FIG. 12 is a top view showing a conventional example.
【図１３】図１２の一部を示す断面図である。13 is a cross-sectional view showing a part of FIG.
【図１４】他の従来例を示す上面図である。FIG. 14 is a top view showing another conventional example.
【図１５】他の従来例を示す斜視図である。FIG. 15 is a perspective view showing another conventional example.
１ 回路基板 ２ 絶縁基板 ３ 回路パターン用溝 ４ 素子埋め込み用凹部 ５，６，７，１４ 素子 １０ 導電性ペースト １１ 回路パターン １３ 貫通孔 1 Circuit Board 2 Insulating Substrate 3 Circuit Pattern Groove 4 Element Embedding Recess 5,6,7,14 Element 10 Conductive Paste 11 Circuit Pattern 13 Through Hole
Claims (1)
この回路パターン用溝に連通する素子埋め込み用凹部が
形成され、上記回路パターン用溝には導電性ペーストが
充填されると共に上記素子埋め込み用凹部には所望の素
子が搭載され、焼成によって上記導電性ペーストと上記
素子の電極とを電気的に接続してなることを特徴とする
回路基板。1. A circuit pattern groove and an element embedding recess communicating with the circuit pattern groove are formed on a surface of an insulating substrate, and the circuit pattern groove is filled with a conductive paste and is used for embedding the element. A circuit board, wherein a desired element is mounted in the concave portion, and the conductive paste and the electrode of the element are electrically connected by firing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16390093A JPH06350233A (en) | 1993-06-10 | 1993-06-10 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16390093A JPH06350233A (en) | 1993-06-10 | 1993-06-10 | Circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06350233A true JPH06350233A (en) | 1994-12-22 |
Family
ID=15782960
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16390093A Pending JPH06350233A (en) | 1993-06-10 | 1993-06-10 | Circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06350233A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006027876A1 (en) * | 2004-09-03 | 2006-03-16 | Murata Manufacturing Co., Ltd. | Ceramic substrate with chip type electronic component mounted thereon and process for manufacturing the same |
| JP2006324398A (en) * | 2005-05-18 | 2006-11-30 | Ngk Spark Plug Co Ltd | Wiring board |
| JP2008211150A (en) * | 2007-02-28 | 2008-09-11 | Seiko Instruments Inc | Three-dimensional structure component and its manufacturing method |
| JP2012124452A (en) * | 2010-12-06 | 2012-06-28 | Samsung Electro-Mechanics Co Ltd | Printed substrate and manufacturing method of the same |
| CN110024120A (en) * | 2016-11-21 | 2019-07-16 | 3M创新有限公司 | Being automatically aligned between circuit die and interconnection piece |
| JP2021515983A (en) * | 2018-03-06 | 2021-06-24 | スリーエム イノベイティブ プロパティズ カンパニー | Automatic alignment between circuit dies and interconnects |
| JP2021524671A (en) * | 2018-05-21 | 2021-09-13 | スリーエム イノベイティブ プロパティズ カンパニー | Ultra-thin and flexible device including circuit die |
| JP2022021708A (en) * | 2020-07-22 | 2022-02-03 | Tdk株式会社 | Manufacturing method of resin-molded electronic component and resin-molded electronic component |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5957495A (en) * | 1982-09-27 | 1984-04-03 | シャープ株式会社 | Printed circuit board |
| JPS59154092A (en) * | 1983-02-21 | 1984-09-03 | レイモンド・イ−・ウイ−チ・ジユニア | Microcircuit and method of producing microcircuit board or the like |
-
1993
- 1993-06-10 JP JP16390093A patent/JPH06350233A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5957495A (en) * | 1982-09-27 | 1984-04-03 | シャープ株式会社 | Printed circuit board |
| JPS59154092A (en) * | 1983-02-21 | 1984-09-03 | レイモンド・イ−・ウイ−チ・ジユニア | Microcircuit and method of producing microcircuit board or the like |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006027876A1 (en) * | 2004-09-03 | 2006-03-16 | Murata Manufacturing Co., Ltd. | Ceramic substrate with chip type electronic component mounted thereon and process for manufacturing the same |
| KR100853144B1 (en) * | 2004-09-03 | 2008-08-20 | 가부시키가이샤 무라타 세이사쿠쇼 | Ceramic substrate with chip type electronic component mounted thereon and process for manufacturing the same |
| JP2006324398A (en) * | 2005-05-18 | 2006-11-30 | Ngk Spark Plug Co Ltd | Wiring board |
| JP2008211150A (en) * | 2007-02-28 | 2008-09-11 | Seiko Instruments Inc | Three-dimensional structure component and its manufacturing method |
| JP2012124452A (en) * | 2010-12-06 | 2012-06-28 | Samsung Electro-Mechanics Co Ltd | Printed substrate and manufacturing method of the same |
| JP2014027317A (en) * | 2010-12-06 | 2014-02-06 | Samsung Electro-Mechanics Co Ltd | Method of manufacturing printed circuit board |
| CN110024120A (en) * | 2016-11-21 | 2019-07-16 | 3M创新有限公司 | Being automatically aligned between circuit die and interconnection piece |
| JP2020504438A (en) * | 2016-11-21 | 2020-02-06 | スリーエム イノベイティブ プロパティズ カンパニー | Automatic alignment between circuit die and interconnect |
| JP2021515983A (en) * | 2018-03-06 | 2021-06-24 | スリーエム イノベイティブ プロパティズ カンパニー | Automatic alignment between circuit dies and interconnects |
| JP2021524671A (en) * | 2018-05-21 | 2021-09-13 | スリーエム イノベイティブ プロパティズ カンパニー | Ultra-thin and flexible device including circuit die |
| JP2022021708A (en) * | 2020-07-22 | 2022-02-03 | Tdk株式会社 | Manufacturing method of resin-molded electronic component and resin-molded electronic component |
| US12002622B2 (en) | 2020-07-22 | 2024-06-04 | Tdk Corporation | Method for producing resin mold-type electronic component and resin mold-type electronic component |
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| A02 | Decision of refusal |
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