JPH02131346U - - Google Patents

Info

Publication number
JPH02131346U
JPH02131346U JP3996889U JP3996889U JPH02131346U JP H02131346 U JPH02131346 U JP H02131346U JP 3996889 U JP3996889 U JP 3996889U JP 3996889 U JP3996889 U JP 3996889U JP H02131346 U JPH02131346 U JP H02131346U
Authority
JP
Japan
Prior art keywords
conductor pattern
semiconductor
sealed package
hermetically sealed
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3996889U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3996889U priority Critical patent/JPH02131346U/ja
Publication of JPH02131346U publication Critical patent/JPH02131346U/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16195Flat cap [not enclosing an internal cavity]

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の一実施例を示す側面図、第2
図はその一部拡大図、第3,4図は他の実施例を
示す側断面図、また第5図は公知のセラミツク・
パツケージの側断面図、第6図はその一部の拡大
断面図、第7図は第6図における−線断面図
、第8図は加圧状態を示す図である。 30,30A,B……基板、32,32A,B
……導体パターン、34……ウインドフレーム、
36,36B……ボンデイング用導体パターン、
38,50……スルーホール、40,40A,B
……外部導体パターン、44……集積回路、50
……キヤツプ。
Figure 1 is a side view showing one embodiment of the present invention;
The figure is a partially enlarged view, FIGS. 3 and 4 are side sectional views showing other embodiments, and FIG.
FIG. 6 is a side sectional view of the package, FIG. 6 is an enlarged sectional view of a part thereof, FIG. 7 is a sectional view taken along the line -- in FIG. 6, and FIG. 8 is a view showing a pressurized state. 30, 30A, B...Substrate, 32, 32A, B
...Conductor pattern, 34...Wind frame,
36, 36B... conductor pattern for bonding,
38, 50...Through hole, 40, 40A, B
...External conductor pattern, 44...Integrated circuit, 50
...cap.

Claims (1)

【実用新案登録請求の範囲】 (1) セラミツク基板に一体に設けたウインドフ
レーム内に半導体回路を固定し、このウインドフ
レームの開口を金属製キヤツプで封止した半導体
気密封止パツケージにおいて、 前記ウインドフレームの基板への取付面よりも
基板側の基板内部に導体パターンを形成し、この
導体パターンの一端を前記半導体回路に接続し、
この導体パターンの他端を外部接続端子に接続し
たことを特徴とする半導体気密封止パツケージ。 (2) 導体パターンの内端は、ウインドフレーム
内の基板上面に形成されたワイヤボンデイング用
導体パターンにスルーホールによつて接続されて
いることを特徴とする請求項(1)に記載の半導体
気密封止パツケージ。 (3) 導体パターンの他端はウインドフレーム外
の基板側面および上面に形成された外部導体パタ
ーンに接続され、この外部導体パターンに外部接
続端子が接続されていることを特徴とする請求項
(1)に記載の半導体気密封止パツケージ。 (4) 導体パターンの内端および外端はボンデイ
ング用導体パターンおよび外部導体パターンに直
接接続されていることを特徴とする請求項(1)に
記載の半導体気密封止パツケージ。
[Scope of Claim for Utility Model Registration] (1) In a semiconductor hermetically sealed package in which a semiconductor circuit is fixed within a window frame integrally provided on a ceramic substrate, and an opening of the window frame is sealed with a metal cap, the window forming a conductor pattern inside the board on the board side of the mounting surface of the frame to the board, and connecting one end of the conductor pattern to the semiconductor circuit;
A semiconductor hermetically sealed package characterized in that the other end of the conductor pattern is connected to an external connection terminal. (2) The semiconductor vaporizer according to claim (1), wherein the inner end of the conductor pattern is connected to a conductor pattern for wire bonding formed on the upper surface of the substrate in the window frame by a through hole. Sealed package. (3) A claim characterized in that the other end of the conductor pattern is connected to an external conductor pattern formed on the side surface and top surface of the board outside the wind frame, and an external connection terminal is connected to this external conductor pattern.
The semiconductor hermetically sealed package described in (1). (4) The semiconductor hermetically sealed package according to claim (1), wherein the inner and outer ends of the conductor pattern are directly connected to the bonding conductor pattern and the external conductor pattern.
JP3996889U 1989-04-06 1989-04-06 Pending JPH02131346U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3996889U JPH02131346U (en) 1989-04-06 1989-04-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3996889U JPH02131346U (en) 1989-04-06 1989-04-06

Publications (1)

Publication Number Publication Date
JPH02131346U true JPH02131346U (en) 1990-10-31

Family

ID=31549345

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3996889U Pending JPH02131346U (en) 1989-04-06 1989-04-06

Country Status (1)

Country Link
JP (1) JPH02131346U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS635238U (en) * 1986-06-25 1988-01-14

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS635238U (en) * 1986-06-25 1988-01-14

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