JPH02129955A - Packaging structure of semiconductor chip - Google Patents

Packaging structure of semiconductor chip

Info

Publication number
JPH02129955A
JPH02129955A JP28281588A JP28281588A JPH02129955A JP H02129955 A JPH02129955 A JP H02129955A JP 28281588 A JP28281588 A JP 28281588A JP 28281588 A JP28281588 A JP 28281588A JP H02129955 A JPH02129955 A JP H02129955A
Authority
JP
Japan
Prior art keywords
semiconductor chip
electrodes
chip
circuit board
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP28281588A
Other languages
Japanese (ja)
Other versions
JP2560456B2 (en
Inventor
Masaaki Ukita
昌昭 浮田
Megumi Hirooka
恵 廣岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shimadzu Corp
Original Assignee
Shimadzu Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shimadzu Corp filed Critical Shimadzu Corp
Priority to JP28281588A priority Critical patent/JP2560456B2/en
Publication of JPH02129955A publication Critical patent/JPH02129955A/en
Application granted granted Critical
Publication of JP2560456B2 publication Critical patent/JP2560456B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PURPOSE:To assure high density packaging by directly connecting electrodes of two semiconductor chips, and directly connecting a remaining electrode of the one semiconductor chip to a pad formed on the surface of a circuit board located in the vicinity of one end surface of the same. CONSTITUTION:Parts 1e-1h of an electrode group formed on one surface of a first semiconductor chip 1 are directly connected electrically and mechanically to pads 3a-3d formed on the surface of a circuit board 3 located in the vicinity of one end surface of the same. Remaining electrodes 1a-1d of the first semiconductor chip 1 project outwardly with respect to the circuit board 3 from one end surface of the same, and electrodes 2a-2d formed on a second semiconductor chip 2 are directly connected to the remaining electrodes 1a-1d electrically and mechanically. Accordingly, an interwiring distance between chips 1, 2 becomes minimum and the flexibility of a wiring position among the respective members 1, 2, 3 are increased. Hereby, packaging can be made high density.

Description

【発明の詳細な説明】 〈産業上の利用分野〉 本発明は、半導体チップの回路基板上への実装構造に関
し、特に、半導体光センサや半導体X線センサ等のチッ
プを実装するのに適した構造に関する。
[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a structure for mounting semiconductor chips on a circuit board, and in particular, a structure suitable for mounting chips such as semiconductor optical sensors and semiconductor X-ray sensors. Regarding structure.

〈従来の技術〉 一般に、ICチップ等の半導体チップを回路基板上に実
装する方法としては、チップをパッケージ内に収容して
装着する方法と、パッケージを用いずにペアチップのま
まで直接回路基板上に装着する方法があるが、実装の高
密度化の観点からはベアチップ実装の方が有利である。
<Prior art> Generally, there are two methods for mounting semiconductor chips such as IC chips on a circuit board: one is to mount the chip in a package, and the other is to mount the chip directly on the circuit board as a pair without using a package. Although there are methods for mounting on a chip, bare chip mounting is more advantageous from the viewpoint of high-density mounting.

ペアチップの実装法としては、従来、ワイヤボンディン
グ法、TAB (テープオートメイテッドボンディング
)法、フリップチップボンディング法等があり、高密度
実装化には特にフリップチップボンディング法が適して
いる。
Conventional methods for mounting paired chips include wire bonding, TAB (tape automated bonding), and flip-chip bonding, with flip-chip bonding being particularly suitable for high-density packaging.

〈発明が解決しようとする課題〉 ところで、最も高密度の実装が可能なフリップチップボ
ンディング法においても、例えば2個のICチップを基
板上に実装して、これらのチップ相互間を電気的に接続
する必要のある場合、その接続のための配線を基板上に
設ける必要があって、その配線距離を短縮化するには限
界がある。例えば、第4図に示すように、2個のICチ
ップ41と42を基板43上にそれぞれフリップチップ
ボンディング法で装着し、ICチップ41の電極41a
とICチップ42の電極32aとを相互に接続する場合
、基板43上での配線距離は最低りだけか要となる。
<Problems to be Solved by the Invention> By the way, even in the flip-chip bonding method, which allows for the highest density packaging, for example, two IC chips are mounted on a substrate and these chips are electrically connected to each other. If it is necessary to do so, it is necessary to provide wiring for the connection on the board, and there is a limit to how short the wiring distance can be. For example, as shown in FIG. 4, two IC chips 41 and 42 are mounted on a substrate 43 by flip-chip bonding, and the electrode 41a of the IC chip 41 is
When interconnecting the electrode 32a of the IC chip 42, the minimum wiring distance on the substrate 43 is required.

この配線距離が長くなると、配線容量および抵抗の増大
、クロストークの増大、素子の負荷駆動能力の減少、処
理スピードの劣化、信号減衰、ノイズの増大等、様々な
弊害が発生して問題となる。
As this wiring distance becomes longer, various problems arise, such as an increase in wiring capacitance and resistance, an increase in crosstalk, a decrease in the element's load driving ability, a deterioration in processing speed, signal attenuation, and an increase in noise. .

このような問題を解決すべく、本出願人は既に、第5図
に示すような実装構造を捷案している(特願昭62−1
16427号)。すなわち、2個の半導体チップ51と
52を、互いの電極形成面を対向させ、対応する電極間
(51aと52b、51bと52c。
In order to solve such problems, the applicant has already devised a mounting structure as shown in FIG.
No. 16427). That is, two semiconductor chips 51 and 52 are placed with their electrode forming surfaces facing each other, and the corresponding electrodes are spaced apart (51a and 52b, 51b and 52c).

51cと52d)を直接はんだ付により接続するととも
に、基板53に孔53cを穿ってこの孔53c内に一方
の半導体チップ51を収容した状態で、他方の半導体チ
ップ52の残余の電極52a、52eを基板53上のパ
ッドに直接はんだ付けによって接続する構造である。
51c and 52d) by direct soldering, a hole 53c is made in the substrate 53, and with one semiconductor chip 51 accommodated in the hole 53c, the remaining electrodes 52a and 52e of the other semiconductor chip 52 are connected. It has a structure in which it is directly connected to a pad on the substrate 53 by soldering.

この構造により、チップ51.52間の各電極は、基板
53上の配線を介することなく相互に直接接続されるこ
とになって、チップ間の配線距離は最小となるとともに
、一方のチップ51が基板53の孔53c内に嵌め込ま
れた状態でその上に他方のチップ52が実装されるので
、その実装密度についても従来のフリップチップポンデ
ィング法により有利となる。
With this structure, the electrodes between the chips 51 and 52 are directly connected to each other without going through the wiring on the substrate 53, and the wiring distance between the chips is minimized. Since the other chip 52 is mounted on the hole 53c of the substrate 53 while being fitted into the hole 53c, the mounting density is also more advantageous than the conventional flip-chip bonding method.

しかし、このような構造を、例えば半導体光検出器等に
適用する場合、第5図におけるチップ51をセンサチッ
プとし、チップ52をそのICアンプとすることになる
が、センサチップ51の両側に入射する光を検出するこ
とができず、また、このような構造のものを多数個組み
合わせて、大面積のセンサとすることはできない。つま
り、1個のセンサチップ51に形成できる素子数分の検
出器しか作れない。
However, when such a structure is applied to, for example, a semiconductor photodetector, the chip 51 in FIG. 5 is used as a sensor chip, and the chip 52 is used as its IC amplifier. Furthermore, it is not possible to combine a large number of such structures into a large-area sensor. In other words, only as many detectors as the number of elements that can be formed on one sensor chip 51 can be made.

更に、ICアンプであるチップ52としては通常Stチ
フプが用いられ、その熱伝導性は悪い。
Further, as the chip 52 which is an IC amplifier, a St chip is usually used, and its thermal conductivity is poor.

一方、センサチップ51としては各種の単体の半導体な
いしは化合物半導体が多用され、温度に対して極めて敏
感であり、第5図の構造ではその放熱に関して難点があ
る。
On the other hand, various single semiconductors or compound semiconductors are often used as the sensor chip 51, and are extremely sensitive to temperature, and the structure shown in FIG. 5 has a drawback in terms of heat dissipation.

本発明はこのような点に鑑みてなされたもので、2個の
チップ間の配線距離が最小で、しかも、光検出器やX線
検出器への適用に際してその検出面の大面積化、および
放熱対策を容易に行なうことのできる実装構造の提供を
目的としている。
The present invention has been made in view of these points, and it is possible to minimize the wiring distance between two chips, and to increase the detection surface area when applied to a photodetector or an X-ray detector. The purpose is to provide a mounting structure that allows easy heat dissipation measures.

く課題を解決するための手段〉 上記の目的を達成するための構成を、実施例に対応する
第1図を参照しつつ説明すると、本発明は、回路基板3
の一端面近傍の表面に形成されたパッド3a、3b、3
c、3dに、第1の半導体チップ1の一表面に形成され
た電極群の一部le。
Means for Solving the Problems> A configuration for achieving the above object will be described with reference to FIG. 1 corresponding to an embodiment.
Pads 3a, 3b, 3 formed on the surface near one end surface of
c, 3d, a part le of the electrode group formed on one surface of the first semiconductor chip 1;

ff、1g、lhが直接電気的および機械的に接続され
、かつ、この第1の半導体チップ1の残余の電極1a、
lb、1c、ldは回路基板3に対してその一端面より
も外方に突出し、その残余の電極1a、lb、lc、l
dに、第2の半導体チップ2に形成された電極2a、2
b、2c、2dが直接電気的および機械的に接続されて
いることによって、特徴づけられる。
ff, 1g, and lh are directly electrically and mechanically connected, and the remaining electrodes 1a of this first semiconductor chip 1,
lb, 1c, ld protrude outward from one end surface of the circuit board 3, and the remaining electrodes 1a, lb, lc, l
d, electrodes 2a, 2 formed on the second semiconductor chip 2
b, 2c, 2d are characterized by being directly electrically and mechanically connected.

なお、本明細書において、直接電気的および機械的に接
続されている、とは、その接続によって電気的に導通し
、かつ、機械的に相互に固着される状態をいい、例えば
接続すべき電極間等を直接はんだ付けもしくは導電性接
着剤等により固着することをいう。
In addition, in this specification, being directly electrically and mechanically connected refers to a state in which the connection causes electrical continuity and mechanically fixes each other; for example, the electrodes to be connected This refers to fixing the parts by direct soldering or by using conductive adhesive, etc.

く作用〉 第1と第2の半導体チップ1と2の対応する電極間1a
と2a、lbと2b、・・・等は基板3上の配線等を介
することなく、相互に直接接続され、チップ間配線距離
は最小となる。また、第2の半導体チップ2は回路基板
3の端面の側方に配設されるから、各部材L  2,3
間の配設位置の自由度が増え、例えば第2図に示すよう
に、必要に応じて冷却用パイプ10等を設けて温度制御
を行ったり、あるいは第3図に示すように、積層組み合
わせによって検出面を大面積化する等の応用が容易とな
る。
Action> Between the corresponding electrodes 1a of the first and second semiconductor chips 1 and 2
and 2a, lb and 2b, etc. are directly connected to each other without using wiring on the substrate 3, and the inter-chip wiring distance is minimized. Further, since the second semiconductor chip 2 is disposed on the side of the end surface of the circuit board 3, each member L 2, 3
For example, as shown in Fig. 2, cooling pipes 10 etc. can be installed as needed to control the temperature, or as shown in Fig. 3, by stacking the This facilitates applications such as increasing the detection surface area.

〈実施例〉 第1図は本発明実施例の側面図である。<Example> FIG. 1 is a side view of an embodiment of the present invention.

この例において、第2の半導体チップ2は、0.4mm
ピッチで4×4の16画素が形成された微小な半導体セ
ンサチップである。また、第1の半導体チップ1は、こ
のセンサチップ2の出力の信号処理を行なうためのIC
チップで、トランジスタ等を集積してアンプ等を形成し
てなるStチップである。
In this example, the second semiconductor chip 2 has a diameter of 0.4 mm.
It is a minute semiconductor sensor chip in which 16 pixels of 4×4 are formed at a pitch. The first semiconductor chip 1 also includes an IC for signal processing of the output of the sensor chip 2.
This is an St chip, which is a chip in which transistors and the like are integrated to form an amplifier and the like.

更に、回路基板3は、第1の半導体チップ1と外部回路
との接続、あるいは第1の半導体チップ1を介して出力
される検出信号をA−D変換する等の更なる信号処理を
施すためのチップやICが実装された基板である。
Further, the circuit board 3 is used to connect the first semiconductor chip 1 to an external circuit or to perform further signal processing such as A-D conversion of the detection signal outputted via the first semiconductor chip 1. This is a board on which chips and ICs are mounted.

さて、第1の半導体チップ1には、第2の半導体チップ
2と接続するための電極1a〜1dと、回路基板3に接
続するための電極1e〜1hが、それぞれ同一面上の両
サイドにまとめられて形成されている。そして、電極i
a、lb、lcおよび1dには、第2の半導体アンプ2
に形成された電極’la、2b、2cおよび2dが、そ
れぞれ直接はんだS・・・Sによって相互接続されてい
る。また、電極1e、If、Igおよび1hには、回路
基板3の一端面に近接する表面上に形成されたパッド3
a、3b、3cおよび3dに、同様にそれぞれ直接はん
だS・・・Sによって接続されている。
Now, the first semiconductor chip 1 has electrodes 1a to 1d for connecting to the second semiconductor chip 2 and electrodes 1e to 1h for connecting to the circuit board 3, respectively, on both sides on the same surface. are formed together. And electrode i
a, lb, lc and 1d, the second semiconductor amplifier 2
The electrodes 'la, 2b, 2c and 2d formed on the electrodes are directly interconnected by solder S...S, respectively. Further, the electrodes 1e, If, Ig and 1h are provided with pads 3 formed on the surface close to one end surface of the circuit board 3.
A, 3b, 3c and 3d are similarly directly connected to each other by solder S...S.

これによって第2の半導体チップ2は、第1の半導体チ
ップ1を介して回路基板3の側方に支持されることにな
る。
As a result, the second semiconductor chip 2 is supported on the side of the circuit board 3 via the first semiconductor chip 1.

以上のような構造は、次の手順によって製造することが
できる。
The structure as described above can be manufactured by the following procedure.

まず、第1の半導体チップ1の各電極1a〜1h上にそ
れぞれはんだバンプを形成した後、それぞれに第2の半
導体チップ2の各電極2a〜2dおよび回路基板3の各
パッド3a〜3dが当接するよう位置決めし、はんだを
リフローすることによって溶融・固化させる。
First, after forming solder bumps on each of the electrodes 1a to 1h of the first semiconductor chip 1, each electrode 2a to 2d of the second semiconductor chip 2 and each pad 3a to 3d of the circuit board 3 are respectively applied. Position them so that they touch each other, and reflow the solder to melt and solidify it.

あるいは、電極1a〜1d上に高融点はんだのバンプを
、電極18〜1hには低融点のはんだのバンプをそれぞ
れ形成し、まず第2の半導体チップ2の各電極2a〜2
dを電極1a〜1dに位置決めして高温リフローで接続
し、次いで回路基板3の各パッド3a〜3dを電極1e
〜1hに位置決めして低温リフローによって接続しても
よい。
Alternatively, bumps of high melting point solder are formed on the electrodes 1a to 1d and bumps of low melting point solder are formed on the electrodes 18 to 1h, respectively, and first, each of the electrodes 2a to 2 of the second semiconductor chip 2 is
d to the electrodes 1a to 1d and connected by high temperature reflow, then each pad 3a to 3d of the circuit board 3 is connected to the electrode 1e.
It is also possible to connect by low-temperature reflow after positioning at 1 h.

なお、各チップが軽量の場合には、はんだS・・・Sに
代えて導電性接着剤を使用することもできる。
Note that if each chip is lightweight, a conductive adhesive may be used instead of the solder S...S.

以上のような基本構造の本発明によると、以下に示すよ
うな応用が可能である。
According to the present invention having the basic structure as described above, the following applications are possible.

第2図に示す例は、第1の半導体アンプ1の直上に、第
2の半導体アンプ2と回路基板3間に沿って伸びる直径
1 n+程度の冷却用パイプ4を配設し、熱伝導性の良
好な接着剤5で接着している。
In the example shown in FIG. 2, a cooling pipe 4 with a diameter of about 1 n+ is arranged directly above the first semiconductor amplifier 1 and extends between the second semiconductor amplifier 2 and the circuit board 3. It is bonded with a good adhesive 5.

この冷却用パイプ4内に水等の冷媒を通すことにより、
熱源となるSi集積回路が形成された第1の半導体チッ
プ1を有効に冷却し、半導体センサチップ2に対する温
度の影響を低減することができる。
By passing a refrigerant such as water through this cooling pipe 4,
The first semiconductor chip 1 on which the Si integrated circuit serving as the heat source is formed can be effectively cooled, and the influence of temperature on the semiconductor sensor chip 2 can be reduced.

第3図に示す例は、第1図の構造のものを多数組階段状
に積層することによって、光等の被検出線Rに対して複
数個のセンサチップ2・・・2の受光面が連続的に並ぶ
ようにしたもので、大面積の面センサ装置が得られる。
In the example shown in FIG. 3, multiple sets of the structure shown in FIG. By arranging them continuously, a large-area surface sensor device can be obtained.

この例において、各回路基板3・・・3としてフィルム
状のフレキシブルプリント基板を用いると、積層厚さが
薄(なって、センサチップ2・・・2をほとんど平面状
に並べることもできる。
In this example, if a film-like flexible printed circuit board is used as each circuit board 3 . . . 3 , the laminated thickness is thin (so that the sensor chips 2 . . . 2 can be arranged almost in a plane).

〈発明の効果〉 以上説明したように、本発明によれば、2個の半導体チ
ップの電極間を直接はんだもしくは導電性接着材によっ
て接続し、かつ、一方の半導体チップの残りの電極を、
回路基板の一端面近傍の表面に形成されたパッドに直接
はんだもしくは導電性接着剤で接続したので、2個のチ
ップ間の配線距離が最小となり、配線容量がほとんどな
く、性能が向上するとともに、平面的な実装に比して高
密度実装が可能となる。
<Effects of the Invention> As explained above, according to the present invention, the electrodes of two semiconductor chips are directly connected by solder or a conductive adhesive, and the remaining electrode of one semiconductor chip is
Since it is connected directly to a pad formed on the surface near one end of the circuit board using solder or conductive adhesive, the wiring distance between the two chips is minimized, and there is almost no wiring capacitance, improving performance. Higher density mounting is possible compared to flat mounting.

しかも、回路基板の一端面の側方に半導体チップが配設
されるから、半導体センサ等への応用に際して、多数個
の組み合わせによるセンサ面積の大面積化や、冷却パイ
プの配役による温度制御等が容易となり、センサとして
の機能や性能を向上させることができる。
Moreover, since the semiconductor chip is placed on the side of one end surface of the circuit board, when applied to semiconductor sensors, it is possible to increase the sensor area by combining multiple chips, and to control temperature by placing cooling pipes. This makes it possible to improve the function and performance of the sensor.

また、センサチップ(第2の半導体チップ)にははんだ
バンブを形成せず、Siチップ(第1の半導体チップ)
側にのみはんだバンプを形成して相互接続が可能となる
ため、センサチップが化合物半導体の場合には、バンブ
形成に伴う汚染の危険がなくなる。すなわち、化合物半
導体は、はんだバンプを形成するためプロセス中のメツ
キ槽への浸漬時において、メツキ液と反応して性能劣化
をきたすことがあるが、このプロセスを省略できるわけ
である。
In addition, no solder bumps are formed on the sensor chip (second semiconductor chip), and the Si chip (first semiconductor chip)
Since interconnections can be made by forming solder bumps only on the sides, there is no risk of contamination associated with bump formation when the sensor chip is a compound semiconductor. That is, when compound semiconductors are immersed in a plating bath during the process of forming solder bumps, they may react with the plating solution and cause performance deterioration, but this process can be omitted.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明実施例の側面図、 第2図および第3図はそれぞれその応用例を示す側面図
、 第4図は従来のフリップチップボンディング法により実
装された2個の半導体チップの相互接続の説明図、 第5図は特願昭62−116427号において提案され
ている実装構造の説明図である。 1・・・第1の半導体チップ 1a〜1h・・・電極 2a〜2d 3a〜3d S・・・S
FIG. 1 is a side view of an embodiment of the present invention, FIGS. 2 and 3 are side views showing application examples thereof, and FIG. 4 is a side view of two semiconductor chips mounted by the conventional flip-chip bonding method. Explanatory Diagram of Connection FIG. 5 is an explanatory diagram of the mounting structure proposed in Japanese Patent Application No. 116427/1982. 1... First semiconductor chip 1a to 1h... Electrodes 2a to 2d 3a to 3d S...S

Claims (1)

【特許請求の範囲】[Claims]  回路基板の一端面近傍の表面に形成されたパッドに、
第1の半導体チップの一表面に形成された電極群の一部
が直接電気的および機械的に接続され、かつ、この第1
の半導体チップの残余の電極は上記回路基板に対して上
記一端面よりも外方に突出し、その残余の電極に、第2
の半導体チップに形成された電極が直接電気的および機
械的に接続されてなる、半導体チップの実装構造。
On the pad formed on the surface near one end of the circuit board,
A part of the electrode group formed on one surface of the first semiconductor chip is directly electrically and mechanically connected, and
The remaining electrodes of the semiconductor chip protrude outward from the one end surface with respect to the circuit board, and a second electrode is provided on the remaining electrodes.
A semiconductor chip mounting structure in which electrodes formed on a semiconductor chip are directly electrically and mechanically connected.
JP28281588A 1988-11-09 1988-11-09 Semiconductor chip mounting structure Expired - Fee Related JP2560456B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28281588A JP2560456B2 (en) 1988-11-09 1988-11-09 Semiconductor chip mounting structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28281588A JP2560456B2 (en) 1988-11-09 1988-11-09 Semiconductor chip mounting structure

Publications (2)

Publication Number Publication Date
JPH02129955A true JPH02129955A (en) 1990-05-18
JP2560456B2 JP2560456B2 (en) 1996-12-04

Family

ID=17657445

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28281588A Expired - Fee Related JP2560456B2 (en) 1988-11-09 1988-11-09 Semiconductor chip mounting structure

Country Status (1)

Country Link
JP (1) JP2560456B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5568361A (en) * 1992-03-17 1996-10-22 Massachusetts Institute Of Technology Three-dimensional electronic circuit of interconnected modules
US5691885A (en) * 1992-03-17 1997-11-25 Massachusetts Institute Of Technology Three-dimensional interconnect having modules with vertical top and bottom connectors
JP2001308258A (en) * 2000-04-26 2001-11-02 Sony Corp Semiconductor package and method of manufacturing it
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
JP2010283245A (en) * 2009-06-08 2010-12-16 Panasonic Corp Semiconductor device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5568361A (en) * 1992-03-17 1996-10-22 Massachusetts Institute Of Technology Three-dimensional electronic circuit of interconnected modules
US5691885A (en) * 1992-03-17 1997-11-25 Massachusetts Institute Of Technology Three-dimensional interconnect having modules with vertical top and bottom connectors
US7112468B2 (en) 1998-09-25 2006-09-26 Stmicroelectronics, Inc. Stacked multi-component integrated circuit microprocessor
JP2001308258A (en) * 2000-04-26 2001-11-02 Sony Corp Semiconductor package and method of manufacturing it
JP2010283245A (en) * 2009-06-08 2010-12-16 Panasonic Corp Semiconductor device

Also Published As

Publication number Publication date
JP2560456B2 (en) 1996-12-04

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