JP2977763B2 - Method of manufacturing an encapsulated chip-on-board electronic module - Google Patents

Method of manufacturing an encapsulated chip-on-board electronic module

Info

Publication number
JP2977763B2
JP2977763B2 JP8143072A JP14307296A JP2977763B2 JP 2977763 B2 JP2977763 B2 JP 2977763B2 JP 8143072 A JP8143072 A JP 8143072A JP 14307296 A JP14307296 A JP 14307296A JP 2977763 B2 JP2977763 B2 JP 2977763B2
Authority
JP
Japan
Prior art keywords
chip
electronic module
board
printed wiring
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP8143072A
Other languages
Japanese (ja)
Other versions
JPH09106998A (en
Inventor
ルイス・イー・ゲイツ・ジュニア
マイケル・ディー・ランヤン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Raytheon Co
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Filing date
Publication date
Application filed by Raytheon Co filed Critical Raytheon Co
Publication of JPH09106998A publication Critical patent/JPH09106998A/en
Application granted granted Critical
Publication of JP2977763B2 publication Critical patent/JP2977763B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
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    • H01L2924/013—Alloys
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    • H01L2924/161—Cap
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    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
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    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
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    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する分野】本発明は、一般に、包封されたチ
ップオンボード電子モデュール（encapsulated chip-on
-board electronic module）の分野に係り、特にはその
ような電子モデュールの製造方法に関する。The present invention relates generally to encapsulated chip-on-board electronic modules.
The invention relates to the field of board electronic modules, and in particular to the production of such electronic modules.

【０００２】[0002]

【従来の技術】高性能航空電子装置モデュールの製造に
関する従来の技術は、典型的に印刷配線板上に個々には
んだ接合される高価なハーメチック単一チップもしくは
マルチチップパッケージ（マルチチップモデュールまた
はＭＣＭとして知られている）に被包された集積回路チ
ップの使用を含む。従来の装置は、表面マウント技術
（surface mount technology）（ＳＭＴ）装置を備えた
通常の航空電子装置および金属リードフレームがはんだ
接合により印刷配線板上にマウントされたマルチチップ
パッケージを含んでいる。はんだによりマウントされた
部品は、温度の変動がはんだ界面に応力を負荷するよう
な敵対軍環境において信頼性の問題を有することが知ら
れている。また、マルチチップパッケージは、接着剤に
よりパッケージベースに接合された相互接続基板（回路
板）を含み、そのパッケージは印刷配線板に接合されて
おり、チップからヒートシンクへの熱路に対して２つの
セラミック層と２つの接着剤層を付加するものである。The prior art for the manufacture of high performance avionics modules has typically involved expensive hermetic single-chip or multi-chip packages (as multi-chip modules or MCMs) which are typically soldered individually onto printed wiring boards. (Known in the art). Conventional devices include conventional avionics devices with surface mount technology (SMT) devices and multi-chip packages in which a metal lead frame is mounted on a printed wiring board by solder bonding. It is known that components mounted by solder have reliability problems in hostile environments where temperature fluctuations place stresses on the solder interface. The multi-chip package also includes an interconnect substrate (circuit board) bonded to the package base by an adhesive, the package is bonded to a printed wiring board, and two heat paths from the chip to the heat sink. It adds a ceramic layer and two adhesive layers.

【０００３】したがって、通常の装置は、コストおよび
信頼性を増加させる、基板対パッケージおよびパッケー
ジ対印刷配線板を含む２層の相互接続、並びに４つの材
料層を含むという点で、比較的複雑である。[0003] Therefore, typical devices are relatively complex in that they include two layers of interconnects, including board-to-package and package-to-printed wiring boards, and four layers of material, which increase cost and reliability. is there.

【０００４】[0004]

【発明が解決しようとする課題】したがって、本発明の
課題は、包封されたチップオンボード電子モデュールの
製造方法を提供しようとするものである。Accordingly, it is an object of the present invention to provide a method of manufacturing an encapsulated chip-on-board electronic module.

【０００５】[0005]

【課題を解決するための手段】上記および他の課題を解
決するために、本発明は、航空電子装置または他の軍用
もしくは商業用電子システムのための環境的に強靭な電
子モデュールを製造するための安価な方法を提供する。
その最も広い観点において、本発明の方法は、包封され
たチップオンボード電子モデュールを製造するものであ
って、電気的相互接続回路を印刷した印刷配線板を提供
し、該印刷配線板に半田接合し得る（solderable）部品
（受動部品も含む）をマウントしおよび電気的に接続
し、この接合された部品をキュアさせ、該印刷配線板に
集積回路チップを直接マウントしおよびワイヤーボンド
し、このチップオンボード電子モデュールをパッシベー
ト化することによってパッシベート化チップオンボード
電子モデュールを製造し、およびこのパッシベート化チ
ップオンボード電子モデュールを包封する各工程を備え
る。パッシベート化は、集積回路チップおよびワイヤー
ボンド中に応力が誘起されないように室温に近い温度で
プラズマ増強（plasma-enhanced）化学気相堆積法を用
いて窒化ケイ素のコーティングを適用することによって
行うことができる。この窒化ケイ素コーティングは、典
型的に、１／２ミクロンのオーダーの厚さを有する。包
封されたチップオンモデュールにカバーを取り付けるこ
ともできる。SUMMARY OF THE INVENTION In order to solve the above and other problems, the present invention is directed to producing an environmentally robust electronic module for avionics or other military or commercial electronic systems. Provide an inexpensive way.
In its broadest aspect, the method of the present invention is for making an encapsulated chip-on-board electronic module, providing a printed wiring board with printed electrical interconnect circuitry, and soldering the printed wiring board to the printed wiring board. Mounting and electrically connecting solderable components (including passive components), curing the bonded components, directly mounting and wire bonding integrated circuit chips to the printed wiring board; The method includes the steps of manufacturing a passivated chip-on-board electronic module by passivating the chip-on-board electronic module, and enclosing the passivated chip-on-board electronic module. Passivation can be accomplished by applying a coating of silicon nitride using plasma-enhanced chemical vapor deposition at temperatures near room temperature so that no stress is induced during integrated circuit chips and wire bonds. it can. This silicon nitride coating typically has a thickness on the order of one-half micron. A cover can be attached to the enclosed chip-on module.

【０００６】本発明の顕著な特徴の１つは、低コスト微
細ライン相互接続印刷配線板（ＰＷＢ）上への直接チッ
プ取り付け（チップオンボード）および相互接続、並び
にはんだ接合された表面マウント技術（ＳＭＴ）のいず
れかの低コストモデュールを作製するためにもっともコ
スト効率的であるものを備えることである。本発明の他
の顕著な特徴で主な新しさは、プラズマ増強化学気相堆
積法により低温（近室温）で、完成されたチップオンボ
ード回路部品に適用された窒化ケイ素パッシベーション
を使用することである。最終の回路アッセンブリーは、
パッシベート化すなわち封止されたチップオンボードモ
デュールを形成する。[0006] One of the salient features of the present invention is direct chip mounting (chip-on-board) and interconnects on low-cost micro-line interconnect printed wiring boards (PWB), and solder-bonded surface mounting techniques ( (SMT) is to provide the most cost effective to make any low cost module. Another major feature of the present invention, a major novelty, is the use of silicon nitride passivation applied to completed chip-on-board circuit components at low temperatures (near room temperature) by plasma enhanced chemical vapor deposition. is there. The final circuit assembly is
A passivated or sealed chip-on-board module is formed.

【０００７】本発明により、ハーメチックパッケージを
まったく排除することができ、これにより重量を軽減
し、印刷配線板上のスペースを使用し尽くすパッケージ
のリードのファンアウトを除去することができる。ま
た、本発明により、集積回路チップからヒートシンクへ
の熱伝達が向上する。作製されたモデュールはこれらの
部品間での界面が少ないからである。また、本発明によ
り、はんだ接合作業を減少させまたは完全に除去するこ
とによってアッセンブリーコストが低減する。本発明で
使用される直接チップ取り付けにより、従来のパッケー
ジに使用されていた、基板対パッケージおよびパッケー
ジ対印刷配線板を含む２層の相互接続、並びに４つの材
料層が排除される。According to the present invention, the hermetic package can be eliminated altogether, thereby reducing the weight and eliminating the fanout of package leads that consumes space on the printed wiring board. Also, the present invention improves heat transfer from the integrated circuit chip to the heat sink. This is because the produced module has few interfaces between these components. The present invention also reduces assembly costs by reducing or eliminating soldering operations. The direct chip attach used in the present invention eliminates the two layers of interconnect, including board-to-package and package-to-printed wiring board, and four layers of material used in conventional packages.

【０００８】集積回路チップは、微細ライン印刷配線板
上に直接マウントされ、その上のパッドにワイヤーボン
ドされて回路相互接続を作る。直接チップ搭載が完了し
た後、集積回路チップまたはワイヤーボンドに実質的に
応力を生じさせない近室温条件下で、プラズマ増強化学
気相堆積法により窒化ケイ素のコーティングを適用す
る。この窒化ケイ素コーティングは、チップ、それらの
相互接続パッド、およびワイヤーボンドジョイントを水
分駆動イオン腐食から効果的に保護する水分バリアーを
提供する。したがって、ハーメチックパッケージの使用
は不必要である。本発明により製造された封止チップオ
ンボード電子モデュールの試験も、作製されたモデュー
ルのレベルでの試験が要求されるのみなので、簡単にな
る。[0008] Integrated circuit chips are mounted directly on fine line printed wiring boards and wire bonded to pads thereon to make circuit interconnects. After the direct chip mounting is completed, a silicon nitride coating is applied by plasma enhanced chemical vapor deposition under near room temperature conditions that do not substantially stress the integrated circuit chip or wire bonds. This silicon nitride coating provides a moisture barrier that effectively protects the chips, their interconnect pads, and wire bond joints from moisture driven ionic corrosion. Therefore, the use of a hermetic package is unnecessary. Testing of encapsulated chip-on-board electronic modules manufactured according to the present invention is also simplified, since only testing at the level of the module being manufactured is required.

【０００９】[0009]

【発明の実施の形態】以下、本発明の実施の形態を図面
を参照して説明する。図中、同様の構造要素には同様の
参照符号を付してある。Embodiments of the present invention will be described below with reference to the drawings. In the figures, similar structural elements are denoted by the same reference numerals.

【００１０】図面を参照すると、図１は、包封されたパ
ッシベート化（封止）チップオンボード電子モデュール
３０を示し、図２は本発明に従う包封チップオンボード
電子モデュール３０の製造方法１０を示すものである。
図１に示す例示モデュール３０は、例えば伝導または流
体流流通冷却（fluid flow flow-through cooling）の
いずれかを用いて冷却できるヒートシンク３１、および
ヒートシンク３１にマウントされた１またはそれ以上の
印刷配線板３２を含む。しかしながら、ヒートシンク３
１は常に必要であるものではなく、本発明にはヒートシ
ンク３１の使用は必要でないということに留意すべきで
ある。マルチ板３２の場合には印刷配線板３２を相互接
続するために、および印刷配線板３２を外部バックプレ
イン（図示せず）を介して他のモデュール３０へ相互接
続するために適切なコネクターが設けられている。Referring to the drawings, FIG. 1 shows an encapsulated, passivated (sealed) chip-on-board electronic module 30, and FIG. 2 shows a method 10 of manufacturing an encapsulated chip-on-board electronic module 30 according to the present invention. It is shown.
The example module 30 shown in FIG. 1 includes a heat sink 31 that can be cooled using, for example, either conduction or fluid flow flow-through cooling, and one or more printed wiring boards mounted on the heat sink 31. 32. However, heat sink 3
It should be noted that 1 is not always necessary and that the present invention does not require the use of a heat sink 31. In the case of a multi-board 32, suitable connectors are provided for interconnecting the printed wiring boards 32 and for interconnecting the printed wiring boards 32 to other modules 30 via an external backplane (not shown). Have been.

【００１１】集積回路チップ３３は、接着剤３４により
印刷配線板３２に接合されている。これら集積回路チッ
プ３３は、バンプ３５およびワイヤーボンド３６を用い
てワイヤーボンドされて集積回路チップ３３を印刷配線
板３２に電気的に接続する。集積回路チップ３３を含む
モデュール３０、所要により受動部品、並びにバンプ３
５およびワイヤーボンド３６は、パッシベーション層３
７によりパッシベート化されている。通常の方法によ
り、包封剤３８が、ワイヤーボンドされた集積回路チッ
プ３３上に設けられ、またはカバー３８ａが、モデュー
ルの回路部品上に配設されている。The integrated circuit chip 33 is joined to the printed wiring board 32 by an adhesive 34. These integrated circuit chips 33 are wire-bonded using bumps 35 and wire bonds 36 to electrically connect the integrated circuit chip 33 to the printed wiring board 32. Module 30, including integrated circuit chip 33, passive components as required, and bumps 3
5 and the wire bond 36 are connected to the passivation layer 3
7 are passivated. In a conventional manner, an encapsulant 38 is provided on the wire-bonded integrated circuit chip 33, or a cover 38a is provided on the circuit components of the module.

【００１２】いくつかの集積回路チップ３３がパッケー
ジされたデバイスとしてより安価に得られるか、あるい
はそれらが単に裸のチップとして得られない場合には、
集積回路チップ３３のいくつかを置き換えるモデュール
上のパッケージ化デバイスの数を制限することがコスト
的に一層好都合である。本発明の目的は、最終モデュー
ルコストを実際的に低く保つために可能な最もコスト効
率的なアプローチを用いることにある。If some integrated circuit chips 33 are available at a lower cost as packaged devices, or if they are not available simply as bare chips,
It is even more cost-effective to limit the number of packaged devices on the module that replace some of the integrated circuit chips 33. It is an object of the present invention to use the most cost-effective approach possible to keep the final module cost practically low.

【００１３】本発明の方法に従い、図２を参照すると、
印刷配線板３２は、ヒートシンク３１上にマウントさ
れ、接着剤３４によりこれに接合されて印刷配線板およ
びヒートシンクのアッセンブリー３９を形成する（工程
１１に示す）。ついで、印刷配線板３２を清浄化する
（工程１２に示す）。オシレーター等の他のはんだ接合
可能な部品、抵抗体およびコンデンサーも導電性接着剤
３４を用いてまたははんだ接合鉛によりマウントするこ
とができる（工程１３に示す）。ついで、印刷配線板３
２からフラックスを清浄化する（工程１４に示す）。次
に、抵抗体やコンデンサーのような受動素子を印刷配線
板３２に接合する（工程１５に示す）。ついで、接合さ
れた部品をキュア（cure）させる（工程１６に示す）。According to the method of the present invention, and referring to FIG.
The printed wiring board 32 is mounted on the heat sink 31 and joined thereto by an adhesive 34 to form an assembly 39 of the printed wiring board and the heat sink (shown in step 11). Next, the printed wiring board 32 is cleaned (shown in step 12). Other solderable components, such as oscillators, resistors and capacitors can also be mounted using conductive adhesive 34 or with soldered lead (shown in step 13). Then, the printed wiring board 3
2. Clean the flux from 2 (shown in step 14). Next, passive elements such as resistors and capacitors are bonded to the printed wiring board 32 (shown in step 15). The bonded parts are then cured (shown in step 16).

【００１４】しかる後、集積回路チップ接着剤を印刷配
線板３２に適用する（工程１７に示す）。ついで、集積
回路チップ３３をチップ接着剤３４を用いて印刷配線板
３２にマウントする（工程１８に示す）。次に、集積回
路チップ３３を印刷配線板３２上に印刷された電気回路
にワイヤーボンド３６を用いてワイヤーボンドする（工
程１９に示す）。以上の処理により機能性チップオンボ
ード電子モデュール３０が作製される。Thereafter, an integrated circuit chip adhesive is applied to the printed wiring board 32 (shown in step 17). Next, the integrated circuit chip 33 is mounted on the printed wiring board 32 using the chip adhesive 34 (shown in step 18). Next, the integrated circuit chip 33 is wire-bonded to the electric circuit printed on the printed wiring board 32 using the wire bond 36 (shown in the step 19). Through the above processing, the functional chip-on-board electronic module 30 is manufactured.

【００１５】しかる後、作製された機能性チップオンボ
ード電子モデュール３０を試験する（工程２０に示
す）。チップオンボード電子モデュール３０を試験した
ら、例えば米国特許第４，２６２，６３１号に記載され
ている装置および方法を用いて、これを窒化ケイ素でパ
ッシベート化してパッシベーション層３７を提供する
（工程２１に示す）。典型的に、集積回路チップ３３ま
たはワイヤーボンド３６に実質的に応力を生じさせない
近室温条件下でのプラズマ増強化学気相堆積法により、
０．５μｍの窒化ケイ素コーティングが適用される。こ
れにより、封止されたチップオンボード電子モデュール
３０が得られる。ついで、パッシベート化されたまたは
封止されたチップオンボード電子モデュール３０を包封
または被包し（図１中、包封剤層３８として示す）、あ
るいはカバー３８ａ（図１）を取り付けて、完成モデュ
ール３０を得る（工程２２に示す）。この完成モデュー
ル３０は、すぐに使用または配送できる。Thereafter, the manufactured functional chip-on-board electronic module 30 is tested (shown in step 20). Once the chip-on-board electronic module 30 has been tested, it is passivated with silicon nitride to provide a passivation layer 37 using, for example, the apparatus and method described in US Pat. No. 4,262,631 (step 21). Shown). Typically, by plasma enhanced chemical vapor deposition under near room temperature conditions that do not substantially stress the integrated circuit chip 33 or wire bonds 36,
A 0.5 μm silicon nitride coating is applied. Thereby, the sealed chip-on-board electronic module 30 is obtained. Then, the passivated or sealed chip-on-board electronic module 30 is encapsulated or encapsulated (shown as an encapsulant layer 38 in FIG. 1) or a cover 38a (FIG. 1) is attached to complete it. A module 30 is obtained (shown in step 22). This completed module 30 is ready for use or delivery.

【００１６】本発明により、はんだ接合プロセスを排除
することによってアッセンブリーコストを低減できる。
本発明に用いられる直接チップ取り付けにより、通常の
パッケージに普通に用いられている、基板対パッケージ
およびパッケージ対印刷配線板を含む２層の相互接続、
並びに４つの材料層を除去できる。かくして、本発明に
より、航空電子装置システムを非常に低コストで製造で
きると同時に、高性能で高信頼性の電子回路を提供でき
る。According to the present invention, assembly costs can be reduced by eliminating the solder joining process.
The direct chip mounting used in the present invention allows for two layers of interconnects, including board-to-package and package-to-printed wiring boards, commonly used in ordinary packages.
In addition, four layers of material can be removed. Thus, the present invention can provide an avionics system at very low cost while providing a high performance and highly reliable electronic circuit.

【００１７】本発明の実用性を実証するために、単一モ
デュール３０プロセス用部材（processing element）を
満足に作製し、試験した結果、設計通りに完全に機能す
るものであることがわかり、モデュール３０を製造する
ために必要な技術の組み合わせの有効性が証明された。In order to demonstrate the utility of the present invention, a single module 30 processing element has been satisfactorily fabricated and tested and found to be fully functional as designed. The effectiveness of the combination of techniques required to produce 30 has been proven.

【００１８】以上、包封されたチップオンボード電子モ
デュールの製造方法を説明した。上記実施の形態は、本
発明の原理の応用を示す多くの特定の形態のいくつかの
ものの単なる例示であることに留意すべきである。明ら
かに、本発明の範囲を逸脱することなく多くのおよび他
の構成が当業者にすぐに考えられるであろう。Thus, a method for making an encapsulated chip-on-board electronic module has been described. It should be noted that the above embodiments are merely illustrative of some of the many specific forms that illustrate the application of the principles of the present invention. Obviously, many and other configurations will be readily apparent to those skilled in the art without departing from the scope of the present invention.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明に従って製造された包封チップオンボー
ド電子モデュールを示す概略断面図。FIG. 1 is a schematic cross-sectional view showing an encapsulation chip-on-board electronic module manufactured according to the present invention.

【図２】本発明に従う包封チップオンボード電子モデュ
ールを製造する方法を示す流れ図。FIG. 2 is a flowchart illustrating a method of manufacturing an encapsulation chip-on-board electronic module according to the present invention.

【符号の説明】[Explanation of symbols]

３０…チップオンボードモデュール ３１…ヒートシンク ３２…印刷配線板 ３３…集積回路チップ ３４…チップ接着剤 ３６…ワイヤーボンド ３７…パッシベーション層 ３８…包封剤層 ３８ａ…カバー DESCRIPTION OF SYMBOLS 30 ... Chip on board module 31 ... Heat sink 32 ... Printed wiring board 33 ... Integrated circuit chip 34 ... Chip adhesive 36 ... Wire bond 37 ... Passivation layer 38 ... Envelope layer 38a ... Cover

───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平２−30171（ＪＰ，Ａ) 特開 昭61−51854（ＪＰ，Ａ) (58)調査した分野(Int.Cl.6，ＤＢ名) H01L 21/60 301 H01L 23/28 - 23/30 H01L 21/56 H01L 21/318 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-2-30171 (JP, A) JP-A-61-51854 (JP, A) (58) Fields investigated (Int. Cl. 6 , DB name) H01L 21/60 301 H01L 23/28-23/30 H01L 21/56 H01L 21/318

Claims (18)

(57)【特許請求の範囲】(57) [Claims] 【請求項１】 電気的相互接続回路を印刷した印刷配線
板を提供し、 該印刷配線板に受動部品を含む半田接合し得る部品をマ
ウントしおよび電気的に接続し、 この接合された部品をキュアさせ、 該印刷配線板に集積回路チップを直接マウントしおよび
ワイヤーボンドし、 このチップオンボード電子モデュールをパッシベート化
することによってパッシベート化チップオンボード電子
モデュールを製造し、およびこのパッシベート化チップ
オンボード電子モデュールを包封する工程を備えること
を特徴とする包封されたチップオンボード電子モデュー
ルの製造方法。1. A printed wiring board on which an electrical interconnect circuit is printed, a solderable component including a passive component is mounted and electrically connected to the printed wiring board, and the joined component is connected to the printed wiring board. Curing, directly mounting and wire bonding the integrated circuit chip on the printed wiring board, and manufacturing the passivated chip-on-board electronic module by passivating the chip-on-board electronic module; and A method for manufacturing an encapsulated chip-on-board electronic module, comprising a step of enclosing an electronic module. 【請求項２】 チップオンボード電子モデュールをパッ
シベート化する工程が、電子モデュールの集積回路チッ
プおよびワイヤーボンドに応力を生じさせない近室温条
件の下でプラズマ増強化学気相堆積法を用いて窒化ケイ
素のコーティングを適用する工程により特徴付けられる
請求項１記載の方法。2. The method of passivating a chip-on-board electronic module, comprising the steps of: using a plasma-enhanced chemical vapor deposition method under plasma-enhanced chemical vapor deposition under near room temperature conditions that do not cause stress on the integrated circuit chip and wire bonds of the electronic module. The method of claim 1, characterized by applying a coating. 【請求項３】 コーティングが、１／２ミクロンのオー
ダーの厚さを有する窒化ケイ素層により特徴付けられる
請求項２記載の方法。3. The method according to claim 2, wherein the coating is characterized by a silicon nitride layer having a thickness on the order of ミ ク ロ ン microns. 【請求項４】 集積回路チップをマウントしおよびワイ
ヤーボンドする工程が、 集積回路チップ接着剤を印刷配線板上の所定の集積回路
チップ部位に適用し、 該チップ接着剤を用いて集積回路チップを印刷配線板に
マウントし、および集積回路チップを印刷板上に印刷さ
れた電気的相互接続回路にワイヤーボンドする工程によ
り特徴付けられる請求項１記載の方法。4. The step of mounting and wire bonding the integrated circuit chip, applying the integrated circuit chip adhesive to a predetermined integrated circuit chip portion on the printed wiring board, and using the chip adhesive to attach the integrated circuit chip. The method of claim 1, characterized by mounting on a printed wiring board and wire bonding the integrated circuit chip to an electrical interconnect circuit printed on the printed board. 【請求項５】 パッシベート化チップオンボード電子モ
デュールを包封する工程が、ワイヤーボンドされたチッ
プを包封剤で包封する工程により特徴付けられる請求項
１記載の方法。5. The method of claim 1, wherein encapsulating the passivated chip-on-board electronic module is characterized by encapsulating the wire-bonded chip with an encapsulant. 【請求項６】 包封されたチップオンボード電子モデュ
ール上にカバーを取り付ける工程をさらに備えた請求項
１記載の方法。6. The method of claim 1, further comprising mounting a cover on the enclosed chip-on-board electronic module. 【請求項７】 電気的相互接続回路を印刷した印刷配線
板を提供し、 該印刷配線板をヒートシンクに直接マウントし、 該印刷配線板に半田接合し得る部品をマウントしおよび
導電的に接続し、 該印刷配線板に集積回路チップを直接マウントしおよび
ワイヤーボンドし、 このチップオンボード電子モデュールを、電子モデュー
ルの集積回路チップおよびワイヤーボンドに応力を生じ
させない近室温でプラズマ増強化学気相堆積法を用いて
窒化ケイ素のコーティングを適用するによって窒化ケイ
素でパッシベート化することによってパッシベート化チ
ップオンボード電子モデュールを製造し、およびこのパ
ッシベート化チップオンボード電子モデュールを包封す
る工程を備えたことを特徴とする封止されたチップオン
ボード電子モデュールの製造方法。7. A printed wiring board having an electrical interconnection circuit printed thereon, wherein the printed wiring board is directly mounted on a heat sink, and a component which can be soldered to the printed wiring board is mounted and electrically connected. An integrated circuit chip is directly mounted on the printed wiring board and wire-bonded, and the chip-on-board electronic module is plasma-enhanced chemical vapor deposition at near room temperature without causing stress on the integrated circuit chip and the wire bond of the electronic module. Manufacturing a passivated chip-on-board electronic module by passivating it with silicon nitride by applying a coating of silicon nitride using and encapsulating the passivated chip-on-board electronic module. Made of sealed chip-on-board electronic module Method. 【請求項８】 コーティングが、１／２ミクロンのオー
ダーの厚さを有する窒化ケイ素層により特徴付けられる
請求項７記載の方法。8. The method of claim 7, wherein the coating is characterized by a silicon nitride layer having a thickness on the order of １ ／ microns. 【請求項９】 集積回路チップをマウントする前に、受
動部品を印刷配線板に接合する工程、およびこの接合さ
れた部品をキュアさせる工程をさらに備えた請求項７記
載の方法。9. The method of claim 7, further comprising: before mounting the integrated circuit chip, bonding the passive components to the printed wiring board and curing the bonded components. 【請求項１０】 集積回路チップをマウントしおよびワ
イヤーボンドする工程が、 集積回路チップ接着剤を印刷配線板上の所定の集積回路
チップ部位に適用し、 該チップ接着剤を用いて集積回路チップを印刷配線板に
マウントし、および集積回路チップを印刷配線板上に印
刷された電気的相互接続回路にワイヤーボンドする工程
により特徴付けられる請求項９の記載方法。10. The step of mounting and wire bonding the integrated circuit chip, applying an integrated circuit chip adhesive to a predetermined integrated circuit chip site on the printed wiring board, and using the chip adhesive to attach the integrated circuit chip. 10. The method of claim 9, wherein the method is characterized by mounting on a printed wiring board and wire bonding the integrated circuit chip to an electrical interconnect circuit printed on the printed wiring board. 【請求項１１】 パッシベート化チップオンボード電子
モデュールを包封する工程が、ワイヤーボンドされたチ
ップを包封剤で包封する工程により特徴付けられる請求
項７記載の方法。11. The method of claim 7, wherein encapsulating the passivated chip-on-board electronic module is characterized by encapsulating the wire-bonded chip with an encapsulant. 【請求項１２】 包封されたチップオンボード電子モデ
ュール上にカバーを取り付ける工程をさらに備えた請求
項１０記載の方法。12. The method of claim 10, further comprising mounting a cover on the encapsulated chip-on-board electronic module. 【請求項１３】 電気的相互接続回路を印刷した印刷配
線板を提供し、 該印刷配線板を清浄化し、 該印刷配線板に半田接合し得る部品をマウントしおよび
導電的に接続し、 該印刷配線板からフラックスを清浄化し、 該印刷配線板に受動部品を接合し、 この接合された部品をキュアさせ、 集積回路チップ接着剤を該印刷配線板上の所定の集積回
路チップ部位に適用し、 該チップ接着剤を用いて集積回路チップを該印刷配線板
にマウントし、 該集積回路チップを該印刷配線板上の電気的相互接続回
路にワイヤーボンドして機能性チップオンボード電子モ
デュールを製造し、 このチップオンボード電子モデュールを窒化ケイ素でパ
ッシベート化することによってパッシベート化チップオ
ンボード電子モデュールを製造し、およびこのパッシベ
ート化チップオンボード電子モデュールを包封する工程
を備えたことを特徴とする包封されたチップオンボード
電子モデュールの製造方法。13. A printed wiring board on which an electrical interconnect circuit is printed, wherein the printed wiring board is cleaned, a solderable component is mounted on the printed wiring board, and the printed wiring board is conductively connected to the printed wiring board. Cleaning the flux from the wiring board, joining passive components to the printed wiring board, curing the joined components, applying an integrated circuit chip adhesive to a predetermined integrated circuit chip portion on the printed wiring board; An integrated circuit chip is mounted on the printed circuit board using the chip adhesive, and the integrated circuit chip is wire-bonded to an electrical interconnection circuit on the printed circuit board to produce a functional chip-on-board electronic module. Manufacturing the passivated chip-on-board electronic module by passivating the chip-on-board electronic module with silicon nitride; and A method for manufacturing an enclosed chip-on-board electronic module, comprising a step of enclosing a chip-on-board electronic module. 【請求項１４】 印刷配線板をヒートシンクに直接マウ
ントし接合する工程をさらに備えた請求項１３記載の方
法。14. The method of claim 13, further comprising the step of directly mounting and joining the printed wiring board to the heat sink. 【請求項１５】 チップオンボード電子モデュールをパ
ッシベート化する工程が、電子モデュールの集積回路チ
ップまたはワイヤーボンドに応力を生じさせない近室温
条件の下でプラズマ増強化学気相堆積法を用いて窒化ケ
イ素のコーティングを適用する工程により特徴付けられ
る請求項１３記載の方法。15. The method of passivating a chip-on-board electronic module, wherein the step of passivating the silicon nitride using plasma-enhanced chemical vapor deposition under near room temperature conditions that does not cause stress on the integrated circuit chip or wire bonds of the electronic module. 14. The method according to claim 13, characterized by applying a coating. 【請求項１６】 コーティングが、１／２ミクロンのオ
ーダーの厚さを有する窒化ケイ素層により特徴付けられ
る請求項１３記載の方法。16. The method according to claim 13, wherein the coating is characterized by a silicon nitride layer having a thickness on the order of ミ ク ロ ン microns. 【請求項１７】 パッシベート化チップオンボード電子
モデュールを包封する工程が、パッシベート化チップオ
ンボード電子モデュールにカバーを取り付ける工程によ
り特徴付けられる請求項１３記載の方法。17. The method of claim 13, wherein encapsulating the passivated chip-on-board electronic module is characterized by attaching a cover to the passivated chip-on-board electronic module. 【請求項１８】 パッシベート化する前に、チップオン
ボード電子モデュールを試験する工程をさらに備えた請
求項１３記載の方法。18. The method of claim 13, further comprising testing the chip-on-board electronic module before passivating.
JP8143072A 1995-06-05 1996-06-05 Method of manufacturing an encapsulated chip-on-board electronic module Expired - Fee Related JP2977763B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US461081 1995-06-05
US08/461,081 US5685071A (en) 1995-06-05 1995-06-05 Method of constructing a sealed chip-on-board electronic module

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JPH09106998A JPH09106998A (en) 1997-04-22
JP2977763B2 true JP2977763B2 (en) 1999-11-15

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EP0747951A2 (en) 1996-12-11
IL118448A0 (en) 1996-09-12
IL118448A (en) 1999-12-22
EP0747951A3 (en) 1998-12-16
US5685071A (en) 1997-11-11
JPH09106998A (en) 1997-04-22

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