JPH02128422A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02128422A
JPH02128422A JP28169488A JP28169488A JPH02128422A JP H02128422 A JPH02128422 A JP H02128422A JP 28169488 A JP28169488 A JP 28169488A JP 28169488 A JP28169488 A JP 28169488A JP H02128422 A JPH02128422 A JP H02128422A
Authority
JP
Japan
Prior art keywords
etching
flow rate
film
hbr
si3n4
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28169488A
Other languages
Japanese (ja)
Inventor
Tsutomu Saito
勉 齋藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP28169488A priority Critical patent/JPH02128422A/en
Publication of JPH02128422A publication Critical patent/JPH02128422A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To specify the etching ratio of Si3N4 at around 10 for selectively etch away Si3N4 by a method wherein the flow rate of HBr is selected not to exceed the flow rate of SF6 and then RIE process is performed using the mixed gas of SF6 and HBr. CONSTITUTION:The flow rate of HBr is selected not to exceed 50% pf the flow rate of SF6 and then the mixed gas of SF6 and HBr is led into a reaction chamber to perform RIE process at specified vacuum degree and voltage density. In such a constitution, the selection ratio (b) of Si3N4/SiO2 can be specified at 10. Consequently, when the film thickness of SiO2 is around 80Angstrom in LOCOS process, even slightly over-etching process shall not damage an Si substrate thereby improving the etching precision and etching efficiency.

Description

【発明の詳細な説明】 〔概 要〕 ドライエツチング法のうち、酸化シリコン膜上の窒化シ
リコン膜のエツチングに適した方法に関し、 Sl 3N a / Si O2のエツチング選択比が
大きく、Sj、N4膜のエツチングレートも大きくする
ことを目的とし、 臭化水素の流量を六弗化硫黄の流量の50%以下にした
六弗化硫黄と臭化水素とからなる混合ガスによって反応
性イオンエツチングをおこなって、窒化シリコン膜をエ
ツチングすることを特徴とする。
[Detailed Description of the Invention] [Summary] Among dry etching methods, this method is suitable for etching a silicon nitride film on a silicon oxide film, and has a high etching selectivity of Sl 3N a /Si O 2 and is suitable for etching a silicon nitride film on a silicon oxide film. With the aim of increasing the etching rate, reactive ion etching was performed using a mixed gas of sulfur hexafluoride and hydrogen bromide, with the flow rate of hydrogen bromide being 50% or less of the flow rate of sulfur hexafluoride. , which is characterized by etching a silicon nitride film.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体装置の製造方法のうち、ドライエツチン
グ法にかかり、特に酸化シリコン膜上の窒化シリコン膜
のエツチングに通したエツチング方法に関する。
The present invention relates to a dry etching method among semiconductor device manufacturing methods, and particularly to an etching method that involves etching a silicon nitride film on a silicon oxide film.

半導体装置の製造方法においては、従前からのウェット
エツチング法に代わって高精度にパターン形成の可能な
ドライエツチング法が汎用されている。しかし、ドライ
エツチングではエツチング選択比の大きいことが重要で
、本発明は酸化シリコン(SiOz)に対する窒化シリ
コン(Si3Na)のエツチング選択比の大きいドライ
エツチング法に関している。
In semiconductor device manufacturing methods, dry etching methods, which can form patterns with high precision, have been widely used in place of conventional wet etching methods. However, in dry etching, it is important to have a high etching selectivity, and the present invention relates to a dry etching method that has a high etching selectivity of silicon nitride (Si3Na) to silicon oxide (SiOz).

〔従来の技術〕[Conventional technology]

例えば、LOCO3法によってフィールド絶縁膜を形成
する工程ではSi3N4膜を酸化防止膜として用いてお
り、第3図(al、 (b)はそのフィールド絶縁膜の
形成工程順図で、同時に従来の問題点を説明する図であ
る。工程の概要を説明すると、第3図(alに示すよう
に、シリコン基板1上に5iOz膜2を介してsL N
、膜3を被着し、そのSi3N4膜3をパターンニング
してフィールド絶縁膜形成領域上の5iaN4膜を除去
する。なお、ここに介在しているSiO□膜2は5i3
Na膜がシリコン基板1にストレスを与えないようにす
るための緩衝膜の役目をする膜である。次いで、第3図
(blに示すように、1000℃以上の高温度において
酸化処理してSin、膜からなるフィールド絶縁膜4を
形成する。しかる後、543N、膜3をエツチング除去
して、除去部分に半導体素子を形成する。
For example, in the process of forming a field insulating film using the LOCO3 method, a Si3N4 film is used as an oxidation prevention film. To explain the outline of the process, as shown in FIG.
, a film 3 is deposited, and the Si3N4 film 3 is patterned to remove the 5iaN4 film on the field insulation film forming region. Note that the SiO□ film 2 interposed here is 5i3
The Na film serves as a buffer film to prevent stress from being applied to the silicon substrate 1. Next, as shown in FIG. 3 (bl), a field insulating film 4 made of a Si film is formed by oxidation treatment at a high temperature of 1000° C. or higher.Then, the 543N film 3 is etched and removed. A semiconductor element is formed in the portion.

ところが、このようなLOCO3法によるフィールド絶
縁膜の形成方法において、Si3N4膜のパターンニン
グは従前には熱燐酸を用いたウェットエツチングをおこ
なっていたが、ウェットエツチングではサイドエツチン
グが進行して精度良く形成することが難しいために、最
近では一層高精度パターンニングの可能なドライエツチ
ング法が用いられており、これは半導体素子形成領域を
微細に精度良く形成できるからである。且つ、フィール
ド絶縁膜の形成には周縁部分のバーズビーク(第3図f
b)に矢印で示す)が問題で、バーズビーク部分を出来
るだけ小さくすることが微細化、高精度化のために重要
であって、それには緩衝膜である5iCh膜2を薄く 
(例えば、200Å以下)形成することも必要な条件に
なる。
However, in this method of forming a field insulating film using the LOCO3 method, patterning of the Si3N4 film was conventionally performed by wet etching using hot phosphoric acid, but with wet etching, side etching progresses and it is not possible to form the Si3N4 film accurately. Since it is difficult to do this, recently a dry etching method has been used which allows for even higher precision patterning, and this is because the semiconductor element formation region can be formed finely and accurately. In addition, for the formation of the field insulating film, a bird's beak (see Fig. 3
The problem is that the bird's beak (indicated by the arrow in b)) is important for miniaturization and high precision to make the bird's beak part as small as possible.
(For example, 200 Å or less) is also a necessary condition.

しかし、SiO□膜2を薄く形成すると、第3図(a)
で説明した5i3Na膜3のパターンニングの際に、5
i02膜2に対するSi3N4膜3のエツチング選択比
を充分に大きくしなければ5iOz膜2がエツチングさ
れ、さらに下層のシリコン基板1にエツチングダメージ
を与える心配がある。
However, if the SiO□ film 2 is formed thinly, as shown in Fig. 3(a).
When patterning the 5i3Na film 3 explained in
If the etching selection ratio of the Si3N4 film 3 to the i02 film 2 is not made sufficiently large, the 5iOz film 2 will be etched, and there is a fear that further etching damage will be caused to the underlying silicon substrate 1.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

ところで、このようなSi3N4膜のドライエラチング
にはエツチングの方向性をもった反応性イオンエツチン
グ(RI E ; Reactive Ion Ech
ing)法を使用しており、その反応ガスとしては四弗
化炭素(CF4)または三弗化炭素(NF3)またはそ
れらの反応ガスに酸素(0□)を混合した混合ガスが従
来から用いられている。しかし、これらのガスは5iO
zに対する5i3Na  (Si:+ N4/5fOz
)のエツチング選択比が端々3程り、膜厚200Å以下
の薄いSiO□膜はエツチング除去される恐れがある。
By the way, reactive ion etching (RIE) with directional etching is used for dry etching of such Si3N4 films.
Conventionally, carbon tetrafluoride (CF4), carbon trifluoride (NF3), or a mixed gas containing oxygen (0□) is used as the reaction gas. ing. However, these gases are 5iO
5i3Na (Si: + N4/5fOz
) has an etching selectivity of about 3, and there is a risk that a thin SiO□ film with a thickness of 200 Å or less will be etched away.

また、弗化メタン(CH.F)または二弗化メタン(C
H2F2)を反応ガスとすると高い選択比をもったエツ
チングが得られるという報告もあるが、炭素(C)が含
まれているために炭素がエツチング面に残存し易い問題
があり、且つ、所望のガス圧の許容範囲が狭くて、安定
性に乏しい欠点がある。
Also, methane fluoride (CH.F) or methane difluoride (C.
There are reports that etching with a high selectivity can be obtained when H2F2) is used as the reaction gas, but since it contains carbon (C), there is a problem that carbon tends to remain on the etched surface, and the desired The disadvantage is that the gas pressure tolerance range is narrow and stability is poor.

本発明はこのような問題点を解消させて、Si3N a
 / S iO□のエツチング選択比が大きく、且つ、
Si3N.膜のエツチングレートを大きくすることを目
的としたドライエツチング法を提供するものである。
The present invention solves these problems and makes Si3N a
/ SiO□ has a large etching selectivity ratio, and
Si3N. This invention provides a dry etching method aimed at increasing the etching rate of a film.

〔課題を解決するための手段〕[Means to solve the problem]

その課題は、臭化水素(HBr)の流量を六弗化硫黄(
SF6)の流量の50%以下にした六弗化硫黄(SF6
)と臭化水素(Illlr)とからなる混合ガスによっ
て反応性イオンエツチングをおこなって、窒化シリコン
膜をエツチングするドライエツチング法によって解決さ
れる。
The challenge is to reduce the flow rate of hydrogen bromide (HBr) to sulfur hexafluoride (
The flow rate of sulfur hexafluoride (SF6) was reduced to 50% or less of the flow rate of sulfur hexafluoride (SF6).
) and hydrogen bromide (Illr) to perform reactive ion etching to etch the silicon nitride film.

〔作 用〕[For production]

流量H Br/ S F b + H Br < 50
%とした反応ガスを用いて反応性イオンエツチングをお
こなうと、Si3N a / St O zのエツチン
グ選択比は10程度になり、且つ、Si+Na膜のエツ
チングレートが1100n 7分になって、上記したL
OCO3法におけるような問題点を解消させることがで
きる。
Flow rate H Br/ S F b + H Br < 50
When reactive ion etching is performed using a reactive gas of
Problems such as those in the OCO3 method can be solved.

〔実 施 例〕 以下、図面を参照して実施例によって詳細に説明する。〔Example〕 Hereinafter, embodiments will be described in detail with reference to the drawings.

第1図は本発明を適用するドライエツチング装置の要部
概要図を示しており、11は石英製の反応チャンバ、1
2は被エツチング材料のウェハー、13は周波数13.
56MH2の高周波電源、14はステージ。
FIG. 1 shows a schematic diagram of the main parts of a dry etching apparatus to which the present invention is applied, in which 11 is a reaction chamber made of quartz;
2 is a wafer of material to be etched, 13 is a frequency 13.
56MH2 high frequency power supply, 14 is stage.

15はガス噴射ノズル、16はガス流入口、17は排気
口である。
15 is a gas injection nozzle, 16 is a gas inlet, and 17 is an exhaust port.

次に、第2図はエツチング特性図を示しており、横軸は
HBr/ S F b + HBr流量比(%)、左縦
軸はエラチングレー) (nm/分)、右縦軸は5i3
N−/5i()zのエツチング選択比で、図中の−・は
si、 N4膜のエツチングレート曲線、−〇−はSi
O□膜のエツチングレート曲線、−△−はSi3N4 
/Si○2のエツチング選択比の曲線である。
Next, Fig. 2 shows an etching characteristic diagram, where the horizontal axis is HBr/S F b + HBr flow rate ratio (%), the left vertical axis is the etching gray (nm/min), and the right vertical axis is 5i3
Etching selectivity ratio of N-/5i()z, - in the figure is Si, N4 film etching rate curve, -0- is Si
Etching rate curve of O□ film, -△- is Si3N4
This is a curve of etching selectivity of /Si○2.

この特性図はS F b 十HBr流量25 SCCM
、  圧力0゜2Toor、  電力密度0.4W/c
d の条件下で得たものであるが、この図表よりHBr
/ S F b + HBr流量比が20%になるよう
にSFb流量20 SCCM、 HBr流量5 SCC
Mにして、圧力、電力密度を上記の条件にすれば、Si
3N a / Si O2のエツチング選択比が10に
なり、5isN4膜のエツチングレートが1100n/
分になり、且つ、同図より流量HBr/SF6 +HB
r<50%とすればSi3N4 /5iOzのエツチン
グ選択比およびS+3Na膜のエツチングレートを共に
大きくできることが明らかである。
This characteristic diagram is S F b 1 HBr flow rate 25 SCCM
, Pressure 0゜2Toor, Power density 0.4W/c
d, but from this diagram, HBr
/ SFb flow rate 20 SCCM, HBr flow rate 5 SCC so that the SF b + HBr flow rate ratio is 20%
If the pressure and power density are set to the above conditions, Si
The etching selectivity ratio of 3N a/SiO2 is 10, and the etching rate of the 5isN4 film is 1100n/
minutes, and from the same figure, the flow rate HBr/SF6 +HB
It is clear that if r<50%, both the etching selectivity of Si3N4/5iOz and the etching rate of the S+3Na film can be increased.

このように、HBrのみではエツチングされないが、S
F6にHBrを添加すれば5i02に対して高選択比で
、エツチングレートの高いSi3 N4膜の反応性イオ
ンエツチングをおこなうことができて、このエツチング
法を適用すればエツチングレートが1000人/分とな
り、Sia Na /5in2のエツチング選択比が8
以上になることを考えると、上記のLOCO3法におい
てはSin、膜は膜厚が80人程度あれば多少のオーバ
エツチングをおこなってもシリコン基板にダメージを与
える問題は発生しない。
In this way, HBr alone does not etch, but S
By adding HBr to F6, it is possible to perform reactive ion etching of a Si3N4 film with a high selectivity to 5i02 and a high etching rate.If this etching method is applied, the etching rate can be 1000 people/min. , the etching selection ratio of Sia Na /5in2 is 8
Considering the above, in the above-mentioned LOCO3 method, if the thickness of the Sin film is about 80 mm, even if some overetching is performed, the problem of damaging the silicon substrate will not occur.

かくして、この反応性イオンエツチング方法を用いれば
エツチング効率も良く、エツチング精度も向上させるこ
とができる。
Thus, if this reactive ion etching method is used, the etching efficiency can be improved and the etching accuracy can also be improved.

なお、上記例はLOCO3法によって説明したが、半導
体装置の製造方法における他の5i3Nn膜を用いる形
成工程にも、本発明を適用できることはいうまでもない
Although the above example has been explained using the LOCO3 method, it goes without saying that the present invention can be applied to other forming steps using 5i3Nn films in semiconductor device manufacturing methods.

〔発明の効果〕〔Effect of the invention〕

以上の説明から明らかなように本発明によれば半導体装
置の製造方法におけるエツチング精度とエツチング効率
が改善できて、ICなど半導体装置の高性能化・高品質
化に役立ち、スループットの向上にも寄与するものであ
る。
As is clear from the above description, according to the present invention, etching accuracy and etching efficiency in a semiconductor device manufacturing method can be improved, which is useful for improving the performance and quality of semiconductor devices such as ICs, and also contributing to improved throughput. It is something to do.

【図面の簡単な説明】 第1図は本発明を適用するドライエツチング装置の要部
断面図、 第2図はエツチング特性図、 第3図(a)、 (b)は従来の問題点を説明する図で
ある。 図において、 1はシリコン基板、   2は5iOz膜、3はSi3
Ng膜、 11は反応チャンバ、 13は高周波電源、 15はガス噴射ノズル、 17は排気口 を示している。 4はフィールド絶縁膜、 12はウェハー 14はステージ、 16はガス流入口、
[Brief Description of the Drawings] Figure 1 is a cross-sectional view of the main part of a dry etching apparatus to which the present invention is applied, Figure 2 is an etching characteristic diagram, and Figures 3 (a) and (b) explain the problems of the conventional method. This is a diagram. In the figure, 1 is a silicon substrate, 2 is a 5iOz film, and 3 is a Si3
11 is a reaction chamber, 13 is a high frequency power source, 15 is a gas injection nozzle, and 17 is an exhaust port. 4 is a field insulating film, 12 is a wafer 14 is a stage, 16 is a gas inlet,

Claims (1)

【特許請求の範囲】[Claims] 臭化水素の流量を六弗化硫黄の流量の50%以下にした
六弗化硫黄と臭化水素とからなる混合ガスによつて反応
性イオンエッチングをおこなつて、窒化シリコン膜をエ
ッチングすることを特徴とする半導体装置の製造方法。
Etching the silicon nitride film by performing reactive ion etching with a mixed gas of sulfur hexafluoride and hydrogen bromide in which the flow rate of hydrogen bromide is 50% or less of the flow rate of sulfur hexafluoride. A method for manufacturing a semiconductor device, characterized by:
JP28169488A 1988-11-07 1988-11-07 Manufacture of semiconductor device Pending JPH02128422A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28169488A JPH02128422A (en) 1988-11-07 1988-11-07 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28169488A JPH02128422A (en) 1988-11-07 1988-11-07 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02128422A true JPH02128422A (en) 1990-05-16

Family

ID=17642681

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28169488A Pending JPH02128422A (en) 1988-11-07 1988-11-07 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02128422A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0722384A (en) * 1993-06-24 1995-01-24 Nec Corp Manufacture of semiconductor device
EP0744767A2 (en) * 1995-05-24 1996-11-27 Nec Corporation Process of etching silicon nitride layer by using etching gas containing sulfur hexafluoride, hydrogen bromide and oxygen

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0722384A (en) * 1993-06-24 1995-01-24 Nec Corp Manufacture of semiconductor device
EP0744767A2 (en) * 1995-05-24 1996-11-27 Nec Corporation Process of etching silicon nitride layer by using etching gas containing sulfur hexafluoride, hydrogen bromide and oxygen
EP0744767A3 (en) * 1995-05-24 1998-03-11 Nec Corporation Process of etching silicon nitride layer by using etching gas containing sulfur hexafluoride, hydrogen bromide and oxygen

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