JPH02127065U - - Google Patents
Info
- Publication number
- JPH02127065U JPH02127065U JP3672189U JP3672189U JPH02127065U JP H02127065 U JPH02127065 U JP H02127065U JP 3672189 U JP3672189 U JP 3672189U JP 3672189 U JP3672189 U JP 3672189U JP H02127065 U JPH02127065 U JP H02127065U
- Authority
- JP
- Japan
- Prior art keywords
- flat package
- terminal portions
- lead wires
- wiring board
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structure Of Printed Boards (AREA)
Description
第１図は本考案の第１の実施例の平面図、第２
図は本考案の第２の実施例の平面図、第３図は本
考案の第３の実施例の平面図、第４図は従来の一
例の平面図及び断面図、第５図はフラツトパツケ
ージ集積回路の平面図及び正面図である。
１…基板、２…ターミナル部、３ａ〜３ｄ…ス
テパターン、４ａ〜４ｃ…配線部、６…パツケー
ジ、７，７ａ，７ｂ…リード線。
Figure 1 is a plan view of the first embodiment of the present invention;
The figure is a plan view of the second embodiment of the present invention, Fig. 3 is a plan view of the third embodiment of the present invention, Fig. 4 is a plan view and sectional view of a conventional example, and Fig. 5 is a flat view. FIG. 2 is a plan view and a front view of a packaged integrated circuit. DESCRIPTION OF SYMBOLS 1... Board, 2... Terminal part, 3a-3d... Step pattern, 4a-4c... Wiring part, 6... Package, 7, 7a, 7b... Lead wire.
Claims (1)
リード線を該複数のリード線に対応して設けられ
た複数のターミナル部と接続することにより該フ
ラツトパツケージ内に収納された集積回路を表面
実装するプリント配線基板において、 前記複数のターミナル部のうちの所定のターミ
ナル部と前記複数のターミナル部の外側に設けら
れた他の配線導体とを前記フラツトパツケージの
下側を通つて、接続する配線部を具備してなるプ
リント配線基板。[Claims for Utility Model Registration] A plurality of lead wires extending in parallel from a flat package are connected to a plurality of terminal portions provided corresponding to the plurality of lead wires to be housed in the flat package. In a printed wiring board on which a surface-mounted integrated circuit is mounted, a predetermined terminal portion of the plurality of terminal portions and another wiring conductor provided outside the plurality of terminal portions are connected to the lower side of the flat package. A printed wiring board comprising a wiring section to be connected through.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3672189U JPH02127065U (en) | 1989-03-30 | 1989-03-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3672189U JPH02127065U (en) | 1989-03-30 | 1989-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02127065U true JPH02127065U (en) | 1990-10-19 |
Family
ID=31543199
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3672189U Pending JPH02127065U (en) | 1989-03-30 | 1989-03-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02127065U (en) |
-
1989
- 1989-03-30 JP JP3672189U patent/JPH02127065U/ja active Pending