JPH0212668U - - Google Patents
Info
- Publication number
- JPH0212668U JPH0212668U JP9069588U JP9069588U JPH0212668U JP H0212668 U JPH0212668 U JP H0212668U JP 9069588 U JP9069588 U JP 9069588U JP 9069588 U JP9069588 U JP 9069588U JP H0212668 U JPH0212668 U JP H0212668U
- Authority
- JP
- Japan
- Prior art keywords
- level
- voltage
- reference voltage
- measured voltage
- displays
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Measurement Of Current Or Voltage (AREA)
Description
第1図は本考案の回路図の一部、第2図は本考
案を使用したロジツクアナライザのCRT表示例
である。
1……プローブ、2……aコンパレータ、3…
…a基準電圧、4……a出力、5……bコンパレ
ータ、6……b基準電圧、7……b出力、8……
ロウレベル部、9……ハイレベル部、10……ロ
ウレベル部、11……不定部。
FIG. 1 is a part of a circuit diagram of the present invention, and FIG. 2 is an example of a CRT display of a logic analyzer using the present invention. 1...probe, 2...a comparator, 3...
...a reference voltage, 4...a output, 5...b comparator, 6...b reference voltage, 7...b output, 8...
Low level part, 9...High level part, 10...Low level part, 11...Undefined part.
Claims (1)
場合第1のレベル、それ以下の場合第2のレベル
を表示するロジツクアナライザにおいて、同時に
複数の基準電圧を設定できることを特徴とするロ
ジツクアナライザ。 A logic analyzer that sets a certain reference voltage and displays a first level when the measured voltage is higher than the reference voltage, and a second level when the measured voltage is lower, characterized in that a plurality of reference voltages can be set at the same time. .
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9069588U JPH0212668U (en) | 1988-07-08 | 1988-07-08 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9069588U JPH0212668U (en) | 1988-07-08 | 1988-07-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0212668U true JPH0212668U (en) | 1990-01-26 |
Family
ID=31315208
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9069588U Pending JPH0212668U (en) | 1988-07-08 | 1988-07-08 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0212668U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07181204A (en) * | 1993-10-12 | 1995-07-21 | Tektronix Inc | Logic-signal display method |
-
1988
- 1988-07-08 JP JP9069588U patent/JPH0212668U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07181204A (en) * | 1993-10-12 | 1995-07-21 | Tektronix Inc | Logic-signal display method |
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