JPH02126681A - Manufacture of mos type semiconductor element - Google Patents

Abstract

PURPOSE:To obtain a LDD structure of good reproducibility by a simplified process by a method wherein a recess formed in the surface of a semiconductor substrate by removing an oxide film region simultaneously with a field oxide film is used as a channel region, the recess is filled with a material for gate electrode use, and a flat gate electrode is formed on the surface of the semiconductor substrate. CONSTITUTION:A removed part of an oxide film 8 which is formed simultaneously in the middle in addition to two field oxide film regions 3 becomes a hollow used to fill a gate electrode 4; when an impurity region is formed in a self- alignment manner by making use of the field oxide film regions 3 and the gate electrode 4 as a mask, a low impurity-concentration source-drain region 71 having a concentration grade is generated under slopes on both ends of the gate electrode 4; this region forms an LDD structure together with a high impurity-concentration source-drain region 72 generated under parts not covered with the gate electrode 4. Accordingly, it is not required to form a side wall; its reproducibility is good.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a MOS type semiconductor element having a structure called an LDD structure in which source/drain regions are composed of a low impurity concentration region and a high impurity concentration region.

[Conventional technology]

In recent years, the dimensions of transistors have become smaller and smaller with the aim of increasing the speed and integration of semiconductor devices. Especially M
In an OS type semiconductor device, the gate channel length is 1i
rm, and problems caused by the so-called short channel effect, such as a sudden drop in threshold voltage, are becoming more prominent. In addition, deterioration of device characteristics due to impact ionization in the drain region is also a problem, and in order to avoid these problems, the concentration of the drain junction is set in two stages, and the LDD (L)
tghLy doped drain) structure has been devised. Conventionally, the method of making this LDDI structure is as shown in Fig. 2 [a
As shown in l~(dl, sidewalls formed by CVD were used. In other words, the second
As shown in Figure (a), after forming a gate oxide film 2 and a field oxide film 3 on a silicon substrate 1, a gate electrode 4 is formed on the gate oxide film 2, and a low concentration layer is formed to form a low concentration drain region. Dose ion implantation 51 is performed by self-alignment using the gate electrode 4 and field oxide film 3 as masks.Next, as shown in Figure (bl), the ion-implanted region is defined as a low impurity concentration region, and the oxide film is formed by low pressure CVD. 60 is deposited on the entire surface.Then, as shown in Figure tc+, the oxide film is etched on the entire surface using a reactive ion etching (RIE) method.Since the RIE method is anisotropic etching, ! Since the etching rate of the oxide film on the wall is low, even if the oxide film on the plane parallel to the surface is etched, the side wall portion remains and a so-called sidewall 6 is formed. When the high-dose ion population 52 is performed to form a high impurity concentration region with the sidewall 6 formed, the high concentration source/drain region 7 is started from a portion far away from the gate electrode, as shown in FIG. td+.
2 can be formed. After that, PSG film 1 is used as the glabella insulating film.
Deposit 0. Through these steps, a low concentration source/drain region 71 in contact with the channel formation region and a high concentration source/drain region 72 necessary for contact with the electrode can be formed in self-alignment with the gate electrode.

[Problem to be solved by the invention]

However, the method described in Figure 2
The formation of the sidewall 6 that forms the drain region is performed by RI.
Since delicate etching by the E method must be used, reproducibility is poor, and the process is long and complicated, resulting in an increase in manufacturing costs.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a MOS type semiconductor device that solves the above problems and can form a reproducible LDD structure with a small number of steps.

[Means to solve the problem]

In order to solve the above problems, the method of the present invention selectively oxidizes the surface layer of a semiconductor substrate to provide an oxide film region between two field oxide film regions whose ends are thinned by sloped surfaces. The oxide film is removed only in the middle region to form a depression, and a gate electrode is provided to fill the depression with a flat surface.
Using the remaining field oxide film and gate electrode as masks, ions are implanted to form source/drain regions with low impurity concentration under the sloped surfaces at both ends of the gate electrode and with high impurity concentration between the gate electrode and the field oxide film region. shall be provided for each.

[Effect]

In addition to the two field oxide film regions, the removed portion of the oxide film formed simultaneously between them becomes a depression for filling the gate electrode, and the field oxide film region and the gate 'i+
If impurity regions are formed by self-alignment using i as a mask, a low impurity concentration source/drain region with a concentration gradient will be created under the sloped surfaces at both ends of the gate electrode, and under the part not covered by the gate electrode. Together with the resulting high impurity concentration source/drain regions, an LDD 7i structure is formed. Therefore, there is no need to form sidewalls, and reproducibility is good.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 3 shows a method of forming a thick oxide film using the LOGO3 oxidation method. First, a thin buffer oxide film 31 with a thickness of about 400 layers is formed on a silicon substrate 1, and then a thin buffer oxide film 31 with a thickness of about 100
A 5lsNa film 32 with a thickness of 0 is grown.

Next, the portion of the 5isN4 film where a thick oxide film will be formed by photolithography is removed by dry etching or the like. The buffer oxide film 31 serves to prevent the silicon from being etched at this time. After this, 5isNa film 3
2 as a mask, steam oxidation is performed at 900° C. for about 10 hours to form an oxide film 30 with a thickness of about 8,400. At this time, a thin oxide film 33 is formed on the Si3N4 film 32. Furthermore, an oxide film is formed under the edge of the 5iJn film, creating a so-called bird's beak portion 34.

The width of the bird beak section 34 at this time is 450 people,
5i-310, the distance from the interface 35 to the bottom 36 of oxidized W430 is about 3400.

FIG. 1(5) to ffl show the source/drain region forming process in one embodiment of the present invention.
A field oxide film 3 and an intermediate oxide film region 8 are simultaneously formed using the S oxidation method, and areas other than those where elements are to be formed are covered with a photoresist I-1!19 (Figure a).

Then, by performing wet etching with HF, the silicon surface in the region where the element will be formed is exposed (Figure b
), at this time, a depression 11 is formed on the surface of the silicon substrate. Next, a gate oxide film 2 and a polycrystalline silicon film 40 for gate electrode are laminated by a normal process, and then a
A photoresist film 91 is applied for planarization using a reactive ion etching method (RIE) (Figure C). Under the condition that the etching speed of the polycrystalline silicon film 4o and the photoresist film 91 are equal, a reactive ion etching method (RIE) is applied. ) and fill in the recess 11 by an etch-back method to form a gate electrode 4 whose surface is flattened relative to the silicon substrate surface (FIG. d). As a result, the gate electrode 4 can be formed accurately in the recess from which the oxide film region 8 has been removed without requiring a gate patterning process.Next, a thermal oxide film 22 is formed on the surface by a thermal oxidation process. After the growth, ion implantation 5 for source/drain regions is performed by self-alignment using the gate oxide film 4 and field oxide film 3 as masks. At this time, the film at the end of the gate electrode 4 is Due to the thickness difference, the high impurity concentration source/drain region 7
The impurity 74 for 2 and the impurity 73 for the low impurity concentration source/drain region 71 can be introduced at the same time (Fig. e).
After this, a short heat treatment is performed at 900 tons for about 30 minutes to form a high impurity concentration region 72 after diffusion and a low impurity concentration region 71 inside it, and a subsequent low pressure CVD process reduces the thickness to about 100 mm. Then, a PSG film 10 is deposited on the surface (Fig. r).

By using such a process, the low impurity concentration source/drain regions 71 and the high impurity concentration source/drain regions 72 can be simultaneously formed in self-alignment using the gate electrode 4 and the field oxide film 3 as masks. Further, as shown in FIG. 1(f), since the channel side end of the low concentration region 71 intersects with the gate oxide film 2 at a shallow angle, deterioration in breakdown voltage due to the influence of the radius of curvature of the end of the drain region is alleviated, and the substrate The withstand voltage between the drains can be improved. Furthermore, since the upper part of the gate electrode 4 is flattened by the etch-back method, it is possible to eliminate disconnection of the M wiring in this part.

〔Effect of the invention〕

According to the present invention, a depression in the semiconductor substrate surface that is created by removing an oxide film region that is formed at the same time as a field oxide film is used as a channel region, and the depression is filled with a gate electrode material to form a surface of the semiconductor substrate. After forming a flat gate electrode, low impurity concentration and high impurity concentration source/drain regions are simultaneously formed by self-alignment using the gate electrode and field oxide film as masks.
Since the LDD structure can be formed in a simplified process with good reproducibility and the drain electric field can be relaxed, short channel effects such as impact ionization of MO8 type elements can be suppressed even in finer, highly integrated semiconductor devices. . Furthermore, by controlling the bird's beak length of the field oxide film that becomes the channel region, it is possible to optimize the concentration of the low impurity concentration region adjacent to the channel formation region, and the end of the low impurity concentration region on the channel side is connected to the gate oxide film. By intersecting at a shallow angle, deterioration in breakdown voltage due to the influence of the radius of curvature of the end of the drain region on the channel side is alleviated, which is effective in improving the breakdown voltage of an MO8 element using a very shallow junction. Furthermore, since the gate electrode portion is flattened with respect to the surface of the semiconductor substrate, it is possible to eliminate disconnection at the step of the wiring provided on the gate electrode.

[Brief explanation of drawings]

Figure 1! al to tfl are cross-sectional views sequentially showing the steps for forming source/drain regions in an embodiment of the present invention, and FIG. 3 is a cross-sectional view showing the LOGO3 oxidation method applicable to the implementation of the present invention. l: silicon substrate, 2: gate oxide film, 3: field oxide film, 4: gate electrode, 5: ions Implantation, 71: Low impurity concentration source/drain region, 72: High impurity concentration source/drain region, 8: Oxide film region, 9, 91: Photoresist film, 11: <dent.? 8. 2 to Lujist π1 ノ/<に】；＾ 7ノ〃 Figure 2

Claims (1)

[Claims] 1) Selectively oxidize the surface layer of the semiconductor substrate to provide an oxide film region between the two field oxide film regions where both ends are thinned by sloped surfaces, and remove the oxide film only in the middle region to form a depression. A gate electrode is formed to fill the depression with a flat surface, and ions are implanted using the remaining field oxide film and gate electrode as a mask to form a gate electrode with a low impurity concentration under the sloped surfaces at both ends of the gate electrode. A method of manufacturing a MOS type semiconductor device, characterized in that source and drain regions each having a high impurity concentration are provided between field oxide film regions.