JPH02125498A - High density circuit board and manufacture thereof - Google Patents
High density circuit board and manufacture thereofInfo
- Publication number
- JPH02125498A JPH02125498A JP63278730A JP27873088A JPH02125498A JP H02125498 A JPH02125498 A JP H02125498A JP 63278730 A JP63278730 A JP 63278730A JP 27873088 A JP27873088 A JP 27873088A JP H02125498 A JPH02125498 A JP H02125498A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- resin
- pad
- board
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000010410 layer Substances 0.000 claims abstract description 56
- 239000004020 conductor Substances 0.000 claims abstract description 43
- 239000011347 resin Substances 0.000 claims abstract description 42
- 229920005989 resin Polymers 0.000 claims abstract description 42
- 229910052751 metal Inorganic materials 0.000 claims abstract description 19
- 239000002184 metal Substances 0.000 claims abstract description 19
- 239000011247 coating layer Substances 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims description 16
- 239000000758 substrate Substances 0.000 claims description 14
- 238000003466 welding Methods 0.000 claims description 7
- 238000009413 insulation Methods 0.000 claims description 5
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 abstract 1
- 230000003287 optical effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 17
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000010949 copper Substances 0.000 description 9
- 238000007772 electroless plating Methods 0.000 description 9
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 239000011889 copper foil Substances 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- ZWEHNKRNPOVVGH-UHFFFAOYSA-N 2-Butanone Chemical compound CCC(C)=O ZWEHNKRNPOVVGH-UHFFFAOYSA-N 0.000 description 3
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 230000001678 irradiating effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 239000003054 catalyst Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229920000459 Nitrile rubber Polymers 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- BGTFCAQCKWKTRL-YDEUACAXSA-N chembl1095986 Chemical compound C1[C@@H](N)[C@@H](O)[C@H](C)O[C@H]1O[C@@H]([C@H]1C(N[C@H](C2=CC(O)=CC(O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O)=C2C=2C(O)=CC=C(C=2)[C@@H](NC(=O)[C@@H]2NC(=O)[C@@H]3C=4C=C(C(=C(O)C=4)C)OC=4C(O)=CC=C(C=4)[C@@H](N)C(=O)N[C@@H](C(=O)N3)[C@H](O)C=3C=CC(O4)=CC=3)C(=O)N1)C(O)=O)=O)C(C=C1)=CC=C1OC1=C(O[C@@H]3[C@H]([C@H](O)[C@@H](O)[C@H](CO[C@@H]5[C@H]([C@@H](O)[C@H](O)[C@@H](C)O5)O)O3)O[C@@H]3[C@H]([C@@H](O)[C@H](O)[C@@H](CO)O3)O[C@@H]3[C@H]([C@H](O)[C@@H](CO)O3)O)C4=CC2=C1 BGTFCAQCKWKTRL-YDEUACAXSA-N 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000003973 paint Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 239000004033 plastic Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- BFKJFAAPBSQJPD-UHFFFAOYSA-N tetrafluoroethene Chemical group FC(F)=C(F)F BFKJFAAPBSQJPD-UHFFFAOYSA-N 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
- G02B6/24—Coupling light guides
- G02B6/42—Coupling light guides with opto-electronic elements
- G02B6/43—Arrangements comprising a plurality of opto-electronic elements and associated optical interconnections
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、信号線に細い金属導体を使用し、この金属導
体をパッドに溶接固定し、かつ、シールド層を有する高
密度配線板およびその製造法に関する。Detailed Description of the Invention (Field of Industrial Application) The present invention is directed to a high-density wiring board that uses a thin metal conductor for a signal line, welds the metal conductor to a pad, and has a shield layer. Regarding manufacturing methods.
（従来の技術）
電子機器の小型化、多機能化、軽量化のために、半導体
素子の高集積化、多機能化が要求され、このような素子
の小型化とともに、それらを搭載する配線板も高密度化
、高性能化が進み、電子機器の軽量化、小型化に貢献し
てきた。(Prior art) In order to make electronic equipment smaller, more multifunctional, and lighter, semiconductor elements are required to be highly integrated and multifunctional. The density and performance of electronic devices have also increased, contributing to the reduction in weight and size of electronic devices.
従来、ＩＣのパッケージ形態としては、パンケージ本体
側面から延びた平行な２列のリードを持つＤＩＰ型パッ
ケージが主流である。このＤＩＰ型パッケージのリード
線は、約２．５鶴（１００ａｉｌｓ）間隔に配置されて
おり、これらの素子の電気的接続は、低密度な配線パタ
ーンが形成された配線板に約２．５ｍｍ間隔で配列され
内壁が金属化された貫通孔を設け、この貫通孔とＩＣパ
ッケージのリード線をはんだ等で接続することによりな
される。Conventionally, the mainstream IC package format has been a DIP package having two parallel rows of leads extending from the side surface of a pancage body. The lead wires of this DIP type package are arranged at intervals of approximately 2.5 mm (100 ails), and the electrical connections of these elements are made at intervals of approximately 2.5 mm on a wiring board on which a low-density wiring pattern is formed. This is accomplished by providing through-holes whose inner walls are metalized and connecting the lead wires of the IC package to the through-holes using solder or the like.
しかし、電子機器の小型化、軽量化、多機能化の要求は
益々増大しており、より小さなスペースに多くの素子を
搭載するようになってきているために、ＩＣチップの機
能数が増加し、パッケージ当たりのリード線の数も増加
する傾向にある。However, the demand for electronic devices to be smaller, lighter, and more multifunctional is increasing, and as more elements are being mounted in a smaller space, the number of functions of IC chips is increasing. , the number of leads per package also tends to increase.
従って、多くの接続端子を持つｔＣチップにおいて、こ
れまでのＤＩＰ型パッケージでは、チップサイズに比べ
てパッケージサイズが大きくなってしまい、部品搭載面
積がかえって増加する傾向にあった。Therefore, in a tC chip having many connection terminals, in the conventional DIP type package, the package size becomes larger than the chip size, and the component mounting area tends to increase.
そこで、これら複雑なＩＣチップに適応するような新し
いパッケージ形態が開発され、この新しいパンケージ形
態の一つにチップキャリヤと呼ばれるものがあり、この
ものは四角形であり、リード線を基板に挿入するのでは
なく、四つの側面に設けられた接続端子とそれに対応す
る基板上の接続端子をはんだ等で接続するものである。Therefore, new package formats have been developed to accommodate these complex IC chips, and one of these new package formats is called a chip carrier, which is rectangular in shape and does not allow lead wires to be inserted into the board. Rather, the connection terminals provided on the four sides are connected to the corresponding connection terminals on the board using solder or the like.
このチップキャリヤの端子間隔は約１．３ｍ＋ｗ （５
０ｍ１ｌＳ）もしくは、約０．６ ＋＋ｎ （２５ｗｉ
ｔｇ）あるいはそれ以下である。このチップキャリヤの
出現により、パッケージ面積がＤＩＰ型パッケージの場
合よりも減少したが、さらに最近では、ＴＡＢ （テー
プオートメイテッドボンディング） 、ＰＧＡ （ビン
グリッドアレイ） 、ＣＯＢ （チップオンボード）と
呼ばれるフィルムキャリヤを用いたり、基板に直接ＩＣ
チップを搭載する方法が採用されるようになり、部品接
続部が基板表面を主体にしつつある。The terminal spacing of this chip carrier is approximately 1.3m+w (5
0ml1S) or about 0.6++n (25wi
tg) or less. With the advent of this chip carrier, the package area has been reduced compared to that of DIP type packages, but more recently, film carriers called TAB (tape automated bonding), PGA (bin grid array), and COB (chip on board) have been introduced. or directly attach the IC to the board.
With the adoption of chip mounting methods, component connections are increasingly being made primarily on the surface of the board.
しかしながら、パッケージ数やパッケージ入出力端子数
の増大は、配線板の端子密度を増加させ、より高い配線
密度を必要とするため、接続端子とバイアホールを用い
た接続方法、小径貫通孔、配線導体（信号ラインに絶縁
被覆電線を用いた場合には電線の直径）の微細化などに
よって配線の高密度化が検討されている。However, an increase in the number of packages and the number of package input/output terminals increases the terminal density of the wiring board and requires higher wiring density. Increasing the density of wiring is being considered through miniaturization (the diameter of the wire when insulated wires are used for signal lines).
（発明が解決しようとする課題）
この配線の微細化において、不要な導体をエツチング除
去するサブトラクト法では、エツチング時のサイドエツ
チングによる配線導体の細り、微細な異物がエツチング
レジストと導体間に存在することによる導体の欠損など
を完全になくすことは困難であり、実用に耐える程度で
あってもそのための設備や工程の複雑さによって経済的
ではなく、現在量産的に可能な配線導体幅は、８０〜１
００μｍであるといわれている。(Problem to be solved by the invention) In the miniaturization of wiring, the subtract method for removing unnecessary conductors by etching causes thinning of the wiring conductor due to side etching during etching, and the presence of minute foreign matter between the etching resist and the conductor. It is difficult to completely eliminate defects in the conductor caused by this, and even if it is practical, it is not economical due to the complexity of the equipment and process, and the width of the wiring conductor that is currently possible for mass production is 80 ~1
It is said to be 00 μm.
また、必要な配線パターンを無電解めっきによって形成
するアディティブ法では、配線導体幅５０〜７０μｍを
形成することが可能であるが、無電解めっきを行うとき
に無電解めっき液中での銅析出による銅ぷりと呼ばれる
現象が起こり易く配線導体の短絡となるので、銅ふり現
象の起こり難い無電解めっき液や液中での析出銅を吸着
し難いめっきレジストの開発が必要である。In addition, with the additive method of forming the necessary wiring pattern by electroless plating, it is possible to form a wiring conductor width of 50 to 70 μm, but when performing electroless plating, copper deposition in the electroless plating solution Since a phenomenon called copper bulge is likely to occur, resulting in a short circuit in the wiring conductor, it is necessary to develop an electroless plating solution that is less likely to cause the copper bulge phenomenon and a plating resist that is less likely to adsorb deposited copper in the solution.
さらに、必要な配線に絶縁電線を用いたマルチワイヤー
配線板では、絶縁基板の上に絶縁電線を固定するための
接着剤を塗布し、絶縁電線を超音波振動する布線針によ
ってその接着剤に固定し、接続の必要な箇所に絶縁電線
を切断し絶縁基板を貫通する孔を明け、その孔内壁を金
属化して表裏の絶縁電線若しくは内層の配線導体と接続
しているため、絶縁電線に加わる機械力例えば布線針の
超音波振動、布線するために絶縁電線を布線方向と反対
方向に加える機械力、隣接する絶縁電線と交差させるた
めに双方の絶縁電線に加わる機械力や貫通孔での接続面
積の確保のために絶縁電線の直径は０．０６ｍｍ以下と
することができないという制限があり、また、布線する
ために必要となる布線針の寸法の制限のために隣接する
絶縁電線との間隔が０．２ｍｍ以上にできないという制
限がある。Furthermore, in multi-wire wiring boards that use insulated wires for the necessary wiring, an adhesive is applied to the insulated substrate to fix the insulated wires, and the insulated wires are attached to the adhesive using a wiring needle that vibrates ultrasonically. The insulated wire is fixed and cut at the point where connection is required, a hole is made through the insulated substrate, and the inner wall of the hole is metalized and connected to the insulated wire on the front and back sides or the wiring conductor on the inner layer. Mechanical force, such as ultrasonic vibration of a wiring needle, mechanical force applied to an insulated wire in the opposite direction to the wiring direction for wiring, mechanical force applied to both insulated wires to cross an adjacent insulated wire, or a through hole. There is a restriction that the diameter of the insulated wire cannot be less than 0.06 mm in order to secure the connection area at the adjacent There is a restriction that the distance from the insulated wire cannot be greater than 0.2 mm.
また、以上に説明したどの配線板においても、配線導体
の間隔を縮めると、隣接する配線導体間での電磁干渉に
よるクロストークが大きくなることは必至である。Furthermore, in any of the wiring boards described above, when the spacing between wiring conductors is reduced, crosstalk due to electromagnetic interference between adjacent wiring conductors inevitably increases.
このクロストークを低減した上で、さらに高密度の配線
を実現しようとすることは、前記に説明したように困難
である。As explained above, it is difficult to reduce this crosstalk and then realize higher wiring density.
本発明は、クロストークを低減し配線密度に優れた配線
板とその製造法を提供するものである。The present invention provides a wiring board that reduces crosstalk and has excellent wiring density, and a method for manufacturing the same.
（課題を解決するための手段）
本発明は、内層回路層ををする基板表面に設けたバンド
と、このパッドに溶接された絶縁被覆層を有する金属導
体と、パッドを被覆する絶縁樹脂と、この樹脂と金属導
体の絶縁被覆層と基板の表面に形成したシールド層と、
シールドを保護する樹脂層と、電子部品を搭載するため
の端子とを備えた配線板であり、以下の工程により製造
することができる。すなわち、
Ａ、内層回路を有する基板の表面にパッドを形成する工
程。(Means for Solving the Problems) The present invention provides a band provided on the surface of a substrate carrying an inner circuit layer, a metal conductor having an insulating coating layer welded to the pad, an insulating resin covering the pad, This insulating coating layer of resin and metal conductor and a shield layer formed on the surface of the board,
This is a wiring board that includes a resin layer that protects a shield and terminals for mounting electronic components, and can be manufactured by the following steps. That is, A. Step of forming pads on the surface of the substrate having the inner layer circuit.
Ｂ、パッド間に絶縁被覆層を有する金属導体をはわせ、
この導体の端末のｗＩ！、縁被覆層を除去して、パッド
に溶接する工程。B. A metal conductor having an insulating coating layer is placed between the pads,
wI of this conductor terminal! , removing the edge coating layer and welding it to the pad.
Ｃ０このパッドを絶縁樹脂で被覆後、硬イヒする工程。C0 The process of coating this pad with insulating resin and then hardening it.
Ｄ、この絶縁樹脂と金属導体の絶縁被覆層と基板の表面
にシールド層を形成する工程。D. A step of forming a shield layer on the insulating coating layer of the insulating resin and metal conductor and on the surface of the substrate.
Ｅ、シールド層の表面に樹脂層を設ける工程。E. Step of providing a resin layer on the surface of the shield layer.
Ｆ９部品搭載端子を形成する工程。Process of forming F9 component mounting terminals.
このときに、パッドを被覆する絶縁樹脂力く光硬化型絶
縁樹脂であれば、硬化のときに高し）温度力毫加わらず
基板の熱による影響を排除でき女子まし％ｚ。At this time, if the insulating resin covering the pad is a photo-curable insulating resin, the influence of the heat of the board can be eliminated without applying high temperature pressure during curing, which is better.
また、シールド層を保護する樹脂層上に基牟反表面を平
坦化するために平坦化用樹脂を設しナれｂｆ、その表面
にさらに配線導体を精密に形成することも容易となり、
好ましい。In addition, by providing a flattening resin on the resin layer that protects the shield layer to flatten the base surface, it becomes easy to form a wiring conductor precisely on that surface.
preferable.
本発明の配線板の一実施例の構造を第１図番こ示す、こ
の配線板は、内層回路Ｎ１を有する基）反２の表面に設
けたパッド３と、この）＜−）ド３に溶接された絶縁被
覆層４を有する金属導体５と、バンド３を被覆する絶縁
樹脂６と、この樹脂６と金属導体５の絶縁被覆層４と基
板２の表面に形成したシールド層７と、シールド層７を
保護する樹脂層８と、電子部品１０を搭載するためのボ
ンディング用端子９とを備えている。The structure of an embodiment of the wiring board of the present invention is shown in Figure 1. This wiring board has a pad 3 provided on the surface of the substrate 2 having an inner layer circuit N1, and a pad 3 provided on the surface of the substrate 3 having an inner layer circuit N1. A metal conductor 5 having a welded insulation coating layer 4, an insulation resin 6 covering the band 3, the insulation coating layer 4 of the resin 6 and the metal conductor 5, a shield layer 7 formed on the surface of the substrate 2, and a shield. It includes a resin layer 8 that protects the layer 7 and a bonding terminal 9 for mounting an electronic component 10.
この配線板の製造法の一実施例を、第２図（ａ）〜（ｅ
）に、製造工程順に示す。An example of the manufacturing method of this wiring board is shown in FIGS. 2(a) to (e).
) are shown in order of manufacturing process.
第２図（ａ）においては、内層回路１を有する基板２に
スルーホール１０となる孔を明け、その孔内壁を金属化
しスルーホール１０を形成し両面の導体を接続する。こ
のときに、内層回路板は、現在配線板に使用されている
材料はプラスチック、セラミック、ガラス、金属芯等す
べて使用でき、内層回路の製造についても現在配線板に
使用されている方法であって内層回路板の材料に適した
方法であればどのような方法でも使用できる。In FIG. 2(a), a hole to be a through hole 10 is made in a substrate 2 having an inner layer circuit 1, and the inner wall of the hole is metallized to form a through hole 10, and conductors on both sides are connected. At this time, the inner layer circuit board can be made of all the materials currently used for wiring boards, such as plastic, ceramic, glass, and metal cores, and the inner layer circuit can be manufactured using the same methods currently used for wiring boards. Any method suitable for the material of the inner circuit board can be used.
第２図（ｂ）では、パッド３となる部分にエツチングレ
ジストを形成して、不要の導体をエツチング除去し、そ
の表面にパッド３を形成した後、パッド３を形成した面
のエツチングレジストは除去する。このとき、裏面にも
エツチングレジスト１１をその全面に形成するが、その
エツチングレジスト１１は、裏面の導体を保護するため
に除去しない。In Fig. 2(b), an etching resist is formed on the part that will become the pad 3, unnecessary conductors are etched away, a pad 3 is formed on the surface, and then the etching resist on the surface where the pad 3 is formed is removed. do. At this time, an etching resist 11 is also formed on the entire surface of the back surface, but the etching resist 11 is not removed in order to protect the conductor on the back surface.
第２図＜ｃ＞では、溶接用針１２とパッド３との間に交
流電圧を印可し絶縁被覆層４を熱によって溶解除去し、
さらに導体５をパッド３に溶接し、光硬化性樹脂６をデ
イスペンサー１３から一定量パッド３の位置に供給しパ
ッド３を被覆した後、ライトケーブル１４から供給され
る紫外線によってその樹脂６を硬化する。このときに、
絶縁被覆層４を有する金属導体５としては、直径が２０
〜５０μｍの銅、金、アルミニウムの線、一般の線に金
めつき又は銀めっきを行った線等を用いることができる
。また、紫外線を照射する場合に、ライトケーブルのよ
うなスポットで照射するのではなく、配線板の配線パタ
ーンを形成するときに用いるような面積の大きい装置を
用いることもできる。ｔｌ接装置は、通常、半導体のチ
ップと半導体の接続端子を接続するときに広く使用され
ているワイヤボンディング装置、交流式抵抗溶接装置又
はレーザ照射装置等を用いることができる。In FIG. 2 <c>, an AC voltage is applied between the welding needle 12 and the pad 3 to melt and remove the insulating coating layer 4 with heat.
Further, the conductor 5 is welded to the pad 3, a certain amount of photocurable resin 6 is supplied from the dispenser 13 to the position of the pad 3 to cover the pad 3, and then the resin 6 is cured by ultraviolet rays supplied from the light cable 14. do. At this time,
The metal conductor 5 having the insulating coating layer 4 has a diameter of 20 mm.
A copper, gold, or aluminum wire with a thickness of ~50 μm, a gold-plated or silver-plated wire, or the like can be used. Furthermore, when irradiating ultraviolet rays, it is also possible to use a device with a large area, such as the one used when forming the wiring pattern of a wiring board, instead of irradiating it in a spot like a light cable. As the TL connection device, a wire bonding device, an AC resistance welding device, a laser irradiation device, etc., which are commonly used for connecting a semiconductor chip and a semiconductor connection terminal, can be used.
第２図（ｄ）では、露出しているこのｉ縁樹脂６と金属
導体５の絶縁被覆層４と基板２の表面に無電解めっきに
よって、導体のシールド層７を形成する。In FIG. 2(d), a conductor shield layer 7 is formed on the exposed i-edge resin 6, the insulating coating layer 4 of the metal conductor 5, and the surface of the substrate 2 by electroless plating.
このシールド層は、無電解めっきに限らず、金、銀、銅
又はカーボンの粒子を樹脂中に分散させた導電性塗料に
浸漬塗布したり、スプレーによりて吹き付けたりしても
形成することができるが、層の均一性から、めっきのほ
うが好ましく、無電解めっきのほか、薄（無電解めっき
を行った後に電解めっきを行っても形成できる。さらに
、真空蒸着法や、スパッタリング法によっても同様に形
成できる。This shield layer is not limited to electroless plating, but can also be formed by dipping or spraying a conductive paint in which gold, silver, copper, or carbon particles are dispersed in a resin. However, from the viewpoint of uniformity of the layer, plating is preferable, and in addition to electroless plating, it can also be formed by electrolytic plating after electroless plating.Furthermore, it can also be formed by vacuum evaporation method or sputtering method. Can be formed.
第２図（ｅ）では、シールド層７の表面に保護のための
樹脂層８を塗布し硬化し、さらにその表面を平滑にする
ための樹脂１６を塗布した後、ステンレス製の平板で挟
んで加熱加圧し、エツチングレジスト１１の部品搭載端
子９となる部分以外を除去した後、裏面の導体の不要な
部分をエツチング除去する。In FIG. 2(e), a protective resin layer 8 is applied to the surface of the shield layer 7 and cured, and then a resin 16 is applied to smooth the surface, and then the shield layer 7 is sandwiched between stainless steel flat plates. After applying heat and pressure to remove the portions of the etching resist 11 other than those that will become the component mounting terminals 9, unnecessary portions of the conductor on the back surface are removed by etching.
（作用）
本発明による配線板は、配線導体に絶縁電線を有するも
のであるが、配線導体の固定に接着剤を用いないので、
接着剤に固定するときに必要な絶縁電線に加わる機械力
例えば布線針の超音波振動、布線するために絶縁電線を
布線方向と反対方向に加える機械力や隣接する絶縁電線
と交差させるために双方の絶縁電線に加わる機械力がな
く、また、絶縁電線の接続がパッドとの溶接なので、そ
の接続面積は従来の絶縁電線の切断断面と比較すると広
くなり絶縁電線の直径の制限は、絶縁電線を製造すると
きの制限のみとなる。(Function) The wiring board according to the present invention has an insulated wire as a wiring conductor, but since no adhesive is used to fix the wiring conductor,
Mechanical force applied to the insulated wire when fixing it to an adhesive, such as ultrasonic vibration of a wiring needle, mechanical force applied to the insulated wire in the opposite direction to the wiring direction for wiring, or making it intersect with an adjacent insulated wire Therefore, there is no mechanical force applied to both insulated wires, and since the insulated wires are connected by welding to the pad, the connection area is wider than the cut cross section of conventional insulated wires, and the diameter limit of the insulated wires is The only restrictions apply when manufacturing insulated wires.
また、シールド層を有するので、クロストークを制限で
きる。Further, since it has a shield layer, crosstalk can be limited.
実施例
両面銅張ガラス−ポリイミド積層ＦｉＭＣＬ−Ｉ−６’
？ （日立化成工業株式会社、商品名）の表面に所望の
エツチングレジストを形成し、不要の銅箔をエツチング
除去して、内層の電源・グランド層を形成して内層回路
板とした。Example double-sided copper-clad glass-polyimide laminate FiMCL-I-6'
? (Hitachi Chemical Co., Ltd., trade name) A desired etching resist was formed on the surface, unnecessary copper foil was removed by etching, and an inner layer power supply/ground layer was formed to obtain an inner layer circuit board.
この内層回路板の表面に、ガラス−ポリイミドのプリプ
レグＣＩＡ−６７Ｎ（日立化成工業株式会社、商品名）
と厚さ１８μｍの銅箔を重ね、１８０℃、３０ｋｇ／−
の条件で、９０分間加熱加圧し、さらに２１０℃で４０
分間加熱硬化させた。A glass-polyimide prepreg CIA-67N (Hitachi Chemical Co., Ltd., trade name) is applied to the surface of this inner layer circuit board.
and 18μm thick copper foil, 180℃, 30kg/-
Heat and pressurize for 90 minutes under the conditions of
It was heated and cured for a minute.
このようにして得られた積層板の所望の箇所に直径１．
５曽翔のドリルで孔明けをし、洗浄、触媒付与、密着促
進後、無電解鋼めっきを行い、孔内壁と銅箔表面に約３
０μｍの無電解銅層を形成し、その片面のパッドの必要
な箇所と接続に必要な配線及び裏面全体にエツチングレ
ジストを形成し、−面の不要な銅箔をエツチング除去し
た。A diameter of 1 mm is placed at a desired location on the thus obtained laminate.
After drilling a hole with a 5-so-sho drill, cleaning, applying a catalyst, and promoting adhesion, electroless steel plating is applied to the inner wall of the hole and the surface of the copper foil.
A 0 μm electroless copper layer was formed, and an etching resist was formed on the necessary parts of the pads on one side, wiring necessary for connection, and the entire back side, and unnecessary copper foil on the - side was etched away.
このときに、約０．６３５＋ｕ＋ （２５ｍ１ｌｓ）の
格子点に直径０．３３５ｍｍのパッドを、約２０００個
形成した。At this time, about 2000 pads each having a diameter of 0.335 mm were formed at grid points of about 0.635+u+ (25 mls).
エツチングレジストを除去した後、エツチングされてい
ない面に、感光性レジストであるリストンＴ−１２２０
（デエポン社、商品名）をラミネートし、パッドとスル
ーホール内壁に厚さ２μｍのニッケルめっきを行い、さ
らに厚さ３μｍの金めつきを行った。After removing the etching resist, apply Riston T-1220, a photosensitive resist, to the unetched surface.
(Deepon Co., Ltd., trade name) was laminated, and the pad and the inner wall of the through hole were plated with nickel to a thickness of 2 μm, and further plated with gold to a thickness of 3 μm.
直径２０μｍの銅線に４フツ化エチレンを被覆し外径６
５μｍとした絶縁電線を、所望のバンド間に、ウェッジ
ボンド方式のワイヤボンダであるＵＳＷ−５Ｚ６０Ｓ
（超音波工業株式会社、商品名）を用いて、ボンディン
グ接続した。A copper wire with a diameter of 20 μm is coated with tetrafluoroethylene and the outer diameter is 6
A 5 μm insulated wire was connected between the desired bands using a wedge-bond type wire bonder, USW-5Z60S.
(Ultrasonic Kogyo Co., Ltd., trade name) for bonding connection.
このときに、従来の絶縁電線を用いた配線板の製造に用
いていた布線用装置の一部を使用し、基板はステップモ
ータ式の精密位置決めテーブルに固定し、絶縁電線を供
給した。At this time, a part of the wiring equipment used in the production of conventional wiring boards using insulated wires was used, the board was fixed to a step motor type precision positioning table, and the insulated wires were supplied.
溶接の条件は、前記ワイヤボンダの超音波の出力を０．
２Ｗ、発信時間を０．１秒とした。The welding conditions are as follows: the ultrasonic output of the wire bonder is 0.
2W, transmission time was 0.1 seconds.
その溶接を行った部分に、紫外線硬化型エポキシ樹脂で
あるラディキュアＲＣ２０００（日立化成工業株式会社
、商品名）を滴下し、露出した金属部分を被覆した後、
露光量３５０ｍｊ／−の紫外線を照射して樹脂を硬化さ
せた。After dripping Radicure RC2000 (trade name, Hitachi Chemical Co., Ltd.), an ultraviolet curable epoxy resin, onto the welded area to cover the exposed metal parts,
The resin was cured by irradiating ultraviolet light with an exposure amount of 350 mj/-.
ついで、フン素樹脂の表面処理液であるテトラエッチ（
潤工社、商品名）に５秒浸漬後、６０℃の温水に浸漬し
、無電解めっき用触媒であるＨ３−１０１Ｂ（日立化成
工業株式会社、商品名）に１０分間浸漬し、５分間水に
浸漬し、無電解銅めっき液）（ｉｄ−４１０（日立化成
工業株式会社、商品名）に浸漬して、約ｌＯμｍの銅シ
ールド層を形成した。Next, Tetra Etch (
Junkosha, trade name) for 5 seconds, immersed in 60°C warm water, immersed in electroless plating catalyst H3-101B (Hitachi Chemical Co., Ltd., trade name) for 10 minutes, and immersed in water for 5 minutes. Then, it was immersed in an electroless copper plating solution (id-410 (trade name, Hitachi Chemical Co., Ltd.)) to form a copper shield layer with a thickness of about 10 μm.
この表面に、シールド層保護用の樹脂として、以下の組
成の樹脂を塗布し、１６０℃で４０分間乾燥した。A resin having the following composition was applied to this surface as a resin for protecting the shield layer, and dried at 160° C. for 40 minutes.
・ニトリルゴム１Ｎ−１４３２Ｊ （日本ゼオン株式会
社、商品名）
７０部
・フェノール樹脂；Ｈ−２４００（日立化成工業株式会
社、商品名）
： ３０部
・メチルエチルケトン； （株式会社ゴードー製）８２
５０部
その後、感光性エツチングレジストを塩化メチレンに浸
漬して除去した。・Nitrile rubber 1N-1432J (Nippon Zeon Co., Ltd., trade name) 70 parts ・Phenol resin; H-2400 (Hitachi Chemical Co., Ltd., trade name): 30 parts ・Methyl ethyl ketone; (manufactured by Gordo Co., Ltd.) 82
50 parts Thereafter, the photosensitive etching resist was removed by immersion in methylene chloride.
感光性レジストであるリストンＴ−１２２０（デュポン
社、商品名）を用いて、裏面の導体表面の部品搭載用端
子と接続に必要な部分にエツチングレジストを形成し、
不要な導体部分をエツチング除去して配線板とした。Using a photosensitive resist, Liston T-1220 (DuPont, trade name), an etching resist is formed on the parts required for connection to the component mounting terminals on the back conductor surface.
Unnecessary conductor parts were removed by etching to create a wiring board.
（発明の効果）
以上に説明したように、本発明によって、以下の効果を
有する配線板とその製造法を提供することができた。(Effects of the Invention) As explained above, according to the present invention, it was possible to provide a wiring board and a method for manufacturing the same having the following effects.
（１） 従来よりも細い導体を使用することができ、
より高密度の配線ができる。(1) Thinner conductors can be used than before,
Allows for higher density wiring.
（２） シールド層によって、クロストークを低減で
きる。(2) Crosstalk can be reduced by the shield layer.
（３）絶縁電線をバッドに溶接しているので、接続の信
頼性が高い。(3) Since the insulated wire is welded to the pad, the connection is highly reliable.
（４）絶縁電線の絶縁被覆の表面にシールド層を設ける
ので、その被覆の厚さを制御することにより、配＆ｉ導
体の特性インピーダンスを制御でき（５）絶縁電線を最
短距離で配線でき、伝搬遅延を短縮できる。(4) Since a shield layer is provided on the surface of the insulation coating of the insulated wire, by controlling the thickness of the coating, the characteristic impedance of the wiring & i conductor can be controlled. Delays can be reduced.
第１図は本発明の一実施例を示す断面斜視図、第２図（
ａ）〜（＋）は本発明の一実施例を説明するための製造
工程における断面図である。
符号の説明
１、内層回路層 ２．基板
３、パッド ４．絶縁被覆層
５、金属導体 ６．絶縁樹脂
７、シールド層 ８．１Ｍ脂層
９、部品搭載用端子
１０、スルーホール
１１、 レジスト
１２、溶接針
１３、デイスペンサ
１４、ライトケーブル
（Ｃ）
第２図FIG. 1 is a cross-sectional perspective view showing one embodiment of the present invention, and FIG. 2 (
a) to (+) are cross-sectional views in a manufacturing process for explaining one embodiment of the present invention. Explanation of symbols 1. Inner circuit layer 2. Substrate 3, pad 4. Insulating coating layer 5, metal conductor 6. Insulating resin 7, shield layer 8.1M fat layer 9, component mounting terminal 10, through hole 11, resist 12, welding needle 13, dispenser 14, light cable (C) Fig. 2
Claims (4)
のパッドに溶接された絶縁被覆層を有する金属導体と、
パッドを被覆する絶縁樹脂と、この樹脂と金属導体の絶
縁被覆層と基板の表面に形成したシールド層と、シール
ドを保護する樹脂層と、電子部品を搭載するための端子
とを備えたことを特徴とする高密度配線板。1. A pad provided on the surface of a substrate having an inner circuit layer, a metal conductor having an insulating coating layer welded to the pad,
It is equipped with an insulating resin that covers the pad, an insulating coating layer of this resin and a metal conductor, a shield layer formed on the surface of the board, a resin layer that protects the shield, and a terminal for mounting electronic components. Features a high-density wiring board.
製造法。 Ａ．内層回路を有する基板の表面にパッドを形成する工
程。 Ｂ．パッド間に絶縁被覆層を有する金属導体をはわせ、
この導体の端末の絶縁被覆層を除去して、パッドに溶接
する工程。 Ｃ．このパッドを絶縁樹脂で被覆後、硬化する工程。 Ｄ．この絶縁樹脂と金属導体の絶縁被覆層と基板の表面
にシールド層を形成する工程。 Ｅ．シールド層の表面に樹脂層を設ける工程。 Ｆ．部品搭載端子を形成する工程。2. A method for manufacturing a high-density wiring board, comprising the following steps. A. A process of forming pads on the surface of a substrate having inner layer circuits. B. A metal conductor with an insulating coating layer is placed between the pads,
The process of removing the insulation coating layer from the terminal of this conductor and welding it to the pad. C. The process of coating this pad with insulating resin and then curing it. D. A step of forming a shield layer on the insulating coating layer of the insulating resin and metal conductor and on the surface of the board. E. A process of providing a resin layer on the surface of the shield layer. F. Process of forming component mounting terminals.
ることを特徴とする請求項１記載の高密度配線板。3. 2. The high-density wiring board according to claim 1, wherein the insulating resin covering the pad is a photocurable insulating resin.
するために平坦化用樹脂を設けたことを特徴とする請求
項１記載の高密度配線板。4. 2. The high-density wiring board according to claim 1, wherein a flattening resin is provided on the resin layer for protecting the shield layer in order to flatten the surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63278730A JPH02125498A (en) | 1988-11-04 | 1988-11-04 | High density circuit board and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63278730A JPH02125498A (en) | 1988-11-04 | 1988-11-04 | High density circuit board and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02125498A true JPH02125498A (en) | 1990-05-14 |
Family
ID=17601402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63278730A Pending JPH02125498A (en) | 1988-11-04 | 1988-11-04 | High density circuit board and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02125498A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006310629A (en) * | 2005-04-28 | 2006-11-09 | Shinko Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| DE112010000683T5 (en) | 2009-02-02 | 2012-10-31 | Mitaka Kohki Co., Ltd. | Method and apparatus for non-contacting surface measurement |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5848379A (en) * | 1981-09-01 | 1983-03-22 | バデイム・バシリエビツチ・ムクキン | Method of forming conductor connecting part |
| JPS6127697A (en) * | 1984-07-18 | 1986-02-07 | 日本シイエムケイ株式会社 | One-side printed circuit board and method of producing same |
-
1988
- 1988-11-04 JP JP63278730A patent/JPH02125498A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5848379A (en) * | 1981-09-01 | 1983-03-22 | バデイム・バシリエビツチ・ムクキン | Method of forming conductor connecting part |
| JPS6127697A (en) * | 1984-07-18 | 1986-02-07 | 日本シイエムケイ株式会社 | One-side printed circuit board and method of producing same |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006310629A (en) * | 2005-04-28 | 2006-11-09 | Shinko Electric Ind Co Ltd | Semiconductor device and its manufacturing method |
| JP4589170B2 (en) * | 2005-04-28 | 2010-12-01 | 新光電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| DE112010000683T5 (en) | 2009-02-02 | 2012-10-31 | Mitaka Kohki Co., Ltd. | Method and apparatus for non-contacting surface measurement |
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